JP2013036903A - Fault spot estimation system, fault spot estimation method and program for fault spot estimation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an increase in test time, facilitate fault diagnosis of scan chain and reduce fault diagnosis time for fault spot estimation.SOLUTION: A system for narrowing a range of fault on a scan chain comprises: means 24 for narrowing a fault candidate scan FF with both of a test pattern in a bypass test mode and a test pattern in a compression test mode; means 23 for identifying a fault scan chain in the compression test mode from a difference in a scan chain structure between the compression test mode and the bypass test mode, and storing the identified scan chain into a storage unit; means 27 for converting a range of fault candidate in the bypass test mode into a range of scan FF in the compression test mode; and means 25 for using the test pattern in the compression test mode to apply fault simulation to the scan chain including the fault candidate, conducting collation with a test result in the compression test mode and outputting a collation result to an output device.

Description

  The present invention relates to a failure diagnosis technique, and more particularly, to a failure location estimation system, a failure location estimation method, and a failure location estimation program.

  As the semiconductor integrated circuit (logic circuit) is increased in scale, miniaturized, and multi-layered, it is difficult to physically identify the failure location. It is important to narrow down the failure location in advance before physical analysis. As one of the prior narrowing methods, a logical failure diagnosis method is used in a scan design circuit (scan circuit) incorporating a test circuit (scan chain). In the scan test mode, a plurality of scan flip-flops (abbreviated as “scan FF”) provided in the LSI circuit are serially connected to form a test circuit (scan chain), and an external scan input ( A pattern is supplied serially from a (Scan In) terminal (load), a pattern is applied in parallel from a plurality of scan FFs whose outputs are connected to the inputs of the logic circuit to be inspected, and inputs are connected to the outputs of the logic circuit The output of the logic circuit is captured by a plurality of scan FFs, the output of the plurality of scan FFs is serially output (unloaded) from an external scan-out (Scan Out) terminal, and the output pattern is captured by an LSI tester. Compare with pattern.

  The logical fault diagnosis method is based on the assumption that the scan chain of the scan circuit operates normally, and the input / output expected value of the scan chain and the test result (logic test result) using the scan chain obtained from the tester. Then, the failure location of the logic part to be tested is estimated using circuit design information. This diagnosis is called “logic failure diagnosis”.

  If the scan chain itself is faulty, it will be affected by the fault at the time of data input (load operation) and at the time of data output (unload operation), so the input value to the logic circuit is different from the expected input value, and Since the output value of the scan chain does not indicate the logic test result as it is, a normal logical failure diagnosis method cannot be used. In view of this, a logical failure diagnosis (scan chain failure diagnosis) system for identifying a failure location on the scan chain has been developed. Recently, the proportion of scan chains (number of chains, chain length) occupying the logic circuit has increased, and along with this, the proportion of samples (SC failure samples) in which the scan chain itself malfunctions tends to increase. For this reason, the importance of scan chain fault diagnosis is increasing.

  In recent years, the number of scan circuits incorporating a compression circuit in which a scan chain is compressed is increasing in order to shorten the test time. A plurality of scan chains in the circuit are compressed by bundling test results using a compression circuit, and output as test results for one scan chain. In the test using the compression circuit, a plurality of scan chains are tested at the same time, so that the test time can be shortened compared to the test not using the compression circuit.

  However, in the failure diagnosis, it is necessary to replace the test result by the LSI tester or the like with a failure detection location (referred to as “failure scan FF”) on the scan chain inside the semiconductor integrated circuit. That is, it is necessary to assign the fail information of the test result to the scan FF on the scan chain. If the test results are compressed, multiple assumptions will occur when the test results are replaced with fault detection locations on the scan chain (multiple assumptions regarding which of the multiple scan chains will be faulty, etc.) The number of failure candidates in the diagnosis result increases. For this reason, failure diagnosis often uses fail information from an uncompressed test.

  If the scan circuit incorporated in the device is defective, the device is always affected by the failure location of the scan circuit during data loading and unloading operations. As a result, in the device test, the number of failures due to defective scan circuits may increase more than the failure of the original logic part (logic circuit) to be inspected. Along with this, the test time and the capacity of the output file (log) for storing fail information increase. As a result, the processing time for scan chain failure diagnosis performed after the failure of the device also becomes longer. For this reason, it is generally avoided to use a test result using a compression circuit for failure diagnosis.

  From the above, it is desired to establish a failure diagnosis method (system) that can shorten the test time and specify the failure scan chain.

  The operation of the scan circuit (uncompressed scan circuit), the difference from the compressed scan circuit, and the influence of the failure on the scan chain will be described below.

  The test of the scan circuit using the compressor is called “compression test mode”. The test of the scan circuit that does not use the compressor is called “bypass test mode”. In addition, the test pattern used in each mode test (including an activation (input) pattern applied to the device under test and an expected value pattern compared with the output pattern from the device under test for the activation (input) pattern. ) Is composed of a plurality of test vectors. A test vector is a minimum unit of a series of operation flow from data input, operation execution to data output.

  Hereinafter, the terminology relating to the scan circuit and the operation of the normal scan circuit in the bypass test mode will be described with reference to FIG. FIG. 9 is a diagram schematically showing a scan circuit in the bypass test mode. FIG. 9 illustrates a scan circuit in which one scan chain exists, the outer solid line represents the entire circuit, and the dotted line in the circuit represents the scan chain. The scan chain includes a scan FF, a signal line, and a cell. In FIG. 9, a square on the broken line represents a scan FF, and a User circuit (combination circuit) in which a rectangular portion surrounded by a dotted line is divided by a scan chain is a test target circuit.

  In the bypass test operation, a pattern value is input and transferred from the scan FF upstream of the scan chain (scan input terminal SIN side) (shift-in), and the value is sequentially set to each scan FF (load operation).

  Thereafter, a system clock (capture clock) is applied, and data is applied to the input of the User circuit (combinatorial logic circuit). The output of the User circuit is taken into a scan FF at the latter stage of the User circuit (capture operation).

  By outputting (shifting out) the state value taken into the scan FF from the scan FF on the downstream side (SOUT side) of the scan chain (unload operation), internal information of the User circuit (combining logic circuit) is obtained. Can do.

  This normal operation of the scan circuit is referred to as “logic section operation test”. A pattern for executing this operation is referred to as a “logic unit operation test pattern”. A test in which the capture operation is excluded from the logic unit operation test is referred to as a “scan chain operation confirmation test”. This is a test for confirming that data is normally applied and output on the scan chain. A pattern for executing this operation is referred to as a “scan chain operation check test pattern”.

  When the scan chain is normal and a failure exists in the User circuit (test target circuit), the correct state value is set in the scan chain by the load operation, and the error state resulting from the failure in the User circuit is propagated by the capture operation Then, the error behavior caused by the failure in the User circuit can be obtained as a result of the bypass test mode by taking in the scan FF (F1, F2, F3, and F4 in FIG. 9) and performing the unload operation.

  Next, the operation of the compression test mode and the features and advantages of the compression test mode will be described with reference to FIG. In the operation of the compression test mode, data is expanded by the expander corresponding to the number of internal scan chains from the number of external input terminals at the time of shift-in.

  In the example of FIG. 10, a test pattern is input from the tester to the SIN terminal. The three chains 1-1 to 1-3 are developed, and the patterns are shifted into the respective scan chains. Next, the capture operation is executed to propagate the error state resulting from the failure in the User circuit. 1-1 scan FF (F1, F2 in FIG. 10), scan chain No. The data are taken into the scan FFs 1-2 and 3 (F3 and F4), respectively. After that, at the time of shift-out, the shift-out results of the three scan chains of chains No. 1-1 to No. 1-3 are input to the compressor, and the compressor compresses them to the number of external output terminals (SOUT) and displays the test results. Output to a tester.

  The bypass test mode and the compression test mode differ in how the scan chains are connected, and the number of chains and the chain length differ, but the same scan FFs used for the scan chains are used in the two test modes. Although not particularly limited, a semiconductor device including a decompressor and a compressor and having a compression test mode function is normally configured to be switchable to a test in the bypass test mode.

  In the compression test mode, by using a decompressor and a compressor, it is possible to set and test data in more scan chains than external terminals. That is, the number of scan chains increases as compared to the bypass test mode. In addition, the chain length of each scan chain is shortened.

  For example, in the bypass test mode of FIG. 9, one scan chain has a chain length of 7 bits (seven serially connected scan FFs), but in the compression test mode of FIG. 10, the chain is composed of three scan chains. The length is 2 or 3 bits. The test time depends on the number of shifts of a shift register composed of serially connected scan FFs. In the compression test mode, the test time is shortened as the chain length is shortened.

  In the logic fault diagnosis, a fault location is estimated by a method of performing a fault simulation or a method of tracing a fault propagation path using the test result, scan circuit configuration information, an expected value of a signal line, and the like.

  As a precondition for logic fault diagnosis, the state value (test pattern) is correctly set in the scan FF during the load operation in the test, and the state value (the output value of the User circuit) captured in the scan FF during the unload operation is It must be output without being affected by a failure on the scan chain.

  If a fault exists on the scan chain, the logical value that has passed through the fault location during the scan shift is affected by the fault. In the load operation, a value passing through the failure location is set in the scan FF located downstream of the failure location. For this reason, a correct value cannot be set for the scan FF downstream of the failure location. In the unload operation, the logical value of the scan FF upstream of the failure location passes through the failure location and is shifted out, so the logical value held by the scan FF may not be output as it is. When the output of the FF at the failure location is a Stuck at-1 failure, the value 0 of the upstream scan FF is all replaced with the value 1 when shifted out. In this case, the logic fault diagnosis based on the assumption that the scan chain is operating normally cannot be applied.

  However, an actual product failure may exist on the scan chain, and it is necessary to narrow down the failure location on the scan chain in the failure diagnosis of the semiconductor integrated circuit (semiconductor device) determined to be defective. .

  As a failure location estimation system that estimates a failure on a scan chain in a scan design circuit, for example, the failure location estimation method of Patent Document 1 can be used. This system tests a defective product with a specific logic unit operation test pattern for the one that has been confirmed as a single scan chain failure among the failed logic circuits in the test chain operation confirmation test pattern. This is a failure location estimation system that narrows down the failure range of the failure scan FF from the obtained test results and then specifies the failure location in detail by failure simulation.

  Hereinafter, in the logic (logic circuit) failure diagnosis, a candidate obtained by first narrowing down is called a “primary failure candidate”, and a candidate finally obtained by failure simulation is called a “final failure candidate”.

  A phenomenon and a definition of terms when a failure occurs on the scan chain will be described with reference to FIG. FIG. 11 shows a scan chain including 10 scan FFs for the sake of simplicity. Index numbers are assigned to the scan FFs in order from the SOUT side. In this example, Index numbers 0-9 are assigned. When attention is paid to a certain scan FF, the SIN side of the scan FF is referred to as “upstream” and the SOUT side is referred to as “downstream”. For example, there are scan FFs 6, 7, 8, 9 upstream of the scan FF 5 in FIG. 11, and scan FFs 4, 3, 2, 1, 0 downstream. The focused scan FF itself may be included downstream.

  In FIG. 11, the serial test pattern from the scan input terminal SIN is input from the scan FF on the scan input terminal SIN side and sequentially shifted in synchronization with the scan clock signal to input a value (apply a state value). This is called “load operation”. Outputting the value of the scan FF from the scan output terminal SOUT is called “unload operation”. “Load” is also referred to as “scan-in” or “shift-in”. “Unload” may be referred to as “scan-out” or “shift-out”. During the load / unload operation, the state value on the scan chain is scan-shifted from the scan input terminal SIN toward the scan output terminal SOUT.

  As the notation method of the load operation and the data (set value) of the load operation, logical values are listed from the scan FF close to the scan input terminal SIN. For example, in the case of {00110011}, the left end represents data on the scan input terminal SIN side, and the right end represents data on the scan output terminal SOUT side.

The scan chain operation check test using the scan chain operation check test (also called “flash test” or “scan check”) is used to check whether the scan chain is operating normally.
{00000000} (all-0),
{11111111} (all-1),
{00110011}
A test vector having a special pattern such as the above is applied, the capture operation is not performed, and the state value is output as it is by the unload operation.

  In the scan chain operation check test, when the operation is normal (when no defect is detected), the capture operation is not performed, so the data loaded from the tester to the scan input terminal SIN is directly output from the scan output terminal SOUT as it is. . On the other hand, when there is a fault on the scan chain (when the scan chain does not operate normally), the value of the data loaded from the tester to the serial input terminal SIN and the data output serially from the serial output terminal SOUT are different. For this reason, a fault scan chain can be specified.

  Here, the scan chain defective operation is considered to be divided into a fixed failure and an indefinite failure. The scan chain fixed failure is a state in which all output values of the obtained test results are fixed to ‘0’ or ‘1’ even if any test vector is applied in the scan chain operation check test. When the output value is fixed to “0”, the failure type is referred to as “stack-at 0 failure” on the scan chain. When the output value is fixed to “1”, the failure type is referred to as “stack-at 1 failure” on the scan chain.

  The scan chain indefinite failure is a state in which a fail signal is detected regardless of whether the output value of the test result in the scan chain operation check test is ‘0’ or ‘1’.

  FIG. 12 is a diagram for explaining the configuration disclosed in Non-Patent Document 1. An input device 1 having an interface unit with a tester, a keyboard, or the outside, a data processing device 2 that operates by program control, a storage device 3 that stores information such as a hard disk and a memory, and a display device that is an interface unit with the outside And an output device 4 such as a printing device. With reference to FIG. 12, each component and each execution means will be described. Refer to Non-Patent Document 1 for details.

  The storage device 3 includes a test result storage unit 31 that stores a test result acquired by a tester, a logic circuit information storage unit 32 that stores net list information, test pattern information, scan chain information, and test result information of a logic circuit, A fault scan chain storage unit 33 that stores a fault scan chain and a fault type; a fault candidate scan FF storage unit 34 that stores a fault candidate scan FF number, a signal line name on the scan chain, and a branch position number of the signal line; Is provided.

  Execute the pass / fail test with the test pattern for the suspicious circuit using the existing tester, identify the fault scan chain and the fault type using the test result of the scan chain operation check test pattern in the test pattern, and test pattern Using the test result of the logic unit operation test, the expected value of each scan FF is compared with the test result of the defective product to narrow down the range (primary candidate) where the possibility of failure scan FF is high, and failure candidates For each branch of the signal line, a scan chain fault simulation is executed, collated with the test result, and the collation result is output.

  In the test result acquisition means 21 of FIG. 12, using the LSI test apparatus 5 such as a tester or a DFT (Design For Testability) tester, “0000”, “1111”, “0101” for all scan chains of the suspicious sample. , A specific logical value such as “0011” or “000111” is repeated, a scan chain operation confirmation test for outputting the result as it is, and a logic part operation test for the suspected sample are executed, and the result is stored in the test result storage unit 31. Remember.

  For example, if a stuck-at fault exists on the scan chain, about half of the scan FFs on the scan chain may have a fault value. Recently, as the logic circuit, a product having an uncompressed test mode and a scan chain length of, for example, 10,000 bits or more generally exists. In such a product (semiconductor device), when a scan chain failure occurs, the test time is prolonged and the output file capacity is increased.

  The diagnosis initial setting means 22 reads the suspect sample netlist information, test pattern information, scan chain information and test result information, and sets predetermined information.

  Next, the fault scan chain specifying means 23 specifies the scan chain in which the fault has occurred based on the test result of the scan chain operation confirmation test of the test result acquisition means 21, and outputs the output value of the specified fault scan chain. The failure type is specified by comparison with the expected output value, and the failure scan chain information and the failure type information are stored in the failure scan chain storage unit 33.

  In the case of the bypass test mode, the failure scan FF narrowing means 24 uses the failure scan chain and the failure type stored in the failure scan chain storage unit 33, as shown in FIG. The output value of each scan FF obtained from the logic part operation test result of the suspicious sample is compared to narrow down primary fault candidates and store them in the fault scan chain storage unit 33. At this time, the method of narrowing down the failure scan FFs may be, for example, using the continuity of the same logic, from the most downstream (SOUT) side scan FF where the same logic starts to the most upstream (SIN) side scan FF. .

  Further, by making the input value at the time of shift-in the same value as the failure value, the influence of the failure at the time of shift-in is canceled and the range of the failure may be narrowed down by shifting out.

  In the compression test mode, the fault scan FF narrowing means 24 estimates all the internal scan chains estimated from the external scan chain as primary fault candidates and stores them in the fault scan chain storage unit 33.

  In the scan chain failure simulation checking means 25, the failure candidate scan FF ranges estimated by the diagnosis initial setting means 22 and the failure scan FF narrowing means 24 are determined according to the failure type specified by the failure scan chain specifying means 23, respectively. As a result, a scan chain failure simulation is executed, the failure simulation result is compared with the test result of the defective product, and a portion having the highest coincidence rate is output as a final failure candidate.

  FIG. 13 is a flowchart showing the failure diagnosis operation of the related technology of FIG.

  The test result acquisition unit 21 acquires the test result of the device (A1).

  The diagnosis initial setting means 22 performs initial setting (A2).

  The fault scan chain specifying unit 23 specifies the fault scan chain and the fault mode (A3).

  In the bypass test mode (no branch of determination “compression?” In FIG. 13), the fault scan FF narrowing means 24 narrows down the range of fault scan FFs (A4).

  In the scan chain fault simulation checking means 25, a fault is assumed for the range of fault candidate scan FFs estimated by the fault scan FF narrowing means 24 according to the fault type specified by the fault scan chain specifying means 23, and the scan chain fault is detected. Check with simulation results.

  In the case of the compression test mode, when a failure cannot be identified in the failure scan FF narrowing means 24 (no branch of determination “specific?” In FIG. 13), the scan chain failure simulation collating means 25 collates with the result of the failure simulation.

  FIG. 14B schematically shows a scan chain operation confirmation test pattern in the bypass test mode and an operation at the time of a test with a defective product. Assume that there is a “stack-at1 failure” at the location indicated by the dashed arrow in the scan chain of the scan chain test, “defective product”. The values in the three rows (seven boxes each) in the “defective product” indicate the scan FF (value). The upstream side of the fourth scan FF from the downstream of the second row of the right output pattern is set to 1, and it is estimated that a fault exists upstream of the scan FF.

  FIG. 14A shows a simulation result (a pattern under “Unload” on the right side) when the pattern shown under “Unload” on the left side is input. Note that the pattern X is a pattern for masking the compare, and thus may be either 1 or 0 (that is, the “Do n’t Care” pattern).

  In the compression test mode, as shown in FIG. 15, the output value is output as a value compressed by the output value of the normal scan chain and the output value of the fault scan chain. For this reason, it is difficult to uniquely specify the state value of each scan FF in the compressed scan chain. Therefore, the scan chain fault diagnosis in the compression test mode needs to be estimated on the assumption that the fail information is masked by the compressor even for the passed scan FF in order to narrow down the failure range of the primary candidates. Diagnosis is complicated. Actually, since the number of assumptions is enormous, practical narrowing down is impossible.

  In FIG. 15B, in the compression test mode, the values in the three rows (seven) boxes between the expander and the compressor in the “defective product” are the scan FFs of the three scan chains. The value of is shown. It is assumed that there is a “stack-at1 failure” at a location (fourth from the downstream) indicated by a broken line arrow in the center of the “defective product”. The upstream side of the fourth scan FF from the downstream of the pattern output from the compressor is affected by the failure point (stuck-at1 failure) of the central scan chain, but as a result of being compressed by the compressor Therefore, even if compared with the expected output value (the simulation output pattern of FIG. 15A), it cannot be determined that there is a failure.

  In the compressor, when the values of the three scan FFs of the corresponding stages input from the three scan chains are the same, 0 or 1 is different, or 1 or X (compare mask) is present. , X is output.

  Note that Patent Document 1 and the like are also referred to in connection with scan chain failure diagnosis.

JP 2010-286383 A

Funatsu et al., “Improvement of diagnostic accuracy of scan chain fault diagnosis method”, LSI Testing Symposium 2009, Nov. 2009

  The analysis of related technology is given below.

(A) When a test is performed on a device under test with a defective scan chain in the compression test mode, fail information on a plurality of scan chains is compressed. May not be output. For this reason, in failure diagnosis using test results, primary failure candidates cannot be narrowed down, and for example, a plurality of scan chains may all become failure candidates. In this case, the number of failure simulations increases, and failure diagnosis in a practical time is difficult.

(B) When the bypass test mode is executed for a device under test having a scan chain defect, the chain length is long. For this reason, the time (number of times) of failure simulation at the time of scan chain failure diagnosis increases, and the diagnosis time becomes longer.

(C) When the bypass test mode is executed for a device under test having a scan chain defect, the number of scan FFs per scan chain is larger than that in the compression test mode. For this reason, the number of scan FFs to fail per scan chain increases, and the capacity of an output file that stores a log of fail information for failure diagnosis (fail log) increases. As a result, the test time becomes longer. As a result, it is not easy to obtain a fail log for diagnosis in a practical time.

  In order to solve at least one of the above problems, according to the present invention, the following configuration is generally used (but is not limited to the following).

According to the present invention, there is provided a failure location estimation system that narrows down a failure range on a scan chain from fail information of a scan chain test result composed of a scan flip-flop, and a test pattern for scan chain failure diagnosis in a bypass test mode. Scan chain diagnostic pattern creation means for creating and storing in the storage unit,
Fault scan / flip-flop narrowing means for narrowing down fault candidate scan flip-flops from test results in both the scan chain fault diagnosis test pattern in the bypass test mode and the scan chain test pattern in the compression test mode; ,
Compared with the test results using the test pattern for the scan chain in the compression test mode, the fault scan chain in the compression test mode is identified and stored in the storage unit based on the difference in the scan chain structure between the compression test mode and the bypass test mode. Fault scan chain identification means to perform,
A failure scan flip-flop compression conversion means for converting the range of failure candidates in the bypass test mode into the range of scan flip-flops in the compression test mode based on the correspondence relationship between the scan flip-flops in the bypass test mode and the compression test mode;
Scan chain fault simulation that uses the test pattern of the compressed test mode to perform fault simulation of the scan chain that includes the scan flip-flops of the fault candidates, collates with the test result in the compressed test mode, and outputs the collation result to the output device And a failure location estimation system including a verification unit.

According to the present invention, the failure location estimation system that narrows down the failure range on the failure scan chain from the fail information of the scan chain test result composed of the scan flip-flop includes the scan chain information between the bypass test mode and the compression test mode. And calculating a correspondence relationship between the scan flip-flops in the bypass test mode and the compression test mode,
First and second scan flip-flops positioned at the input and output ends of the scan chain in the compression test mode, and a bypass test mode corresponding to predetermined bits before and after the first and second scan flip-flops Identify the scan flip-flop number on the scan chain
For the test pattern in the bypass test mode, an output value is set in the scan flip-flop that specifies the number, and scan flip-flops other than the predetermined bits before and after the first and second scan flip-flops are set. A scan chain diagnostic pattern creating means for setting the output value to a value masking comparison with the expected value and storing it as a test pattern for scan chain fault diagnosis;
Test result acquisition means for acquiring a test result of a scan chain by the test pattern for scan chain failure diagnosis and storing it in a test result storage unit;
Initial setting means for reading circuit design information and test results, and for initial setting of fault diagnosis,
Comparing the output value of the scan flip-flop obtained from the test result by the test pattern for the scan chain fault diagnosis and the expected output value, the fault scan chain and the fault type in the bypass test mode are specified, and the fault scan chain is stored. Fault scan chain specifying means to be stored in the unit,
Each scan flip-flop is referred to by using a fault scan chain and a fault type stored in the fault scan chain storage unit with reference to a test result of the logic part of the test pattern for scan chain diagnosis stored in the test result storage unit By comparing the expected output value of the group and the output value of each scan flip-flop obtained from the test result of the logic unit, the primary fault candidates are narrowed down, and the fault scan flip-flops are stored in the fault scan chain storage unit Means,
By referring to the range of scan flip-flops of primary failure candidates in the bypass test mode and the scan flip-flop correspondence information, the scan flip-flops in the compressed test mode corresponding to the scan flip-flops in the bypass test mode The fault scan flip-flop compression conversion means for converting into the fault information, rewriting the primary fault candidate in the bypass test mode to the primary fault candidate in the compression test mode, and storing it in the fault scan chain storage unit;
If the signal line between the scan flip-flops is branched according to the failure type with respect to the range of the primary failure candidates rewritten by the failure scan flip-flop compression conversion means, before and after the branch as failure candidates Assuming that each fault is distinct, scan chain fault simulation is performed using the test pattern in the compressed test mode, and the fault simulation result is compared with the test result in the compressed test mode. And a scan chain fault simulation verification means for outputting the signal line together with the fault type,
An output device that receives an output from the scan chain fault simulation verification means and outputs the fault scan chain, the fault scan flip-flop, the fault type, a fault signal line, and a fault branch position of the fault signal line With.

  According to the present invention, it is possible to suppress an increase in test time, facilitate scan chain failure diagnosis, and shorten failure diagnosis time for failure location estimation.

It is a figure which shows the structure of one Embodiment of this invention. It is a flowchart which shows the procedure of one Embodiment of this invention. It is a figure which shows the structural example of the scan chain diagnostic pattern preparation means in one Embodiment of this invention. It is a figure explaining operation | movement of the scan chain diagnostic pattern preparation means in one Embodiment of this invention. It is a figure which shows typically the example of a scan chain circuit. (A) is a scan chain configuration in bypass test mode, (B) is an expected output value, and (C) is a diagram showing an output value. 3 is a diagram showing a configuration of a failure scan FF compression conversion means 27. FIG. It is a figure which shows typically the scan FF conversion from a bypass test mode to a compression test mode. It is a figure which shows typically the logic circuit which a failure generate | occur | produced in bypass test mode. It is a figure which shows typically the scanning circuit of a compression test mode. It is a figure explaining the phenomenon when a failure arises on a scan chain, and the definition of a term. It is a figure which shows the structure disclosed by the nonpatent literature 1 as related technology. 13 is a flowchart for explaining a failure diagnosis operation of the related technique of FIG. 12. (A) is a simulation in the bypass test mode, (B) is a diagram schematically showing the operation during the test in the bypass test mode. (A) is a simulation in compression test mode, (B) is a figure which shows typically operation | movement at the time of the test in compression test mode. It is a figure which shows the structural example of the scan chain failure simulation collation means in one Embodiment of this invention.

  An embodiment of the present invention will be described. According to a preferred embodiment, a test pattern for scan chain fault diagnosis is created in the bypass test mode, and the test is performed using both the test pattern for scan chain fault diagnosis and the test pattern for scan chain in the compressed test mode. From the test results of the scan chain failure diagnosis test pattern, the failure candidate scan FFs are narrowed down, and compared with the test result using the test pattern for the compression test mode scan chain, in the compression test mode and the bypass test mode. The failure scan chain in the compression test mode is identified from the difference in the scan chain structure, the range of the failure candidate scan FF of the failure scan chain is narrowed down, and the compression test mode Test pattern There running fault simulation of the scan chain, and outputs the collating result by matching the test results.

  FIG. 1 is a diagram showing a configuration of an embodiment of the present invention. Input device with interface unit with keyboard or outside, data processing device operated by program control, storage device for storing information such as hard disk and memory, display device and printing device as interface unit with outside, etc. Output device. With reference to FIG. 1, each component and each execution means will be described. The storage device 3 includes a test result storage unit 31 that stores a test result obtained by a tester (not shown), and a logical circuit information storage that stores net list information, test pattern information, scan chain information, and test result information of the logic circuit. Unit 32, fault scan chain storage unit 33 for storing fault scan chain information and fault type information, fault candidate scan storing fault candidate scan FF number, signal line name on scan chain, and branch position number of signal line FF storage unit 34.

  The scan chain diagnostic pattern creation means 26 is based on the netlist information, the scan chain configuration information in the bypass test mode, and the scan chain configuration information in the compression test mode, and the scan FF information in the bypass test mode and the scan FF information in the compression test mode. Is created and stored. Then, the scan chain diagnostic pattern creation means 26 connects the scan FF on the most SIN side (scan FF whose input terminal is connected to SIN) and the scan FF on the most SOUT side (output terminal is connected to SOUT) of each scan chain in the compression test mode. Scan FF that scans the same scan FF on the bypass test mode scan chain and sets the expected output value based on the scan FF information of the search result for the test pattern in the bypass test mode Are classified into scan FFs masked by Don't care ('X'), a bypass test pattern for scan chain fault diagnosis is created, and stored in the logic circuit information storage unit 32.

  The test result acquisition unit 21 uses an LSI test apparatus such as a tester or a DFT (Design For Testability) tester to perform a scan chain operation check test on a suspect sample, a scan chain operation check test on all scan chains of the suspect sample, and a logic unit. The operation test is executed, and the result is stored in the test result storage unit 31.

  The diagnosis initial setting means 22 reads the suspicious sample netlist information, test pattern information, scan chain information and test result information, and sets predetermined information.

  The fault scan chain specifying unit 23 outputs the output value of each scan FF obtained from the scan chain operation confirmation test result using the test pattern for scan chain fault diagnosis stored in the test result storage unit 31 and the output of each scan FF. The failure scan chain in the bypass test mode and its failure type are identified by comparing with the expected value, and stored in the failure scan chain storage unit 33.

  The failure scan FF narrowing means 24 refers to the logic unit operation test result of the test pattern for scan chain diagnosis stored in the test result storage unit 31, and determines the failure scan chain and failure type stored in the failure scan chain storage unit 33. Using the output expected value of each scan FF and the output value of each scan FF obtained from the logic unit operation test result, the primary fault candidates are narrowed down and stored in the fault scan chain storage unit 33.

  The failure scan FF compression conversion unit 27 stores the range of scan FFs obtained from the primary failure candidate information in the bypass test mode stored in the failure scan chain storage unit 33 and stored in the logic circuit information storage unit 32. Based on the scan FF correspondence information of the bypass test mode and the compression test mode, the scan FF of the bypass test mode is calculated, converted into the scan FF information of the compression test mode corresponding to the scan FF, and the primary failure candidate is rewritten Then, it is stored in the fault scan chain storage unit 33.

  The scan chain fault simulation verification unit 25 branches the signal line between the scan FFs according to the fault type specified by the fault scan chain specifying unit 23 with respect to the primary fault candidate range estimated by the fault scan FF compression conversion unit 27. In such a case, before and after the branch is distinguished as a failure candidate, a failure is assumed, and a scan chain failure simulation is executed using a test pattern in the compressed test mode. Then, the failure simulation result of the scan chain using the compression test mode pattern is compared with the test result of the compression test mode, and, for example, the scan FF and the signal line having the highest matching rate are output together with the failure type.

  FIG. 2 is a flowchart for explaining the entire procedure of the fault diagnosis of the embodiment of FIG.

  The scan chain diagnosis pattern creation means 26 generates a test pattern for scan chain diagnosis (A0).

  The test result acquisition unit 21 acquires a test result (A1).

  The diagnosis initial setting means 22 performs failure diagnosis initial setting (A2).

  The failure scan chain specifying unit 23 specifies the failure scan chain and the failure mode based on the output value of each scan FF obtained from the scan chain operation confirmation test result and the expected output value of each scan FF (A3).

  The failure scan FF narrowing means 24 narrows down the range of the failure scan FF (A4).

  The failure scan FF compression conversion means 27 calculates the scan FF in the bypass test mode, converts it into scan FF information in the compression test mode corresponding to the scan FF, and rewrites the primary failure candidate (A6).

  When the signal line between the scan FFs is branched, the scan chain failure simulation verification unit 25 assumes a failure in the branch before and after the branch (A8), and uses the test pattern in the compression test mode to perform the scan chain failure simulation. Is executed, the failure simulation result is compared with the test result in the compression test mode, and the failure scan FF is specified (A5).

  Note that the functions and processing of each unit in FIG. 1 may be realized by a program operating on a computer. In this case, the present invention provides the computer program and a computer-readable recording medium that records the program.

  Next, the scan chain diagnostic pattern creation means 26 of FIG. 1 will be described. FIG. 3 is a diagram illustrating a configuration example of the scan chain diagnostic pattern creation unit 26. As shown in FIG. 3, the scan chain diagnostic pattern creating unit 26 includes a scan chain information analyzing unit 261, a scan FF classification specifying unit 262, and a diagnostic pattern creating unit 263. The processing of each means will be described below.

  The scan chain information analysis unit 261 calculates correspondence information between the scan FF information of the scan chain in the bypass test mode and the scan FF information of the scan chain in the compression test mode, and uses the logic circuit information storage unit as the scan FF correspondence information 32.

  The scan FF search specifying unit 262 is located on the most SIN side of all scan chains in the compression test mode based on the scan FF correspondence information calculated by the scan chain information analysis unit 261 and stored in the logic circuit information storage unit 32. Identify the scan FF and the scan FF on the scan chain in the bypass test mode corresponding to the scan FF located closest to the SOUT side, and based on the chain length of each scan chain in the bypass test mode, the smaller number of scan FFs The output expected value that can identify the failure type of the scan chain is calculated by comparing the scan FF set to '0' or '1' with the expected value by Don't care ('X') (compare) Are classified into scan FFs for masking.

  Based on the scan FF classification information acquired by the scan FF search specifying unit 262, the diagnostic pattern creation unit 263 edits the value of the scan chain test pattern in the bypass test mode, and uses the logical pattern as a test pattern for scan chain diagnosis. The information is stored in the circuit information storage unit 32.

FIG. 4 is a diagram for explaining the operation of the scan chain diagnostic pattern creation means 26. 4A and 4B show scan chain configurations in the bypass test mode and the compression test mode. Referring to FIG. 4A, the scan chain configuration in the bypass test mode is
Number of chains: 1 Chain length: 24 bits
Chain name: C1
It is. In the scan chain, the scan FF numbers from the SOUT side are S1, S2,... S24.

Referring to FIG. 4B, the scan chain configuration in the compression test mode is
Number of chains: 3 Chain length: 8 bits each
Chain name: C1-1, C1-2, C1-3
It is. In each of the three chains, the scan FF numbers from the SOUT side are S1, S2,..., S24.

  The scan chain configuration in the bypass test mode and the scan chain configuration in the compression test mode are collated, and correspondence information between the bypass test mode and the compression test mode is created and stored for all scan FFs on the scan chain. .

  For example, in FIG. 4, S17 is the chain name C1 of the bypass test mode and the scan FF of the 17th bit, and at the same time is the same as the scan name of the chain name C1-1 and the 1st bit of the compression test mode of FIG. Corresponding information is calculated, and the corresponding information for both scan FFs is created and stored.

  Next, from the scan chain configuration in the compression test mode, the scan FF (S8 whose input is connected to SIN and S1 whose output is connected to SOUT) on the most scan input terminal SIN and scan output terminal SOUT side of each scan chain is set. Search as a keypoint scan FF, and identify a keypoint scan FF in the compression test mode on the scan chain in the bypass test mode based on the correspondence information.

For example, S8 and S1 of the keypoint scan FF of the chain name C1-1 in FIG. 4B correspond to S24 and S17 of the chain name C1 in FIG.
S8 and S1 of the keypoint scan FF of the chain name C1-2 in FIG. 4B correspond to S9 and S16 of the chain name C1 in FIG.
Keypoint scans FFS8 and S1 of the chain name C1-3 in FIG. 4B correspond to S8 and S1 of the chain name C1 in FIG. 4A, respectively.

  Finally, based on the keypoint / scan FF information, the diagnostic pattern creation means 263 sets the output expected value of the keypoint / scan FF and the scan FFs for several bits before and after the bypass test pattern to “0”. It is set so that it becomes an arbitrary value of “or” “1”, and other scan FFs are edited so that the expected output value becomes “X”.

  FIG. 4C is an image diagram of an expected output value of the completed scan chain failure diagnosis bypass test pattern. An expected value is set for each point of a long scan chain in the bypass test mode.

  The simplest method for creating a diagnostic pattern is to extract a test vector having a desired output expectation value from a test pattern in an existing bypass test mode and mask unnecessary information. However, in this method, since it is impossible to distinguish between a scan FF that becomes a failure state in the shift-in operation and the capture operation and a scan FF that becomes a failure state in the shift-out operation, the accuracy of narrowing down the failure scan FFs deteriorates. .

  The best method for creating a diagnostic pattern is to select a keypoint scan FF from any scan FF (target scan FF) on the other scan chain from the previous scan FF on the data input side of the target scan FF. Search scan FFs, set the expected value of the previous scan FF freely, and determine the output value of the target scan FF (existing design tools etc. can be used). It is possible to create a pattern that is not affected by the scan FF that is in the state.

At this time, if the scan chain is long enough,
"00110011" for 8 bits from the keypoint scan FF on the scan input terminal SIN side,
By setting 8 bits from the key point scan FF on the scan output terminal SOUT side to “11001100”, it is more efficient to specify the failure type of not only a stuck-at failure but also an indefinite failure or transition failure with one test pattern Can be done automatically.

  The scan chain in the bypass test mode often has an extremely long chain length, and if there is a fault on the chain, there is a problem that the number of failures increases and the test time increases. By masking the failure on the chain, fail information unnecessary for diagnosis is not output, so that the test time can be remarkably shortened and the amount of fail information can be reduced.

  The test pattern generation procedure (A0 in FIG. 2) may be skipped by creating a test pattern for scan chain failure diagnosis in advance.

  1 will be described in detail below with reference to FIGS. 5 and 6. FIG. FIG. 5 is a diagram schematically showing a circuit example. As shown in FIG. 5, it is assumed that 24 scan FFs are arranged in the circuit, and the “stack-at1 failure” exists in the second scan FF from the top and the third scan FF from the right. FIG. 6A shows the scan chain configuration in the bypass test mode of FIG. 5 and shows that the portion of the stack-at1 failure in FIG. 5 is the chain name C1 and the scan FF number S13. FIG. 6B shows an example of an expected output value in the bypass test mode, and FIG. 6C shows an example of an output value in the bypass test mode.

  As shown in FIG. 6B, the expected output values are: S1 is “0”, S2 is “1”, S7 is “0”, S8 is “1”, S9 is “0”, and S10 is “1”. , S15 is “0”, S16 is “1”, S17 is “0”, S18 is “1”, S23 is “0”, S24 is “1”, and others are “X”.

  As shown in FIG. 6 (C), the output values are S1 “0”, S2 “1”, S7 “1”, S8 “1”, S9 “0”, S10 “1”, S15 is “1”, S16 is “1”, S17 is “1”, S18 is “1”, S23 is “1”, S24 is “1”, and others are “X”.

  Since it is known in advance that the failure type is a stuck-at1 failure using the failure scan chain specifying means 23, the scan chain circuit (compression test mode) was affected by the stuck-at1 failure during the shift-out operation. As shown in FIG. 6C, the possible range is a range where the output value “1” is continuous except for the output value “X”, and the scan FFs S10 to S24 in FIG. 6A. Can be estimated.

  In FIG. 6, the value (pattern) is set only for 2-bit scan FFs (that is, “01” and “X” for others), but setting values such as “0101” and “0011” may be used. . By using a plurality of test patterns, the range of the fault scan FF can be narrowed down to a narrower range.

  FIG. 7 is a diagram showing a configuration of the failure scan FF compression conversion means 27 of FIG. Referring to FIG. 7, the failure scan FF compression conversion unit 27 includes a bypass failure candidate calculation unit 271 and a compression scan FF conversion unit 272. The bypass failure candidate calculation means 271 scans the logic circuit information storage unit 32 for the range of scan FFs obtained from the primary failure candidate information in the bypass test mode stored in the failure scan chain storage unit 33. Based on the FF correspondence information, the scan FF in the bypass test mode is calculated, and the compressed scan FF conversion unit 272 converts the scan FF information into the compressed test mode FF corresponding to the scan FF, rewrites the primary failure candidate, and the failure Store in the scan chain storage unit 33.

  FIG. 8 is a diagram for explaining a specific operation of the failure scan FF compression conversion means 27. FIG. 8A is a diagram showing the configuration of the scan chain in the bypass test mode. The scan chain name and the scan FF number are the same as those in FIG.

  FIG. 8B is a diagram illustrating the configuration of the scan chain in the compression test mode. The scan chain names are C1-1, C1-2, C1-3 from the top, and are numbered S1, S2,... Sequentially from the left of each scan chain. Using the scan FF correspondence information obtained when creating the scan chain failure diagnosis pattern, C1 and S17 in the bypass test mode correspond to C1-1 and S2 in the compression test mode, and the same applies to other scan FFs as well. You can see the correspondence. As shown in FIG. 6, the scan FFs S10 to S24 that may be affected by the stuck-at1 failure are the scan chain S7 to the chain name C1- of the scan chain of the chain name C1-2 in the compression test mode. It can be seen that this is S8 of one scan chain.

  The failure scan FF compression conversion means 27 converts the range of the failure scan FF in the bypass test mode obtained by the failure scan FF narrowing means 24 into the scan FF information in the compression test mode using this correspondence information. The conversion result is rewritten as a primary failure candidate and stored in the failure scan chain storage unit 33.

  FIG. 16 shows an example of the configuration of the scan chain failure simulation verification means 25 of FIG. Note that the scan chain fault simulation verification means 25 that considers the branch of the signal line connected to the fault candidate scan FF is referred to the description in Patent Document 1 (one in the branch consideration fault simulation verification unit 26 in FIG. 1 of Patent Document 1). (FIG. 16 is based on FIG. 5 of Patent Document 1).

  In FIG. 16, the scan chain fault simulation verification unit 25 includes a fault scan FF selection unit 251, a signal line branch distinction unit 252, a scan chain fault simulation unit 253, and a simulation result verification unit 254.

  The failure scan FF selection unit 251 refers to the scan scan chain in the compression test mode with reference to the failure scan chain in the failure scan chain storage unit 33 and the scan FF information in the compression test mode converted by the failure scan FF compression conversion unit 27. A failure assumption scan FF is selected from primary failure symptom scan FFs for performing failure simulation.

  The signal line branch distinguishing unit 252 refers to the logic circuit information storage unit 32 and distinguishes the signal line group from the scan output of the fault assumption scan FF to the downstream scan FF for each branch.

  The scan chain failure simulation unit 253 refers to the failure type of the failure scan chain recorded in the logic circuit information storage unit 31 and the failure scan chain storage unit 33, and before and after branching the signal line considering branching. Assuming each failure, a scan chain failure simulation is performed using the compression test mode pattern.

  The simulation result collation unit 254 collates the scan chain failure simulation result with the test result recorded in the test result storage unit 31 (the test result in the compression test mode), and calculates the ratio of the two. The simulation result matching unit 254 outputs the scan FF and the signal line having the highest ratio of the two together with the failure type. Note that a predetermined threshold value may be provided to output a matching or mismatching determination result, or a matching ratio may be output as the degree of failure possibility. As a method for calculating the coincidence rate between the failure simulation result and the test result, in addition to the method described in Patent Document 1, the existing coincidence rate calculating method may be used as it is, or a calculation method may be incorporated independently.

  It should be noted that the disclosures of the above-mentioned patent documents and non-patent documents are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

DESCRIPTION OF SYMBOLS 1 Input device 2 Data processing device 3 Memory | storage device 4 Output device 5 LSI test device 21 Test result acquisition means 22 Fault initial setting means 23 Fault scan chain specific means 24 Fault scan FF narrowing means 25 Scan chain fault simulation verification means 26 Scan chain diagnosis Pattern creation means 27 Fault scan FF compression conversion means 31 Test result storage section 32 Logic circuit information storage section 33 Fault scan chain storage section 34 Fault candidate scan FF storage section 251 Fault scan FF selection section 252 Signal line branch distinction section 263 Scan chain fault Simulation unit 254 Simulation result checking unit 261 Scan chain information analysis unit 262 Scan FF search specifying unit 263 Diagnostic pattern creation unit 271 Bypass failure candidate calculation unit 72 compressed scan FF converting means

Claims (8)

A failure location estimation system that narrows down the failure range on a scan chain from fail information of a scan chain test result comprising a scan flip-flop,
A scan chain diagnostic pattern creating means for creating a test pattern for scan chain fault diagnosis in the bypass test mode and storing the test pattern in the storage unit;
Fault scan / flip-flop narrowing means for narrowing down fault candidate scan flip-flops from the test results in both the scan chain fault diagnosis test pattern in the bypass test mode and the scan chain test pattern in the compression test mode; ,
Compared with the test results using the test pattern for the scan chain in the compression test mode, the fault scan chain in the compression test mode is identified and stored in the storage unit based on the difference in the scan chain structure between the compression test mode and the bypass test mode. Fault scan chain identification means to perform,
A failure scan flip-flop compression conversion means for converting the range of failure candidates in the bypass test mode into the range of scan flip-flops in the compression test mode based on the correspondence relationship between the scan flip-flops in the bypass test mode and the compression test mode;
A scan chain fault that executes a fault simulation of the scan chain including the scan flip-flop of the fault candidate using a test pattern of the compression test mode, collates with a test result in the compression test mode, and outputs a collation result to an output device Simulation verification means;
A failure location estimation system comprising: By comparing the scan chain information between the bypass test mode and the compression test mode, the correspondence between the scan flip-flops in the bypass test mode and the compression test mode is calculated,
First and second scan flip-flops positioned at the input and output ends of the scan chain in the compression test mode, and a bypass test mode corresponding to predetermined bits before and after the first and second scan flip-flops Identify the scan flip-flop number on the scan chain
For the test pattern in the bypass test mode, an output value is set in the scan flip-flop that specifies the number, and scan flip-flops other than the predetermined bits before and after the first and second scan flip-flops are set. The scan chain diagnostic pattern creating means for setting an output value to a value that masks comparison with an expected value and storing it as a test pattern for scan chain fault diagnosis;
Test result acquisition means for acquiring a test result of a scan chain by the test pattern for scan chain failure diagnosis and storing it in a test result storage unit;
Initial setting means for reading circuit design information and test results, and for initial setting of fault diagnosis,
Comparing the output value of the scan flip-flop obtained from the test result by the test pattern for the scan chain fault diagnosis and the expected output value, the fault scan chain and the fault type in the bypass test mode are specified, and the fault scan chain is stored. The fault scan chain specifying means to be stored in a section;
Each scan flip-flop is referred to by using a fault scan chain and a fault type stored in the fault scan chain storage unit with reference to a test result of the logic part of the test pattern for scan chain diagnosis stored in the test result storage unit The failure scan flip-flop that compares the expected output value of the group and the output value of each scan flip-flop obtained from the test result of the logic unit to narrow down primary failure candidates and stores them in the failure scan chain storage unit Narrowing means;
By referring to the range of scan flip-flops of primary failure candidates in the bypass test mode and the scan flip-flop correspondence information, the scan flip-flops in the compressed test mode corresponding to the scan flip-flops in the bypass test mode The fault scan flip-flop compression conversion means for converting into the fault information, rewriting the primary fault candidate in the bypass test mode to the primary fault candidate in the compression test mode, and storing it in the fault scan chain storage unit;
When the signal line between the scan flip-flops branches according to the failure type with respect to the range of the primary failure candidates rewritten by the failure scan flip-flop compression conversion means, the pre- and post-branch signal lines are classified as failure candidates. Separately, assuming each failure, using the test pattern of the compression test mode, the scan chain failure simulation is performed, the failure simulation result is compared with the test result of the compression test mode, and based on the matching rate in the comparison, The scan chain fault simulation verification means for outputting a scan flip-flop and a signal line together with a fault type;
An output device that receives an output from the scan chain fault simulation verification means and outputs the fault scan chain, the fault scan flip-flop, the fault type, a fault signal line, and a fault branch position of the fault signal line The failure location estimation system according to claim 1, further comprising: The scan chain diagnostic pattern creation means compares the scan flip-flop information of the scan chain of the bypass test mode with the scan flip-flop information of the scan chain of the compression test, and obtains correspondence information of the scan flip-flop numbers of both. Scan chain information analysis means for calculating and storing as scan flip-flop correspondence information;
Based on the scan flip-flop correspondence information, the scan flip-flop connected to the scan input end of the scan chain in the compression test mode and the scan flip-flop connected to the scan output end are stored as a key point scan flip-flop. And specifying a scan flip-flop number in the bypass test mode of the keypoint scan flip-flop,
A test vector in which a keypoint scan flip-flop and an expected output value of a scan flip-flop for a predetermined bit before and after the keypoint scan flip-flop are desired values is extracted from a test pattern of a given bypass test mode,
The expected output value of the keypoint scan flip-flop and the scan flip-flop for a predetermined number of bits before and after the key-point scan flip-flop is the state value determination scan flip-flop as specified in the test vector, and on the other scan chains Scan flip-flop search specifying means for classifying the expected output value of the scan flip-flop as a state value undetermined scan flip-flop for masking with Don't care ('X');
Based on the classification information of the scan flip-flop, edits the value of the test pattern of the bypass test, and stores as a test pattern for scan chain fault diagnosis in the logic circuit information storage unit,
The failure location estimation system according to claim 1 or 2, further comprising: The failure scan flip-flop compression conversion means,
The scan flip-flop correspondence stored in the logic circuit information storage unit 2 with respect to the range of the scan flip-flop obtained from the primary failure candidate information in the bypass test mode stored in the fault scan chain storage unit Bypass failure candidate calculation means for calculating a scan flip-flop in bypass test mode based on the information,
A compressed scan flip-flop conversion means for converting into scan flip-flop information in a compressed test mode corresponding to the scan flip-flop, rewriting a primary failure candidate and storing it in the failed scan chain storage unit;
The failure location estimation system according to claim 3, further comprising: A failure location estimation device that narrows down the failure range on the scan chain from the fail information of the scan chain test result consisting of scan flip-flops,
Create a test pattern for scan chain fault diagnosis in bypass test mode and store it in the storage unit.
From the test results of both the scan chain fault diagnosis test pattern in the bypass test mode and the scan chain test pattern in the compression test mode, the failure candidate scan flip-flops are narrowed down.
Compared with the test results using the test pattern for the scan chain in the compression test mode, the fault scan chain in the compression test mode is identified and stored in the storage unit based on the difference in the scan chain structure between the compression test mode and the bypass test mode. And
Based on the correspondence between the scan flip-flops in the bypass test mode and the compressed test mode, the range of failure candidates in the bypass test mode is converted into the range of scan flip-flops in the compressed test mode.
Using the test pattern of the compression test mode, the failure simulation of the scan chain including the scan flip-flop of the failure candidate is executed, the test result in the compression test mode is collated, and the collation result is output to the output device.
A fault location estimation method characterized by the above. The scan chain diagnostic pattern creation means of the failure location estimation device compares the scan chain information between the bypass test mode and the compression test mode, calculates the correspondence between the scan flip-flops in the bypass test mode and the compression test mode,
First and second scan flip-flops positioned at the input and output ends of the scan chain in the compression test mode, and a bypass test mode corresponding to predetermined bits before and after the first and second scan flip-flops Identify the scan flip-flop number on the scan chain
For the test pattern in the bypass test mode, an output value is set in the scan flip-flop that specifies the number, and scan flip-flops other than the predetermined bits before and after the first and second scan flip-flops are set. Set the output value to a value that masks the comparison with the expected value, store it as a test pattern for scan chain fault diagnosis,
The test result acquisition means of the failure location estimation device acquires the test result of the scan chain by the test pattern for scan chain failure diagnosis, and stores it in the test result storage unit,
The failure scan chain specifying means of the failure location estimating device compares the output value of the scan flip-flop obtained from the test result by the test pattern for the scan chain failure diagnosis with the expected output value, and the failure in the bypass test mode Identify the scan chain and fault type, store them in the fault scan chain storage unit,
The failure scan flip-flop narrowing means of the failure location estimation device refers to the test result of the logic part of the scan chain diagnostic test pattern stored in the test result storage unit, and is stored in the failure scan chain storage unit. Using the fault scan chain and fault type, the expected output value of each scan flip-flop is compared with the output value of each scan flip-flop obtained from the test result of the logic unit to narrow down the primary fault candidates , Store it in the fault scan chain storage unit,
The failure scan flip-flop compression conversion means of the failure location estimating apparatus refers to a bypass flip test mode primary flip candidate scan flip-flop range and the scan flip-flop correspondence information, and performs a bypass test. The mode scan flip-flop is converted into the corresponding scan flip-flop information of the compressed test mode, the primary failure candidate in the bypass test mode is rewritten to the primary failure candidate in the compression test mode, and stored in the failure scan chain storage unit Remember,
The scan chain fault simulation verification means of the fault location estimation device is configured to provide a signal line between the scan flip-flops according to the fault type with respect to the primary fault candidate range rewritten by the fault scan flip-flop compression conversion means. , Branching before and after branching as failure candidates, assuming each failure, using the test pattern in the compressed test mode, and executing the scan chain failure simulation, the failure simulation result and the compression test mode test result Based on the coincidence rate, the scan flip-flop and the signal line are output together with the fault type, and the fault scan chain, the fault scan flip-flop, the fault type, the fault signal line, and the fault signal line are output. Output the failure branch position of And wherein, fault location estimation method according to claim 5, wherein. To the computer that constitutes the failure location estimation device that narrows down the failure range on the scan chain from the fail information of the scan chain test result consisting of scan flip-flops,
A process of creating a test pattern for scan chain fault diagnosis in the bypass test mode and storing it in the storage unit;
A process for narrowing down failure candidate scan flip-flops from the test results in both the scan chain failure diagnosis test pattern in the bypass test mode and the scan chain test pattern in the compression test mode;
Compared with the test results using the test pattern for the scan chain in the compression test mode, the fault scan chain in the compression test mode is identified and stored in the storage unit based on the difference in the scan chain structure between the compression test mode and the bypass test mode. And
Based on the correspondence between the scan test flip-flops in the bypass test mode and the compression test mode, the process of converting the range of failure candidates in the bypass test mode into the scan flip-flop range in the compression test mode;
Using the test pattern in the compressed test mode, executing a failure simulation of the scan chain including the scan flip-flop of the failure candidate, checking the test result in the compressed test mode, and outputting the matching result to the output device;
A program that executes By comparing the scan chain information between the bypass test mode and the compression test mode, the correspondence between the scan flip-flops in the bypass test mode and the compression test mode is calculated,
First and second scan flip-flops positioned at the input and output ends of the scan chain in the compression test mode, and a bypass test mode corresponding to predetermined bits before and after the first and second scan flip-flops Identify the scan flip-flop number on the scan chain
For the test pattern in the bypass test mode, an output value is set in the scan flip-flop that specifies the number, and scan flip-flops other than the predetermined bits before and after the first and second scan flip-flops are set. A process of setting the output value to a value that masks comparison with the expected value and storing it as a test pattern for scan chain fault diagnosis,
A process for acquiring a test result of a scan chain by the test pattern for scan chain failure diagnosis and storing it in a test result storage unit;
Comparing the output value of the scan flip-flop obtained from the test result by the test pattern for the scan chain fault diagnosis and the expected output value, the fault scan chain and the fault type in the bypass test mode are specified, and the fault scan chain is stored. Processing to be stored in the department,
Each scan flip-flop is referred to by using a fault scan chain and a fault type stored in the fault scan chain storage unit with reference to a test result of the logic part of the test pattern for scan chain diagnosis stored in the test result storage unit Comparing the expected output value of the group and the output value of each scan flip-flop obtained from the test result of the logic unit, narrowing down the primary failure candidates and storing them in the failure scan chain storage unit;
By referring to the range of scan flip-flops of primary failure candidates in the bypass test mode and the scan flip-flop correspondence information, the scan flip-flops in the compressed test mode corresponding to the scan flip-flops in the bypass test mode Processing to convert the primary failure candidate in the bypass test mode into a primary failure candidate in the compressed test mode and store it in the failure scan chain storage unit,
When the signal line between the scan flip-flops branches according to the failure type with respect to the range of the primary failure candidates rewritten to the compressed test mode, the failure is distinguished by distinguishing before and after the branch as failure candidates. Execute the scan chain fault simulation using the test pattern in the compression test mode, compare the fault simulation result with the test result in the compression test mode, and select the scan flip-flop and signal line as the fault type based on the match rate. Output together with the fault scan chain, the fault scan flip-flop, the fault type, the fault signal line, and the fault branch position of the fault signal line to an output device;
The program according to claim 7, wherein the computer is executed.

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