JP6654456B2 - Test point circuit, scan flip-flop for sequential test, semiconductor device and design device - Google Patents

Description

  The present invention relates to a test point circuit, a scan flip-flop for a sequential test, a semiconductor device, and a design device, and relates to a technique applicable to, for example, a Logic Built-In Self Test (LBIST).

  A scan test is a general LSI (Large Scale Integration) test method. In order to make the scan test executable, the flip-flop (FF) in the circuit is replaced with an FF with a multiplexer (MUX) called a scan FF. The MUX can switch between a test input and a normal operation input by a scan enable signal.

  At the time of a scan test, scan FFs are serially connected to each other and operate as a shift register that can be controlled and observed from an external terminal of the LSI (this is called a “scan chain”). By shifting the scan chain, an arbitrary test pattern (load data) is supplied from a test input to each scan FF (load). This is called a “scan shift operation”. The test pattern set in each scan FF is applied to a combination circuit to be tested.

  Then, by switching the scan enable signal, the operation result of the combinational circuit is taken into the scan FF from the normal operation input. This is called a “capture operation”. The operation result obtained by the capture operation is shifted again by the scan FF, and a response is observed (unload). Simultaneously with the unloading, application (loading) of the next test pattern is performed. The scan test of the LSI is executed by comparing the value unloaded by the tester (unload data) with its expected value.

  In the scan test, the number of shift cycles corresponding to the number of scan FFs connected to the scan chain is required, so that a very large number of test steps is required. In addition, in order to execute an LSI scan test, it is necessary to store test data including expected values of load data and unload data required for a scan shift operation in a memory of a tester. If the number of test steps is very large, test data may not fit in the memory of the tester, and a necessary test may not be performed.

  As an example of a design for testability (DFT) that reduces the amount of test data, a Logic Built-in Self Test (LBIST) has been proposed (Non-Patent Document 1). In the LBIST, load data generated from a pseudo random pattern generator (PRPG) inside a circuit is supplied to a scan chain to perform a scan shift operation, and unload data after a capture operation is compressed into a response inside the circuit. (Multiple Input Signature Register: MISR).

  For this reason, during the scan test period by LBIST, there is no need to apply test data from an external tester, and the test can be executed only by supplying a clock. Then, after executing the test for an arbitrary time, the value compressed by the MISR is observed by an external tester, and the presence or absence of a failure is determined. Therefore, the test data amount required for the external tester is only the control sequence of the LBIST controller, the initial values of PRPG and MISR, and the expected values of the values output from the MISR.

Debaleena Das, Nur A. Touba, Reducing test data volume using external / LBIST hybrid test patterns, International Test Conference 2000

  2. Description of the Related Art Power-on Self-Test (POST) is required to realize functional safety of automotive in-vehicle devices in accordance with the international standard ISO 26262. In POST, the test of the logic unit is performed by LBIST due to the limitation of the amount of test data. In LBIST, since a test is executed by applying a random number pattern, there is a high possibility that many faults in the circuit will end undetected. For this reason, it is common practice to insert a test point circuit (Test Point Insertion: TPI) so that the probability of detecting a fault in the circuit when a random number is applied is increased. In LBIST, a large amount of TPI is required to increase the failure detection rate, and there is a problem that an area overhead (hereinafter, referred to as an area OH) increases. In addition, since the POST execution time is limited, it is necessary to shorten the test time and increase the failure detection rate.

  Other problems and novel features will be apparent from the description of this specification and the accompanying drawings.

According to one embodiment, the test point circuit constitutes a scan chain, and in one capture operation period of the clock sequential test, the first test clock circuit or the last test point circuit uses the first capture clock. The captured first operation result is captured by a second capture clock after the first capture clock.
Note that what is expressed by replacing the circuit of the above embodiment with a method, an apparatus, or a system, a program that causes a computer to execute a part of the processing in the circuit, and the like are also effective as aspects of the invention.

  According to the embodiment, the number of test point circuits required to achieve the target failure detection rate can be reduced, the increase in area overhead can be suppressed, and the test time can be reduced. .

FIG. 3 is a diagram illustrating an example of a semiconductor device capable of executing LBIST. FIG. 6 is a diagram for explaining insertion of a control test point circuit. It is a figure explaining insertion of a test point circuit for observation. FIG. 6 is a diagram illustrating an example of an operation waveform of a scan test. FIG. 6 is a diagram illustrating an example of an operation waveform of a clock sequential test. FIG. 2 is a diagram illustrating a configuration of a semiconductor device in which a test point circuit according to the first embodiment is inserted. FIG. 3 is a diagram illustrating a failure detection rate with respect to a scan test time of the semiconductor device according to the first embodiment; FIG. 4 is a diagram illustrating another configuration of the test point circuit according to the first embodiment. FIG. 13 is a diagram showing a configuration of a semiconductor device in which a test point circuit according to a second embodiment is inserted. FIG. 14 is a diagram illustrating a configuration of a semiconductor device in which a test point circuit according to a third embodiment is inserted. FIG. 14 is a diagram illustrating a configuration of a test point circuit according to a fourth embodiment. FIG. 2 is a diagram showing a configuration of a design device for designing a semiconductor device according to an embodiment. FIG. 4 is a diagram showing a design flow of the semiconductor device according to the embodiment. FIG. 4 is a diagram showing a design flow of the semiconductor device according to the embodiment. FIG. 15 is a diagram showing a configuration of a semiconductor device according to a fifth embodiment in which a scan flip-flop for a sequential test is inserted. FIG. 15 is a diagram showing a configuration of a sequential test scan flip-flop according to a fifth embodiment. FIG. 16 is a diagram illustrating an example of an operation waveform of the semiconductor device according to FIG. 15. FIG. 16 is a diagram illustrating an example of an operation waveform of the semiconductor device according to FIG. 15. 17 is a truth table of the scan flip-flop for the sequential test shown in FIG. 16. FIG. 3 is a diagram illustrating a schematic configuration of a scan flip-flop for a sequential test. 21 is a truth table of the scan flip-flop for the sequential test shown in FIG. 20. FIG. 15 is a diagram illustrating another configuration of the scan flip-flop for sequential test according to the fifth embodiment. 23 is a truth table of the scan flip-flop for the sequential test shown in FIG. 22. FIG. 15 is a diagram illustrating another configuration of the scan flip-flop for sequential test according to the fifth embodiment. 25 is a truth table of the scan flip-flop for the sequential test shown in FIG. 24. FIG. 15 is a diagram illustrating another configuration of the scan flip-flop for sequential test according to the fifth embodiment. 27 is a truth table of the scan flip-flop for the sequential test shown in FIG. 26. FIG. 27 is a diagram showing an operation waveform example of the semiconductor device into which the scan flip-flop for the sequential test shown in FIG. 24 or 26 is inserted. FIG. 27 is a diagram showing an operation waveform example of the semiconductor device into which the scan flip-flop for the sequential test shown in FIG. 24 or 26 is inserted. FIG. 17 is a diagram showing a configuration of a semiconductor device according to a sixth embodiment in which a scan flip-flop for a sequential test is inserted. FIG. 17 is a diagram illustrating a failure detection rate with respect to a scan test time of the semiconductor device according to the sixth embodiment. FIG. 21 is a diagram illustrating a configuration of a semiconductor device according to a seventh embodiment in which a scan flip-flop for a sequential test is inserted. FIG. 21 is a diagram showing a configuration of a semiconductor device according to an eighth embodiment in which a scan flip-flop for a sequential test is inserted. FIG. 19 is a diagram showing a configuration of a semiconductor device according to a ninth embodiment in which a scan flip-flop for a sequential test is inserted. FIG. 21 is a diagram showing a schematic configuration of a sequential test scan flip-flop used in a ninth embodiment. 36 is a truth table of the scan flip-flop for the sequential test shown in FIG. 35. FIG. 21 is a diagram showing a configuration of a semiconductor device according to a tenth embodiment in which a scan flip-flop for a sequential test is inserted. FIG. 2 is a diagram showing a configuration of a design device for designing a semiconductor device according to an embodiment. FIG. 4 is a diagram showing a design flow of the semiconductor device according to the embodiment. FIG. 3 is a diagram illustrating a configuration of a semiconductor device in which a test point circuit and a scan flip-flop for a sequential test according to the embodiment are inserted.

  Hereinafter, embodiments will be described with reference to the drawings. For clarity of explanation, the following description and drawings are appropriately omitted and simplified. Specific numerical values and the like shown in the following embodiments are merely examples for facilitating understanding of the present invention, and are not limited thereto unless otherwise specified. In each of the drawings, the same elements are denoted by the same reference numerals, and repeated description will be omitted as necessary.

  In addition, each element described in the drawings as a functional block that performs various processes can be configured by a CPU, a memory, and other circuits in terms of hardware, and can be configured by a program loaded in the memory in terms of software. It is realized by such as. Therefore, it is understood by those skilled in the art that these functional blocks can be realized in various forms by only hardware, only software, or a combination thereof, and the present invention is not limited to any of them.

  The embodiment relates to a semiconductor device capable of executing a Logic Built-In Self Test (LBIST), a test point circuit used for the semiconductor device, and a design device of the semiconductor device. First, a semiconductor device capable of executing LBIST will be described with reference to FIG. FIG. 1 is a diagram illustrating an example of a semiconductor device capable of executing LBIST. In the following description, a combination circuit to be tested is referred to as a DUT (Design Under Test).

  As shown in FIG. 1, a semiconductor device 1 includes a DUT 2, a pseudo random pattern generator (hereinafter, referred to as PRPG) 3, a response compressor (Multiple Input Signature Register: hereinafter, referred to as MISR) 4, and an LBIST. A controller 5 includes a scan flip-flop (hereinafter, referred to as SFF) 10.

  In the semiconductor device 1, a plurality of scan chains are constructed by connecting a plurality of SFFs 10 serially. In the example shown in FIG. 1, five SFFs 10 are connected to one scan chain, respectively. The SFF 10 is a shift scan flip-flop that can switch between a scan shift operation and a capture operation. The SFF 10 has a MUX (multiplexer) 11, an FF (flip-flop) 12, a data input terminal DATA, a scan-in terminal SIN, a control input terminal SMC, a clock terminal CLK, and a data output terminal Q.

  The MUX 11 receives a test signal input from the scan-in terminal SIN and an operation result from the DUT 2 input from the data input terminal DATA. The MUX 11 switches between a scan shift operation and a capture operation according to a scan enable signal (scan-enable) input from the control input terminal SMC. That is, the scan enable signal is a control signal for switching between the scan shift operation and the capture operation.

  In the example shown in FIG. 1, when the scan enable signal is high (1), the scan-in terminal SIN becomes valid. When the scan enable signal is low (0), the data input terminal DATA becomes valid. The FF 12 captures a value output from the MUX 11 according to a clock signal (clock 1 or clock 2) input from the clock terminal CLK, and outputs the value from the data output terminal Q to the scan-in terminal SIN of the SFF 10 at the subsequent stage. Although FIG. 1 shows an example in which clock signals supplied to the respective scan chains are different, the clock signals may be the same.

  The PRPG3 is connected to the input side of the plurality of scan chains. The PRPG 3 generates load data (test signal) in the LBIST and supplies it to the scan chain. The SFF 10 outputs a test signal input from the scan-in terminal SIN to the subsequent SFF 10 during the scan shift operation period. An arbitrary test pattern is set in each SFF 10 by performing a shift operation of the scan chain.

  In the capture operation, the value set in each SFF 10 is supplied to the DUT 2 during the shift operation period, and the operation result in the DUT 2 is captured in each SFF 10. The MISR 4 is connected to the output side of the plurality of scan chains. After the capture operation, the MISR 4 compresses unload data from a plurality of scan chains. The result of this compression is called a "signature". The signature compressed by the MISR 4 is compared with an expected value by a control circuit in the circuit at the time of the POST operation and an expected value by an external tester at the time of a test of a good product to determine whether there is a failure.

  The LBIST controller 5 is connected to the PRPG 3 and the MISR 4. The clock signal tck is supplied to each of the LBIST controller 5, PRPG3, and MISR4. The LBIST controller 5 supplies an initial value to the PRPG3. The PRPG 3 generates load data based on an initial value supplied from the LBIST controller 5 in synchronization with the clock signal tck. Note that the initial value of PRPG3 can be arbitrarily rewritten by a test data input signal tdi supplied from the outside.

  Further, the LBIST controller 5 outputs the compression result compressed by the MISR 4 to an external tester as a test data output signal tdo. After the test is executed for an arbitrary time, the presence or absence of a failure in the DUT is determined by comparing the compression result with an expected value using an external tester.

  A test point circuit is inserted into the semiconductor device 1 so that the probability of detecting a failure in the circuit increases when a random number is applied. Here, the test point circuit is a logic circuit inserted for the purpose of improving the controllability and observability of signal lines and terminals in the test target circuit.

  "Controllability" is a measure of how easily the internal state of the DUT can be controlled from external terminals. Specifically, “controllability” refers to the minimum value of the number of signal lines for which a logical value must be set to set the value of any signal line or terminal included in the DUT to 0 or 1. “Observability” is a measure of how easily the internal state of the DUT can be observed at an external terminal. Specifically, it refers to the minimum value of the number of signal lines for which a logical value must be set in order to propagate a signal to an observation point.

  By inserting the test point circuit into the test target circuit, it is possible to increase the failure detection rate in the DUT when applying a random number in LBIST. Here, a test point circuit inserted for the purpose of improving controllability is referred to as a control test point circuit. The control test point circuit is a logic circuit that functions as a control point that can set the value of the signal line in the DUT to 0 or 1. The control test point circuit includes, for example, a combinational circuit such as an AND gate and an OR gate, an external input terminal, and a flip-flop.

  A test point circuit inserted for the purpose of improving observability is referred to as an observation test point circuit. The observation test point circuit functions as an observation point at which the operation result of the DUT can be observed. The external test terminal and the SFF correspond to the observation test point circuit. In the following, the test point may be abbreviated as TP. Inserting a TP circuit into a signal line of a DUT to improve testability (testability, testability) may be abbreviated as TPI (Test Point Insertion).

  FIG. 2 is a diagram illustrating insertion of a control TP circuit. In the example shown in FIG. 2, as indicated by a broken line, an AND gate, an OR gate, and a control FF are inserted as a control TP circuit for a signal line having a low control probability of 1 value. Propagation of the value from the control FF can increase the probability of setting the inserted part of the AND gate and the OR gate to 1, and can improve the failure detection rate.

  FIG. 3 is a diagram illustrating insertion of the observation TP circuit. In the example illustrated in FIG. 3, as indicated by the broken line, the observation FF is inserted as a monitoring TP circuit in a portion where the failure propagation probability is low up to the end point FF. By connecting the observation FF with a fan-out, the failure can be observed by the observation FF, and the failure detection rate can be improved.

  As described above, in LBIST, a large amount of TPI is required to increase the failure detection rate, and there is a problem that the area OH increases. In view of such a problem, the present inventors have devised to apply a clock sequential test (multi-cycle test) to LBIST in order to reduce the number of inserted TPs or LBIST execution time.

  The clock sequential test is a scan test in which a plurality of capture clocks are input during one capture operation period and a response of a test signal by the DUT 2 is captured by the plurality of capture clocks. Here, the operation waveforms of the scan test using a single clock and the clock sequential test using a plurality of clocks will be described with reference to FIGS.

  4 and 5, the shift of the test signal during the scan shift operation period and the capture of the operation result during the capture operation period are performed in synchronization with the clock edge of the test clock. In the following description, a test clock during a capture operation period is referred to as a “capture clock”.

  FIG. 4 is a diagram showing an operation waveform example of a scan test for a single stuck-at fault model in which a single clock is applied during one capture operation period. When the scan enable signal is low (0), the operation result of DUT2 input from the data input terminal DATA is captured. In the example shown in FIG. 4, only one capture clock is input during one capture operation period.

  FIG. 5 is a diagram showing an operation waveform example of a clock sequential test in which a plurality of clocks are applied during one capture operation period. In the example shown in FIG. 5, three capture clocks are applied during one capture operation period. In FIG. 5, as in FIG. 4, when the scan enable signal is low (0), the operation result of the DUT 2 input from the data input terminal DATA is captured.

  As described above, in the clock sequential test, the operation result of the DUT 2 can be captured by a plurality of capture clocks during one capture operation period. As a result, the range in which a fault is activated during one capture operation period can be expanded, and the number of detectable faults can be increased. For this reason, it is possible to reduce the number of inserted TPs or the LBIST execution time required to achieve the target failure detection rate.

  The observation FF used as the observation TP circuit described in FIG. 3 has the same configuration as the SFF described in FIG. 1 and does not assume a clock sequential test. The present inventors have devised a test point circuit in consideration of the clock sequential test in order to further improve the effect of the clock sequential test.

  The test point circuit according to the embodiment constitutes a scan chain capable of executing a scan test of an LSI and performs a clock sequential test. The test point circuit according to the embodiment has a logic structure capable of suppressing an increase in area overhead due to test point insertion, shortening the test time, and increasing the fault detection rate. Specifically, in the test point circuit according to the embodiment, during one capture operation period of the clock sequential test, the first capture clock captures the first or last test point circuit captured by the preceding test point circuit or the last test point circuit. The operation result is captured at a second capture clock after the first capture clock.

  The semiconductor device using the test point circuit according to the embodiment can be applied to, for example, a product in which a Power-on Self-Test (POST) based on the international standard ISO26262 is mounted. In addition, this semiconductor device can be applied to a product that wants to reduce test cost when LBIST is applied in a mass production test process, a design device (EDA (electronic design automation) tool) for mounting LBIST, and the like. .

Embodiment 1 FIG.
A semiconductor device in which the test point circuit according to the first embodiment is inserted will be described with reference to FIG. FIG. 6 is a diagram showing a configuration of the semiconductor device 1A according to the first embodiment. As shown in FIG. 6, the semiconductor device 1A includes a DUT 2, a PRPG 3, a MISR 4, an LBIST controller 5, an SFF 10, and an observation scan flip-flop (hereinafter, referred to as an observation SFF) 20. In FIG. 6, the observation SFF 20 is indicated as obsSFF. The configuration other than the observation SFF 20 is the same as that described with reference to FIG. 1, and a detailed description thereof will be omitted.

  A plurality of scan chains are built in the semiconductor device 1A. At least one of the plurality of scan chains includes only the observation SFF 20. In the example shown in FIG. 6, one scan chain is composed of only the observation SFF 20, and the other scan chains are composed of the SFF 10. The scan chain configured by the SFF 10 is configured separately from the scan chain configured only by the observation SFF 20.

  In FIG. 6, the scan chain constituted by the observation SFF 20 is indicated as a scan chain 6A. In the scan chain 6A, five observation SFFs 20 are serially connected. In other scan chains, five SFFs 10 are serially connected.

  The observation SFF 20 is an observation test point circuit inserted for the purpose of improving observability and having an effect of improving the efficiency of a clock sequential test. The observation SFF 20 is inserted into the DUT 2 that outputs an operation result according to a test signal to be scanned in. The observation SFF 20 has an XOR gate 21, a MUX 22, a FF 23, a data input terminal DATA, a scan-in terminal SIN, a control input terminal SMC, a clock terminal CLK, and a data output terminal Q. That is, the observation SFF 20 has the same input / output configuration as the SFF 10.

  The output of the observation SFF 20 is connected to the scan-in terminal SIN of the observation SFF 20 at the subsequent stage, and the scan chain 6A is configured. The observation SFF 20 can switch between a scan shift operation and a capture operation.

  The observation SFF 20 captures the operation result from the DUT 2 at each of a plurality of capture clocks during one capture operation period. For example, the first capture clock applied during one capture operation period is the first capture clock, and the capture clock following the first capture clock is the second capture clock. The calculation result from the DUT 2 captured by the first capture clock is defined as a first calculation result. A period in which one capture clock pulse operation is performed in one capture operation period is defined as a capture cycle.

  Note that the first capture clock may not be applied first during one capture operation period, but may be applied later. The second capture clock only needs to be applied after the first capture clock in one capture operation period.

  The calculation result from the DUT 2 is input to the data input terminal DATA during the capture operation period. A test signal is input to the scan-in terminal SIN during the scan shift operation period, and a first operation result captured by the observation SFF 20 at the preceding stage of the scan chain with the first capture clock during the capture operation period is input.

  The XOR gate 21 receives a signal input from the scan-in terminal SIN and a signal input from the data input terminal DATA. Further, the XOR gate 21 calculates the calculation result from the DUT 2 input from the data input terminal DATA, and the first calculation result captured by the observation SFF 20 at the preceding stage of the scan chain input from the scan-in terminal SIN using the first capture clock. And outputs an exclusive OR with

  The MUX 22 receives a signal input from the scan-in terminal SIN and a signal output from the XOR gate 21. The MUX 22 switches between a scan shift operation and a capture operation according to a scan enable signal input from the control input terminal SMC. In the example shown in FIG. 6, when the scan enable signal is high (1), the MUX 22 performs the scan shift operation, and the input from the scan-in terminal SIN becomes valid. The MUX 22 performs a capture operation when the scan enable signal is low (0), and the output from the XOR gate 21 becomes valid.

  The FF 23 captures a value output from the MUX 22 according to a clock signal (clock2) input from the clock terminal CLK, and outputs the value from the data output terminal Q to the scan-in terminal SIN of the observation SFF 20 at the subsequent stage. During the scan shift operation period, the FF 23 captures a test signal. Also, during the capture operation period, the FF 23 captures the exclusive OR output from the MUX 22 with the second capture clock following the first capture clock. That is, the first calculation result captured by the observation SFF 20 at the preceding stage of the scan chain 6A with the first capture clock is propagated to the observation SFF 20 at the subsequent stage with the second capture clock after the first capture clock.

  If an SFF 10 is used instead of the observation SFF 20 in FIG. 6, in the clock sequential test, the operation result that reaches the data input terminal DATA of the observation SFF 20 at the first capture clock is propagated at the next second capture clock. It disappears without a point.

  On the other hand, in the semiconductor device 1A according to the first embodiment, the operation result that has reached the observation SFF 20 with the first capture clock during one capture operation period is determined by the subsequent stage on the scan chain 6A with the next second capture clock. Is transmitted via the XOR gate 21 to the observation SFF 20. As described above, in the semiconductor device 1A, it is possible to increase the probability that the calculation result that has reached the observation SFF 20 can be accumulated in the observation SFF 20 subsequent to the scan chain 6A without being lost in the next capture cycle.

  In addition, the observation SFF 20 accumulates the operation result that has reached the preceding observation SFF 20 and, at each capture cycle, captures the operation result from the DUT 2 via the XOR gate 21 from the data input terminal DATA of the observation SFF 20. it can. Therefore, when a plurality of capture clocks are applied during one capture operation period, the number of detectable faults increases. This makes it possible to reduce the number of inserted TPs required to achieve the target failure detection rate. Therefore, an increase in area overhead can be suppressed.

  In addition, by executing the clock sequential test in the semiconductor device 1A of FIG. 6, many failures can be detected in one capture operation period, and as a result, the test time can be reduced. In the scan test, since the scan shift operation time occupies most of the test time, increasing the number of capture clocks during the capture operation period has almost no effect on the test time.

  Here, the effect of reducing the test time will be described with reference to FIG. FIG. 7 is a diagram illustrating a failure detection rate with respect to a test time. In FIG. 7, the horizontal axis indicates the test time, and the vertical axis indicates the failure detection rate. In FIG. 7, the solid line indicates the result of the semiconductor device 1A using the observation SFF 20 according to the embodiment, and the broken line indicates the result of the semiconductor device when the observation SFF 20 is replaced with the SFF 10 in FIG. Is shown.

  In the example shown in FIG. 7, a clock sequential test in which 10 capture clocks are applied in one capture operation period is applied. As shown in FIG. 7, by using the observation SFF 20, the test time required to reach the target failure detection rate can be reduced to half or less as compared with the case where the SFF 10 is used.

  As described above, according to the embodiment, the efficiency of the clock sequential test can be improved with a low area OH by using a scan chain configuration using the observation SFF 20 without adding a special test circuit.

  The semiconductor device 1A shown in FIG. 6 can execute LBIST, and has the PRPG3 and the MISR4 mounted thereon. However, the present invention is not limited to this example. The clock sequential test has a high effect of reducing the number of inserted TPs or the LBIST execution time, especially in LBIST, but has a certain effect in compression scan.

  A compressed scan is an example of a design for testability (DFT) that reduces the amount of test data. In the compression scan, the number of SFFs per scan chain is reduced by constructing more scan chains inside than the number of external terminals. Then, the value supplied from the external input terminal is developed into the number of internal scan chains via the decompressor, and a test pattern is applied to each scan FF. The output from the scan chain is compressed by a compressor and observed at an external output terminal.

  In the compression scan, a set value (care bit) of a scan FF required for failure detection is supplied with a small number of shift cycles, and each scan FF can be observed with a small number of shift cycles. For this reason, it is possible to increase the number of failure detections per bit of the external input / output terminal and reduce the amount of test data. The observation SFF 20 according to the embodiment can also be applied to a semiconductor device capable of executing a compression scan test.

  In a semiconductor device capable of executing a compression scan, a decompressor and a compressor which can be controlled and observed from the outside are connected instead of the PRPG3 and the MISR4 in FIG. Even in a semiconductor device capable of performing a compression scan, the efficiency of the clock sequential test can be improved by adopting a configuration similar to the configuration illustrated in FIG.

  In the example shown in FIG. 6, the clock signal (clock2) supplied to the scan chain 6A is different from the clock signal (clock1) supplied to the other scan chains, but may be the same. That is, the scan chain including the SFF 10 and the scan chain including the observation SFF 20 may have different clock domains or may have the same clock domain.

  FIG. 8 shows another example of the observation SFF 20. FIG. 8 is a diagram showing a configuration of another test point circuit 30 according to the first embodiment. The observation SFF 30 is used instead of the observation SFF 20 of the semiconductor device 1A in FIG. As shown in FIG. 8, the observation SFF 30 has a NOR gate 31, an XOR gate 32, an FF 33, a data input terminal DATA, a scan-in terminal SIN, a control input terminal SMC, a clock terminal CLK, and a data output terminal Q. .

  Similar to the scan chain 6A in FIG. 6, the plurality of observation SFFs 30 constitute one scan chain. Further, at least one scan chain among the plurality of scan chains in the semiconductor device 1A is configured only by the observation SFF 30.

  The observation SFF 30, like the observation SFF 20, captures the operation result from the DUT 2 with each of the plurality of capture clocks during one capture operation period. The calculation result from the DUT 2 is input to the data input terminal DATA during the capture operation. A test signal is input to the scan-in terminal SIN during the scan shift operation period, and a first operation result captured by the observation SFF 20 at the preceding stage of the scan chain with the first capture clock during the capture operation period is input.

  A scan enable signal, which is a control signal for switching between a scan shift operation and a capture operation, is input to the control input terminal SMC. The NOR gate 31 receives a scan enable signal input from the control input terminal SMC and a signal input from the data input terminal DATA during the capture operation period, and outputs a NOR. The XOR gate 32 receives the first operation result input to the scan-in terminal SIN and the NOR of the NOR gate 31, and outputs an exclusive OR.

  The FF 33 captures the value output from the XOR gate 32 in response to the clock signal input from the clock terminal CLK, and outputs the value from the data output terminal Q to the scan-in terminal SIN of the observation SFF 20 at the subsequent stage. During the capture operation period, the FF 33 captures the exclusive OR output from the XOR gate 32 with the second capture clock following the first capture clock.

  In the scan shift operation period (scan enable signal = 1), the value of the data input terminal DATA is cut off, and the test signal input from the scan-in terminal SIN is taken into the FF 33. During the capture operation period (scan enable signal = 0), the value of the data input terminal DATA is inverted and passed through. The XOR gate 32 receives the inverted value of the value of the data input terminal DATA and the value of the scan-in terminal SIN. The FF 33 captures the output value of the XOR gate 32 according to the clock terminal CLK. The FF 33 of the observation SFF 30 has the same function as the FF 23 of the observation SFF 20 except that the value to be taken is inverted.

  When the observation SFF 30 is used, the inverted value of the value input from the data input terminal DATA is taken into the FF 33 via the XOR gate 32 during the capture operation period. Even when the inverted value of the input of the data input terminal DATA is captured by the observation SFF 30, there is no effect on the scan test operation and the normal user operation.

  In the clock sequential test, the first operation result captured by the observation SFF 20 at the preceding stage of the scan chain 6A with the first capture clock is propagated to the observation SFF 20 at the subsequent stage with the second capture clock after the first capture clock. Thus, the efficiency of the clock sequential test can be improved with a low area OH. Further, the configuration of the observation SFF 30 is smaller in circuit area and delay than the configuration of the observation SFF 20. For this reason, by using the observation SFF 30 as the observation test point circuit, the area OH can be further suppressed, and the decrease in operation speed can be suppressed.

Embodiment 2 FIG.
A semiconductor device in which a test point circuit according to the second embodiment is inserted will be described with reference to FIG. FIG. 9 shows a configuration of a semiconductor device 1B according to the second embodiment. As shown in FIG. 9, the semiconductor device 1B includes a DUT 2, a PRPG 3, a MISR 4, an LBIST controller 5, an SFF 10, an observation SFF 30, and an observation SFF 40. The observation SFF 30 and the observation SFF 40 are observation test point circuits inserted for the purpose of improving observability and having an effect of improving the efficiency of the clock sequential test. In FIG. 9, the observation SFF 30 is indicated as obsSFF, and the observation SFF 40 is indicated as obsSFF2.

  In the semiconductor device 1B, at least one scan chain of the plurality of scan chains includes the observation SFF 30 and the observation SFF 40. In the example shown in FIG. 6, one scan chain is configured by the observation SFF 30 and the observation SFF 40, and the remaining scan chains are configured by the SFF 10. In FIG. 9, the scan chain constituted by the observation SFF 30 and the observation SFF 40 is shown as a scan chain 6B.

  In the scan chain 6B, the observation SFF 40 is connected to the foremost stage, and four observation SFFs 30 are serially connected to the subsequent stage of the observation SFF 40. As the observation SFF 30, one having the configuration shown in FIG. 8 is used. Although the observation SFF 30 is used in the example shown in FIG. 9, the observation SFF 20 shown in FIG. 6 may be used instead of the observation SFF 30. That is, in the scan chain 6B, the observation SFF 40 and the four observation SFFs 20 may be serially connected. The configuration other than the observation SFF 30 and the observation SFF 40 is the same as that described with reference to FIG. 6, and a detailed description thereof will be omitted.

  The output of the observation SFF 40 is connected to the scan-in terminal SIN of the observation SFF 30. Further, the output of the observation SFF 30 is connected to the scan-in terminal SIN terminal of the observation SFF 30 at the subsequent stage, respectively, to form the scan chain 6B. The output of the observation SFF 30 at the last stage is connected to the data input terminal DATA2 of the observation SFF 40. Both the observation SFF 40 and the observation SFF 30 can switch between a scan shift operation and a capture operation. The observation SFF 40 can capture the operation result from the DUT 2 with each of a plurality of capture clocks during one capture operation period, similarly to the observation SFF 30.

  In the semiconductor device 1B according to the second embodiment, in the clock sequential test, a failure propagated to the last observation SFF 30 can be held on the scan chain 6B. As shown in FIG. 9, the observation SFF 40 has an XOR gate 41, a MUX 42, an FF 43, a data input terminal DATA, a data input terminal DATA2, a scan-in terminal SIN, a control input terminal SMC, a clock terminal CLK, and a data output terminal Q. are doing.

  A test signal is input to the scan-in terminal SIN during a scan shift operation period. The calculation result from the DUT 2 is input to the data input terminal DATA during the capture operation period. In addition, a first calculation result captured by the last observation SFF 30 with the first capture clock during the capture operation period is input to the data input terminal DATA2. That is, the observation SFF 40 has two data input terminals.

  XOR gate 41 receives a signal input from data input terminal DATA and a signal input from data input terminal DATA2. The XOR gate 41 calculates the operation result from the DUT 2 input from the data input terminal DATA, the first operation result captured by the last observation SFF 30 of the scan chain input from the data input terminal DATA 2 with the first capture clock, and The exclusive OR of is output.

  The MUX 42 receives a signal input from the scan-in terminal SIN and a signal output from the XOR gate 41. The MUX switches between a scan shift operation and a capture operation according to a scan enable signal input from the control input terminal SMC. In the example shown in FIG. 9, the MUX 42 performs a scan shift operation when the scan enable signal is high (1), and the input from the scan-in terminal SIN becomes valid. The MUX 42 performs a capture operation when the scan enable signal is low (0), and the output from the XOR gate 41 becomes valid.

  The FF 43 takes in the value output from the MUX 42 in response to a clock signal (clock 2) input from the clock terminal CLK, and outputs the value from the data output terminal Q to the scan-in terminal SIN of the observation SFF 30 at the subsequent stage.

  During the scan shift operation period (scan enable signal = 1), the FF 43 captures a test signal input from the scan-in terminal SIN. Also, during the capture operation period (scan enable signal = 0), the FF 43 captures the exclusive OR of the two data input terminals (DATA, DATA2) with the second capture clock following the first capture clock. That is, the first operation result captured by the last observation SFF 30 of the scan chain 6B with the first capture clock is propagated to the first observation SFF 20 with the second capture clock after the first capture clock.

  As described above, in the semiconductor device 1B according to the second embodiment, even when a plurality of capture clocks are applied during one capture operation period in the clock sequential test, the observation SFF 30 at the last stage of the scan chain 6B is driven by a certain capture clock. Is propagated to the observation SFF 40 at the forefront stage at the next capture clock and does not disappear.

  Due to the circuit configuration, in the clock sequential test, the MISR 4 may not be used during the capture operation period or may not be observed by an external tester via the compressor. In such a case, the calculation result taken into the last observation SFF 30 at the last stage has no propagation destination when the next capture clock is output, and is lost.

  When the circuit configuration shown in FIG. 9 is used as in the second embodiment, the operation result captured in the last observation SFF 30 can be propagated to the first observation SFF 40 by the capture clock of the next capture cycle. Loss can be prevented.

  In the scan chain 6B, each observation SFF 30 connected to the subsequent stage of the observation SFF 40 is, as described in the first embodiment, the first observation SFF 40 captured by the preceding observation SFF 40 or the observation SFF 30 with the first capture clock. One operation result is captured by the second capture clock. Thus, the number of faults that can be detected in one capture operation of the clock sequential test can be increased as compared with the first embodiment. As a result, it is possible to reduce the number of inserted TPs or the LBIST execution time required to achieve the target failure detection rate.

Embodiment 3 FIG.
A semiconductor device having a test point circuit according to the third embodiment inserted will be described with reference to FIG. FIG. 10 is a diagram showing a configuration of a semiconductor device 1C according to the third embodiment. As shown in FIG. 10, the semiconductor device 1C includes a DUT 2, a PRPG 3, a MISR 4C, an LBIST controller 5, an SFF 10, and an observation SFF 30. In the semiconductor device 1C, in the clock sequential test, the fault propagated to the last observation SFF 30 can be held by the MISR 4C.

  In the semiconductor device 1C, at least one scan chain of the plurality of scan chains includes only the observation SFF 30. In the example shown in FIG. 6, one scan chain is composed of only the observation SFF 30, and the remaining scan chains are composed of the SFF 10. In FIG. 10, a scan chain including only the observation SFF 30 is indicated as a scan chain 6C.

  In the scan chain 6C, five observation SFFs 30 are serially connected. As the observation SFF 30, one having the configuration shown in FIG. 8 is used. Although the observation SFF 30 is used in the example shown in FIG. 9, the observation SFF 20 shown in FIG. 6 may be used instead of the observation SFF 30.

  In the capture operation period (scan enable signal = 0), the first operation result captured by the last observation SFF 30 of the scan chain 6C at the first capture clock is the MISR4C at the second capture clock after the first capture clock. Is propagated to In the example shown in FIG. 10, a clock signal (clock2) is input to the MISR4. The MISR 4C captures the value output from the last observation SFF 30 in synchronization with the clock signal (clock2).

  The MISR 4C can compress the unload data from the plurality of scan chains after the capture operation to generate a signature, and can perform the compression operation by taking in the value of the last observation SFF 30 during the capture operation. That is, the MISR 4C can capture the output value of the observation SFF 30 at the final stage every capture cycle not only during the shift period but also when a plurality of capture clocks are applied in the clock sequential test.

  As described above, in each capture cycle, the fault propagation that has reached the last observation SFF 30 can be captured by the MISR 4C and can be observed without losing the fault. As a result, the number of faults that can be detected during one capture operation period of the clock sequential test can be increased, and the number of inserted TPs required to achieve the target fault detection rate or the LBIST execution time can be reduced. It becomes possible.

Embodiment 4 FIG.
The test point circuit according to the fourth embodiment will be described with reference to FIG. FIG. 11 is a diagram illustrating a configuration of the observation SFF 50 according to the fourth embodiment. As shown in FIG. 11, the observation SFF 50 has an XOR gate 51, a MUX 52, an FF 53, a data input terminal DATA, a scan-in terminal SIN, a control input terminal SMC, a clock terminal CLK, and a data output terminal Q.

  The observation SFF 50 is an observation test point circuit inserted for the purpose of improving observability and having an effect of improving the efficiency of the clock sequential test. The observation SFF 50 is an SFF cell having a self-loop structure of the XOR gate 51. The observation SFF 50 has a function of retaining a failure that has reached the data input terminal DATA in its own FF 53 when a plurality of capture clocks are applied in the clock sequential test.

  The XOR gate 51 receives the operation result of the DUT 2 input from the data input terminal DATA and the value output from the FF 53. The exclusive OR of the XOR gate 51 is input to the MUX 52. Further, a test signal input from the scan-in terminal SIN is input to the MUX 52. The MUX 52 outputs one of the exclusive OR and the test signal to the FF 53 according to the scan enable signal input from the control input terminal SMC.

  In the scan shift operation period (scan enable signal = 1), the value of the data input terminal DATA is cut off, and the test signal input from the scan-in terminal SIN is taken into the FF 53. In the capture operation period (scan enable signal = 0), the exclusive OR of the value of the data input terminal DATA and the value output from the FF 53 is taken into the FF 53.

  The FF 53 captures a first operation result input from the data input terminal DATA with a first capture clock during one capture operation period. Then, at the second capture clock following the first capture clock, the FF 53 captures the exclusive OR of the value input from the data input terminal DATA and the first operation result.

  As described above, a failure captured by the FF 53 of the observation SFF 50 in a certain capture cycle may be captured again by the FF 53 via the self-loop XOR gate 51 in the next capture cycle, and may remain without being lost. . Thereby, the number of faults that can be detected during one capture operation period of the clock sequential test can be increased. In the above embodiment, it is necessary to construct a scan chain composed of only the observation test point circuit. However, the observation SFF 50 can improve the efficiency of the clock sequential test without depending on the configuration of the scan chain. It becomes possible.

  A design apparatus 100 according to an embodiment will be described with reference to FIGS. FIG. 12 is a diagram showing a configuration of a design apparatus for designing a semiconductor device according to the embodiment. 13 and 14 are diagrams showing a design flow of the semiconductor device according to the embodiment. The design device 100 is for designing a semiconductor device with high efficiency of the clock sequential test described above.

  The design device 100 includes an arithmetic processing device 110, a storage device 120, a control input device 130, and a display output device 131. The arithmetic processing device 110 is a device capable of loading a program required for designing a semiconductor device and executing each functional process required for the design, and includes a CPU, a memory, and the like. The arithmetic processing device 110 has a test point insertion program 111 and a scanning program 112.

  The storage device 120 has a net list 121, a function library 122, a test constraint DB 123, a test point inserted net list 124, a test point insertion information DB 125, and a scanned net list 126. The storage device 120 refers to a storage medium such as an HDD disk or a memory for storing information of a library or a netlist. The design device 100 generates a semiconductor device in which the observation test point circuit described in the first to third embodiments is inserted by using the program of the arithmetic processing device 110 and referring to the netlist and the library of the storage device 120. .

  The control input device 130 is a general term for a device that allows a user to operate the arithmetic processing device 110 and the storage device 120, and includes a keyboard, a mouse, and the like. The display output device 131 is for the user to check the operation of the arithmetic processing device 110 and the storage device 120, and includes a display and the like.

  The netlist 121 stores cell information of an AND gate, an OR gate, an XOR gate, and the like, connection information between terminals, and the like, in addition to the cell information of the observation test point circuit described above. The function library stores cell functions and the like. The test constraint DB 123 stores information necessary for a circuit operation during a test. The information stored in the test constraint DB 123 includes, for example, information such as fixing the external output terminal to 0.

  The arithmetic processing unit 110 executes the test point insertion program 111 with reference to the net list 121, the function library 122, and the test constraint DB 123, thereby converting the test point inserted net list 124 into which the observation test point circuit is inserted. Generate. The test point insertion program 111 has a function of inserting the observation SFF 20, observation SFF 30, or observation SFF 40 as an observation test point circuit in addition to a general test point insertion function.

  Further, the arithmetic processing unit 110 refers to the function library 122, the test constraint DB 123, the test point inserted netlist 124, and the test point insertion information DB 125 to execute the scanning program 112, thereby improving the efficiency of the clock sequential test. Produce expensive semiconductor devices. The test point insertion information DB 125 stores test point insertion information including connection information of the inserted test point circuit.

  The scanning program 112 has a function of constructing at least one scan chain only with the inserted observation SFF in addition to a general scan chain construction function. The scanning program 112 uses the netlist after the insertion of the test point circuit, and builds at least one scan chain using only the observation SFF based on the test point insertion information. The test point insertion information can be output from the test point insertion program 111 or can be generated from the cell name of the instance of the test point inserted netlist.

  Further, the scanning program 112 can also execute a process of connecting the SFF or obsSFF at the first stage of each scan chain to the PRPG3 and a process of connecting the last SFF or obsSFF of each scan chain to the MISR4. By executing the scan program 112, the arithmetic processing unit 110 can generate a scan netlist 126 of a semiconductor device capable of executing LBIST and having improved clock sequential test efficiency.

  Here, a design flow of the semiconductor device will be described with reference to FIGS. First, with reference to FIG. 13, a description will be given of a process of generating a test point inserted netlist. FIG. 13 is a diagram illustrating an example of an algorithm for generating a test point inserted netlist.

  As shown in FIG. 13, first, predetermined information is input to the net list 121, the function library 122, and the test constraint DB 123 (step S11). Then, by analyzing the input information, circuit information and test constraint information are identified (step S12). Here, an SFF in the circuit, a user FF having a shift register structure, test constraint information, and the like are obtained. The test constraint information defines a target number of test point circuits to be inserted (target insertion number).

  Then, based on the information of the identified SFF, the controllability and observability of the logic circuit are analyzed based on random numbers in a general TPI algorithm (step S13). Then, based on the analysis result of step S13, an insertion point of the control test point circuit / observation test point circuit is selected (step S14).

  Thereafter, selection of the insertion point of the test point circuit is executed until the insertion point reaches the target number of insertions defined as the test constraint information (step S15). If the number of insertions has not reached the threshold value (NO in step S15), the processing from S13 to S15 is repeated. When the insertion point reaches the target number of insertions (step S15 YES), the observation SFF is inserted at the selected insertion point. The observation SFF 20, the observation SFF 30, or the observation SFF 40 is inserted into the observation point (step S16). Thereafter, the test point inserted netlist is output (step S17), and the test point inserted netlist generation processing ends.

  Next, referring to FIG. 14, a process of generating a scanned net list will be described. FIG. 14 is a diagram illustrating an example of an algorithm for generating a scanned netlist. As shown in FIG. 14, first, predetermined information is input to the net list 121, the function library 122, the test constraint DB 123, and the test point insertion information DB 125 (Step S21). Thereafter, by analyzing the input information, circuit information and test constraint information are identified (step S22). Then, the SFF in the circuit and the observation SFF corresponding to the clock sequential test are identified from the identified circuit information (step S23).

  Thereafter, at least one scan chain is constructed with the identified observation SFF (step S24). The arithmetic processing unit 110 executes a process of serially connecting only the observation SFF 20 or the observation SFF 30 as in the first embodiment in the scan chain including the observation SFF. Alternatively, the arithmetic processing unit 110 connects the observation SFF 40 to the forefront stage as in Embodiment 2, and connects the observation SFF 20 or the observation SFF 30 to the subsequent stage. In this case, the output of the last observation SFF is connected to the data input terminal DATA2 of the first observation SFF 40. By configuring the scan chain with the observation SFF as described above, the number of faults that can be detected during one capture operation period of the clock sequential test can be increased.

  Then, a scan chain is constructed by the SFF separately from the scan chain including the observation SFF (step S25). Thus, the scan netlist is output (step S26), and the process of generating the scan netlist ends. By using the scan netlist generated in this way, the number of faults detectable during one capture operation period of the clock sequential test is increased, and the number of inserted TPs necessary to achieve the target fault detection rate is reduced. Alternatively, it is possible to design a circuit capable of reducing the test execution time.

  In addition, as a process after the construction of the scan chain in FIG. 14, the arithmetic processing unit 110 executes a general compression circuit addition program to execute the LBIST, so that the LBIST of the PRPG 3, the MISR 4, the LBIST controller 5, etc. Add a circuit. When the semiconductor device of the third embodiment is designed, the output from the observation SFF during one capture operation period of the clock sequential test may be input to the output side of the observation SFF at the last stage of the scan chain. Insert possible MISR4. Thus, in one capture operation, the MISR 4 can capture the calculation result captured by the observation SFF provided at the last stage of the scan chain by the first capture clock by the next second capture clock. When performing a compression scan test, the arithmetic processing unit 110 adds a decompressor, a compressor, and the like for performing a compression scan.

  Then, the arithmetic processing unit 110 generates a test pattern for executing the clock sequential test by executing a general test pattern generation program on the circuit generated by the compression circuit addition program. This makes it possible to achieve the target detection rate in a short test time as shown in FIG.

  It is also possible to design a logic circuit with high clock sequential test efficiency using the observation SFF 50 using the design apparatus 100 shown in FIG. The design apparatus 100 executes the test point insertion program 111 to insert the observation SFF 50 at the observation point. Then, the design apparatus 100 does not construct a scan chain using the observation SFF 50, but constructs a scan chain using the SFF 10. That is, the process of step S25 is performed without performing the process of step S24 in FIG. As described above, by using the observation SFF 50, it is not necessary to have a function of a program for constructing a scan chain including only the observation SFF 50.

  In addition, the above-described program may be stored using various types of non-transitory computer readable media and supplied to a computer. Non-transitory computer-readable media include various types of tangible storage media. Examples of the non-transitory computer readable medium are a magnetic recording medium (for example, a flexible disk, a magnetic tape, a hard disk drive), a magneto-optical recording medium (for example, a magneto-optical disk), a CD-ROM (Read Only Memory) CD-R, and a CD. -R / W, semiconductor memory (e.g., mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM), flash ROM, RAM (Random Access Memory)). In addition, the program may be supplied to a computer by various types of transitory computer readable media. Examples of transitory computer readable media include electrical signals, optical signals, and electromagnetic waves. Transitory computer readable media can provide the program to a computer via a wired communication line such as an electric wire and an optical fiber, or a wireless communication line.

  As described above, according to the embodiment, the XOR output of the scan input and the data input is input to the flip-flop during one capture operation period of the clock sequential test, so that the data input and the scan input are performed. Can be captured. Thus, when a plurality of capture clocks are applied in the clock sequential test, the failure propagation that has reached the flip-flop in each capture cycle can be retained and compressed without being lost. This makes it possible to reduce the test time required to reach the target failure detection rate.

  Note that the test point circuit according to the embodiment can also be expressed as follows. The test point circuit described below corresponds to FIG.

(Appendix 1)
A test point circuit inserted into a combinational circuit that outputs an operation result according to a test signal to be scanned in,
A flip-flop that captures a first operation result from the combinational circuit with a first capture clock during one capture operation period of a clock sequential test;
An XOR gate that outputs an exclusive OR of the first operation result and a second operation result from the combinational circuit to the flip-flop;
Including
The flip-flop captures the exclusive OR with the second capture clock following the first capture clock.
Test point circuit.

(Appendix 2)
A semiconductor device design device including an arithmetic processing device capable of executing a predetermined process according to a preset program,
The semiconductor device includes:
A scan flip-flop forming a scan chain;
A test point circuit according to appendix 1,
Including
The arithmetic processing unit,
Performing an analysis process for analyzing the probability that the operation result from the combinational circuit becomes a predetermined logic state,
Based on the result of the analysis processing, select an insertion position of the test point circuit,
Inserting the test point circuit at the selected insertion position,
When constructing a scan chain by the scan flip-flop, do not execute the construction of the scan chain by the test point circuit,
Design equipment.

  In the above-described embodiment, an example has been described in which, in a semiconductor device that can execute LBIST, a test point circuit is inserted (TPI) to increase a failure detection rate, and a clock sequential test (multi-cycle test) is performed.

  In the following embodiment, an example in which a clock sequential test is performed to reduce test execution time without inserting a test point circuit in a semiconductor device capable of executing LBIST will be described.

  As described above, the clock sequential test is a multi-cycle test that captures the operation result from the combinational circuit with a plurality of capture clocks during one capture operation period. The clock sequential test is effective for reducing the LBIST execution time even when a test point circuit is not inserted.

  In the following embodiments, a schematic configuration of a semiconductor device capable of executing LBIST is the same as the configuration of the semiconductor device shown in FIG. 1, and thus a detailed description is omitted. An operation waveform example of the clock sequential test using a plurality of clocks is as described in FIG.

  The SFF 10 used in FIG. 1 does not assume a clock sequential test. The present inventors devised a scan flip-flop for a sequential test (hereinafter, referred to as seqSFF) in consideration of the clock sequential test, which is used in place of the SFF 10 in FIG. 1 in order to further improve the effect of the clock sequential test. .

  The scan flip-flop for a sequential test according to the embodiment constitutes a scan chain capable of executing an LSI scan test, and performs a clock sequential test. The seqSFF according to the embodiment has a logical structure that can reduce the test execution time and increase the failure detection rate.

  Specifically, the seqSFF according to the embodiment includes a test enable input terminal to which a test enable signal is input. The seqSFF is a second capture clock after the first capture clock during a single capture operation period of the clock sequential test according to the test enable signal, and is a stage preceding the scan flip-flop for the sequential test in the scan chain or the scan. The first cell at the last stage of the chain captures the first operation result from the combinational circuit captured by the first capture clock.

  The semiconductor device using the seqSFF of the embodiment can be applied to, for example, a product mounted with POST. In addition, this semiconductor device can be applied to a product that wants to reduce test cost when LBIST is applied in a mass production test process, a design device (EDA tool) for mounting LBIST, and the like.

Embodiment 5 FIG.
Referring to FIGS. 15 and 16, a sequential test scan flip-flop (seqSFF) used in a semiconductor device that executes a clock sequential test will be described. FIG. 15 is a diagram showing a configuration of a semiconductor device in which a seqSFF according to the fifth embodiment is inserted. The semiconductor device 1D of FIG. 15 has a minimum configuration capable of retaining the failure propagation that has reached the SFF 10 when a plurality of clocks are applied in the clock sequential test, without being lost even in the next capture cycle. FIG. 15 illustrates only the minimum configuration of the semiconductor device 1D for explaining the seqSFF 60.

  As shown in FIG. 15, the semiconductor device 1D includes a DUT 2, an SFF 10, and a seqSFF 60. A seqSFF 60 is serially connected to the subsequent stage of the SFF 10, and one scan chain is constructed. The DUT 2 and the SFF 10 have the same configurations as those described with reference to FIG.

  FIG. 16 is a diagram illustrating a configuration of the seqSFF 60 according to the fifth embodiment. As shown in FIG. 16, the seqSFF 60 includes a NOR gate 61, a NAND gate 62, an XOR gate 63, an FF64, a data input terminal DATA, a control input terminal SMC, a scan-in terminal SIN, a test enable input terminal SEQ_TEST_EN, a clock terminal CLK, and a data terminal. It has an output terminal Q. The input / output configuration of the seqSFF 60 is the same as the input / output configuration of the SFF 10 except for the test enable input terminal SEQ_TEST_EN. That is, the seqSFF 60 has a test enable input terminal SEQ_TEST_EN in addition to the input / output configuration of the SFF 10.

  The output of the SFF 10 is connected to the scan-in terminal SIN of the seqSFF 60. The seqSFF 60 can switch between a normal user operation and a scan test operation. The seqSFF 60 is further capable of switching between a scan shift operation and a capture operation during a scan test operation period. The seqSFF 60 captures the operation result from the DUT 2 at each of a plurality of capture clocks during one capture operation period.

  For example, the first capture clock applied during one capture operation period is the first capture clock, and the capture clock following the first capture clock is the second capture clock. The calculation result from the DUT 2 captured by the first capture clock is defined as a first calculation result. A period in which one capture clock pulse operation is performed in one capture operation period is defined as a capture cycle.

  Note that the first capture clock may not be applied first during one capture operation period, but may be applied later. The second capture clock only needs to be applied after the first capture clock in one capture operation period.

  The calculation result from the DUT 2 is input to the data input terminal DATA during the capture operation period. A test signal is input to the scan-in terminal SIN during the scan shift operation period, and a first operation result captured by the SFF 10 at the preceding stage of the scan chain with the first capture clock is input during the capture operation period.

  A test enable signal (seq_test_enable) is input to the test enable input terminal SEQ_TEST_EN. The seqSFF 60 switches between a normal user operation and a scan test operation according to the test enable signal. For example, a user operation is performed when the test enable signal is low (0), and a scan test operation is performed when the test enable signal is high (1).

  A scan enable signal (scan_enable) is input to the control input terminal SMC. The seqSFF 60 switches between a scan shift operation and a capture operation according to a scan enable signal. For example, when the test enable signal is high (1), the scan shift operation is performed when the scan enable signal is high (1), and the capture operation is performed when the scan enable signal is low (0).

  The NOR gate 61 receives a scan enable signal (scan-enable) input from the control input terminal SMC and a signal input from the data input terminal DATA, and outputs a NOR. The NAND gate 62 receives the first operation result input to the scan-in terminal SIN and the test enable signal, and outputs a NAND. The XOR gate 63 receives the NOR of the NOR gate 61 and the NAND of the NAND gate 62, and outputs an exclusive OR.

  The FF 64 captures a value output from the XOR gate 63 according to a clock signal (clock) input from the clock terminal CLK, and outputs the value from the data output terminal Q. During the scan shift operation period, the FF 64 captures a test signal. Also, during the capture operation period, the FF 64 captures the exclusive OR output from the XOR gate 63 with the second capture clock following the first capture clock. That is, the first operation result captured by the SFF 10 at the preceding stage of the scan chain at the first capture clock is transmitted to the seqSFF 60 at the subsequent stage at the second capture clock after the first capture clock.

  Here, the operation of the semiconductor device 1D will be described. 17 and 18 are diagrams showing examples of operation waveforms of the semiconductor device 1D according to FIG. As shown in FIG. 17, during the user operation, the scan enable signal = 0 (constant LOW) and the test enable signal = 0 (constant LOW) are set. At this time, the SFF 10 and the seqSFF 60 both take in the value input from the data input terminal DATA.

  As shown in FIG. 18, during the scan test operation, the test enable signal is set to 1 (constant HIGH). In the scan test operation, the scan enable signal is set to 1 (HIGH) during the scan shift operation period. At this time, the SFF 10 and the seqSFF 60 take in the value from the scan-in terminal SIN and perform a scan shift operation.

  In the scan test operation, the scan enable signal is set to 0 (LOW) during the capture operation period. At this time, the SFF 10 takes in the value from the data input terminal DATA, and the seqSFF 60 takes in the exclusive OR of the value from the data input terminal DATA and the value from the scan-in terminal SIN. FIG. 19 shows a truth table of the scan flip-flop for the sequential test shown in FIG. The seqSFF 60 has a configuration that satisfies the functions shown in the truth table of FIG.

  Here, it is assumed that two capture clocks are applied in the clock sequential test. It is assumed that the SFF 10 takes in the influence of a certain fault propagation in the first capture cycle. That is, the output value of the data output terminal Q of the SFF 10 after the first capture clock application is inverted between a normal state and a failure state.

  The seqSFF 60 takes in the exclusive OR of the values from the data input terminal DATA and the scan-in terminal SIN in the second capture cycle. Therefore, when the value of the data output terminal Q of the SFF 10 is inverted, the value taken by the seqSFF 60 is also inverted. I do. As described above, the fault captured by the SFF 10 in the first capture cycle is held in the seqSFF 60 in the second capture cycle.

  Suppose a case where the seqSFF 60 in FIG. 15 is used instead of the seqSFF 60. In the clock sequential test, the operation result that has reached the data input terminal DATA of the preceding SFF 10 at the first capture clock is lost without any propagation destination at the next second capture clock unless it reaches the subsequent SFF 10 via the DUT 2. Would. This disappearance probability increases as the number of logic gate stages increases. In general logic, since a large number of logic gates exist, it is unlikely that a failure can be held by applying a capture clock multiple times.

  In contrast, in the semiconductor device 1D according to the fifth embodiment, the operation result that has reached the SFF 10 with the first capture clock during one capture operation period is transmitted to the subsequent seqSFF 60 on the scan chain with the next second capture clock. Propagated. Thus, in the semiconductor device 1D, it is possible to increase the failure detection rate when a plurality of capture clocks are applied.

  In addition, by executing the clock sequential test in the semiconductor device 1D, many failures can be detected in one capture operation period, and as a result, the test time can be reduced.

  The seqSFF 60 is not limited to the logical structure shown in FIG. The configuration of the seqSFF 60 may be any configuration as long as it is a schematic configuration of the scan flip-flop for the sequential test shown in FIG. 20 and satisfies the functions shown in the truth table shown in FIG.

又は否定排他的論理和

が取り込まれる。 That is, when the scan enable signal = 0 and the test enable signal = 0, the value of the data input terminal DATA is taken in. When the scan enable signal = 0 and the test enable signal = 1, the exclusive OR of the values of the data input terminal DATA and the scan-in terminal SIN is obtained.

Or negated exclusive OR

Is taken in.

が取り込まれる。 When the scan enable signal = 1, the value of the scan-in terminal SIN (SIN) or the value of the scan-in terminal SIN is negated regardless of the value of the test enable signal.

Is taken in.

  FIGS. 22, 24 and 26 show other examples of the logic circuit of the seqSFF 60 satisfying the truth table of FIG. 23, 25, and 27 respectively show truth tables of the seqSFF 60A of FIG. 22, the seqSFF 60B of FIG. 24, and the seqSFF 60C of FIG.

  The seqSFF 60A shown in FIG. 22 includes a NOR gate 61, an XOR gate 63, an FF 64, and an OR gate 65. The NOR gate 61 receives a scan enable signal (scan-enable) input from the control input terminal SMC and a signal input from the data input terminal DATA, and outputs a NOR.

  The OR gate 65 has one input terminal of negative logic. The OR gate 65 receives the value from the scan-in terminal SIN and the negative logic of the test enable signal, and outputs a logical sum. The XOR gate 63 receives the NOR of the NOR gate 61 and the OR of the OR gate 65, and outputs an exclusive OR. The FF 64 takes in the value output from the XOR gate 63 and outputs it from the data output terminal Q.

  The operation waveform of the seqSFF 60A shown in FIG. 22 is the same as the operation waveform shown in FIGS. That is, as shown in FIG. 17, during the user operation, the scan enable signal = 0 (constant LOW) and the test enable signal = 0 (constant LOW) are set. Further, as shown in FIG. 18, at the time of the scan test operation, the test enable signal is set to 1 (constant HIGH). In the scan test operation, the scan enable signal is set to 1 (HIGH) during the scan shift operation period.

  As described above, even in the configuration shown in FIG. 22, during the capture operation period, the first operation result captured by the SFF 10 at the previous stage of the scan chain with the first capture clock is the second capture result after the first capture clock. The clock is transmitted to the seqSFF 60 at the subsequent stage.

  The seqSFF 60B shown in FIG. 24 includes a NOR gate 61, a NAND gate 62, an XOR gate 63, an FF 64, and an OR gate 66. The NOR gate 61 receives a scan enable signal (scan-enable) input from the control input terminal SMC and a signal input from the data input terminal DATA, and outputs a NOR.

  The OR gate 66 outputs a logical sum of the scan enable signal and the test enable signal. The NAND gate 62 receives the value from the scan-in terminal SIN and the logical sum from the OR gate 66, and outputs a NAND. The XOR gate 63 receives the NOR of the NOR gate 61 and the NAND of the NAND gate 62, and outputs an exclusive OR. The FF 64 takes in the value output from the XOR gate 63 and outputs it from the data output terminal Q.

  The seqSFF 60C shown in FIG. 26 includes an XOR gate 67, a MUX 68, a MUX 69, and an FF 64. The XOR gate 67 receives the value from the data input terminal DATA and the value from the scan-in terminal SIN, and outputs an exclusive OR. The MUX 68 receives the value from the data input terminal DATA and the exclusive OR from the XOR gate 67. When the test enable signal is low (0), the value from the data input terminal DATA is valid, and when the test enable signal is high (1), the value from the XOR gate 67 is valid.

  The value from MUX 68 is input to MUX 69. Further, the MUX 69 receives a value from the scan-in terminal SIN. For the MUX 69, the value from the MUX 68 is valid when the scan enable signal is low (0), and the value from the scan-in terminal SIN is valid when the MUX 69 is high (1). The FF 64 takes in the value output from the MUX 69 and outputs it from the data output terminal Q.

  FIGS. 28 and 29 show operation waveforms of the semiconductor device in which the seqSFFs 60B and 60C shown in FIGS. 24 and 26 are inserted. As shown in FIG. 28, at the time of a user operation, the scan enable signal is set to 0 (constant LOW). At this time, the test enable signal may have any value of 0/1 (don't care).

  As shown in FIG. 29, in the scan test operation, during the capture operation period, the scan enable signal = 0 (LOW) and the test enable signal = 1 (HIGH). In the scan test operation, the scan enable signal is set to 1 (HIGH) during the scan shift operation period. At this time, the test enable signal may have any value of 0/1 (don't care).

  As described above, by adopting a structure in which an exclusive OR or a negative exclusive OR of the value of the scan-in terminal SIN and the value of the data input terminal DATA is taken, failures that have reached the scan-in terminal SIN and the data input terminal DATA can be simultaneously performed. Can be captured. Thus, when a capture clock is applied a plurality of times in the clock sequential test, it is possible to hold a failure that has reached the seqSFF 60 in each capture cycle. As a result, the number of faults that can be detected in one capture period increases, and the test time required to reach the target detection rate can be reduced.

Embodiment 6 FIG.
A semiconductor device according to a sixth embodiment in which a scan flip-flop for sequential test (seqSFF) is inserted will be described with reference to FIG. FIG. 30 is a diagram showing a configuration of a semiconductor device 1E according to the sixth embodiment in which a seqSFF is inserted.

  As shown in FIG. 30, the semiconductor device 1E includes a DUT 2, a PRPG 3, a MISR 4, an LBIST controller 5, and a plurality of seqSFFs 60. Note that the configuration other than the seqSFF 60 is the same as that described with reference to FIG. 1, and a detailed description thereof will be omitted.

  The semiconductor device 1E has one or more scan chains. In the example shown in FIG. 30, each scan chain is composed of only seqSFF60. In FIG. 30, one scan chain constituted by the seqSFF 60 is shown as a scan chain 6D. In the scan chain 6D, five seqSFFs 60 are serially connected.

  The seqSFF 60 has the same configuration as that shown in FIG. Instead of the seqSFF 60, it is also possible to use a seqSFF having another configuration that satisfies the function of the truth table shown in FIG.

  A scan enable signal is input to a control input terminal SMC of each seqSFF 60. A test enable signal is input to a test enable input terminal SEQ_TEST_EN of each seqSFF 60. Note that the test enable input terminal SEQ_TEST_EN is not necessarily controlled by an external input terminal, but may be controlled by a test mode register or the like.

  During a user operation, a test enable signal = 0 and a scan enable signal = 0 are applied. A test enable signal = 0 and a scan enable signal = 0 are supplied to a control input terminal SMC and a test enable input terminal SEQ_TEST_EN of each seqSFF 60, respectively. As a result, the value input from the scan-in terminal SIN is cut off, and the seqSFF 60 takes in the value from the data input terminal DATA.

  At the time of the scan test operation, the test enable signal = 1 is set. During the scan shift operation period, the scan enable signal = 1 is set. Each seqSFF 60 performs a scan shift operation by taking in the value from the scan-in terminal SIN. At the time of the capture operation, the scan enable signal = 0 is set. Each seqSFF 60 takes in the exclusive OR of the value from the data input terminal DATA and the value from the scan-in terminal SIN.

  Therefore, when a plurality of capture clocks are applied by the clock sequential test, a failure that reaches the seqSFF 60 in a certain capture cycle is captured by the subsequent seqSFF 60 on the scan chain via the scan-in terminal SIN in the next capture cycle.

  For example, when the number of stages of the scan chain 6D is N, a failure captured in the head seqSFF 60 may be held by the seqSFF 60 on the scan chain 6D until N capture clocks are applied at most. As a result, the number of faults that can be detected during the capture operation period in the clock sequential test can be increased.

  Here, the effect of reducing the test time will be described with reference to FIG. FIG. 31 is a diagram illustrating a failure detection rate with respect to a test time of the semiconductor device 1E according to the sixth embodiment. In FIG. 31, the horizontal axis indicates the test time, and the vertical axis indicates the failure detection rate. Also, in FIG. 31, the solid line indicates the result of the semiconductor device 1E using the seqSFF 60 according to the embodiment, and the broken line indicates the result of the semiconductor device when the SFF 10 is used instead of the seqSFF 60 in FIG. .

  As shown in FIG. 31, in the semiconductor device 1E according to the sixth embodiment, by using the seqSFF60, it is possible to achieve the target failure detection rate in a shorter test time than when using the SFF10.

Embodiment 7 FIG.
A semiconductor device according to the seventh embodiment in which a scan flip-flop for sequential test (seqSFF) is inserted will be described with reference to FIG. FIG. 32 is a diagram showing a configuration of a semiconductor device 1F according to the seventh embodiment in which a seqSFF is inserted.

  In a semiconductor device 1F shown in FIG. 32, a part of SFF is replaced by seqSFF60 in a general LBIST configuration. Instead of the seqSFF 60, it is also possible to use a seqSFF having another configuration that satisfies the function of the truth table shown in FIG. In FIG. 32, “FF” indicates a flip-flop having no scan function such as scan-in and scan-out. Here, a flip-flop having no scan function is referred to as a normal flip-flop (hereinafter, normal FF).

  The semiconductor device 1F has one or more scan chains. In the example shown in FIG. 32, at least one scan chain 6E among a plurality of scan chains incorporates a shift register structure 7A in user logic. In the shift register structure 7A, the head is replaced by seqSFF60, and two normal FFs are serially connected at the subsequent stage of seqSFF60. In the scan chain 6E, seqSFFs 60 are arranged before and after the shift register structure 7A.

  The data output terminal Q of the preceding seqSFF 60 is connected to the scan-in terminal SIN of the seqSFF 60 of the shift register structure 7A. The operation result from the DUT 2 captured by the seqSFF 60 at the head of the shift register structure 7A is directly taken into the normal FF at the subsequent stage. The data output terminal Q of the last normal FF of the shift register structure 7A is connected to the input to the DUT 2 and the scan-in terminal SIN of the next seqSFF 60 on the scan chain 6E.

  In the example illustrated in FIG. 32, a shift register structure 7B including one seqSFF and one normal FF, a shift register structure 7C including one seqSFF and two normal FFs are configured in the user logic. The shift register structure 7B and the shift register structure 7C constitute one scan chain.

  In the shift register structure 7B, a normal FF is serially connected after the seqSFF60. In the shift register structure 7C, two normal FFs are serially connected after the seqSFF 60. The data output terminal Q of the normal FF of the shift register structure 7B is connected to the input to the DUT 2 and the scan-in terminal SIN of the seqSFF 60 of the shift register structure 7C.

  Although not shown here, FFs other than the shift register structure are replaced with seqSFF60. The output of the seqSFF 60 or the shift register structure is connected to the scan-in terminal SIN of the seqSFF 60 connected to the subsequent stage, thereby forming a scan chain. In the shift register structures 7A to 7C and other shift register structures, the scan shift operation is performed in the same manner as in the case where the scan chain is constructed by the SFF.

  As described in the sixth embodiment, the scan enable signal is input to the control input terminal SMC of each seqSFF 60 in the seventh embodiment. A test enable signal is input to a test enable input terminal SEQ_TEST_EN of each seqSFF 60.

  In the seventh embodiment, when a plurality of capture clocks are applied by the clock sequential test, a failure that has reached the first seqSFF 60 of the shift register structure in a certain capture cycle is not lost in the next capture cycle, and is not lost in the next capture cycle. Propagate to normal FF. This makes it possible to improve the efficiency of the clock sequential test.

  In the seventh embodiment, a part other than the head of the shift register structure is incorporated in the scan chain while keeping the normal FF. Therefore, an increase in the area can be suppressed as compared with the case where all the flip-flops have a scan function.

Embodiment 8 FIG.
A semiconductor device in which a scan flip-flop for sequential test (seqSFF) according to the eighth embodiment is inserted will be described with reference to FIG. FIG. 33 is a diagram showing a configuration of a semiconductor device 1G in which a seqSFF according to the eighth embodiment is inserted.

  Some of the user FFs in the circuit do not contribute to the improvement of the efficiency of the clock sequential test even when replaced with the seqSFF60. Since the seqSFF 60 has a larger area than the SFF, replacing all the user FFs with the seqSFF 60 increases the area.

  Therefore, the semiconductor device 1G according to the eighth embodiment has a structure in which the replacement target of the seqSFF 60 is limited to some user FFs. In FIG. 33, a flip-flop having no scan function is denoted as FF, and a flip-flop having a scan function is denoted as SFF.

  First, in the eighth embodiment, when a plurality of capture clocks are applied in the clock sequential test, a user FF that efficiently increases the number of detected faults when faults reaching the data input terminal DATA are accumulated is selected.

  The selection of the user FF that contributes to the improvement of the efficiency of the clock sequential test can be obtained by using a combinational logic amount of an input cone to the data input terminal DATA, a failure-based failure simulation, or the like. Then, only the selected user FF is replaced with the seqSFF 60 to construct a scan chain.

  FIG. 33 shows an example of the semiconductor device 1G in which the replacement target of the seqSFF 60 is limited to some of the user FFs. The semiconductor device 1G has one or more scan chains. In the example shown in FIG. 33, a shift register structure 7D in user logic is incorporated in at least one scan chain 6F among a plurality of scan chains. The scan chain 6F does not include the SFF. The scan chain 6F has two seqSFFs 60 and a shift register structure 7D arranged between the two seqSFFs 60 and having the seqSFF 60 at the top. The scan chain 6F has the same configuration as the scan chain 6E according to the seventh embodiment, and thus a detailed description is omitted.

  In FIG. 33, since the shift register structure 7D is included in the selected user FF, the shift register structure 7D is incorporated in the scan chain 6F, but the present invention is not limited to this. All the selected user FFs may be replaced with seqSFFs 60, and the scan chain 6F may be configured only with the seqSFFs 60.

  Further, at least one scan chain 6G among the plurality of scan chains does not include the seqSFF60. The scan chain 6G has two SFFs, and a shift register 8 disposed between the two SFFs and having the SFF at the top. The shift register 8 includes an SFF and two FFs. Although the scan chain 6G includes the shift register 8, there may be a scan chain that does not include the shift register.

  In this way, by limiting the replacement target to the seqSFF 60 to a part of the user FFs having a high effect of improving the efficiency of the clock sequential test, it is possible to suppress an increase in the area and to shorten the test time. .

Embodiment 9 FIG.
The semiconductor device according to the ninth embodiment in which the scan flip-flop for sequential test (seqSFF) is inserted will be described with reference to FIG. FIG. 34 shows a configuration of a semiconductor device 1H in which a seqSFF according to the ninth embodiment is inserted. As shown in FIG. 9, the semiconductor device 1H includes a DUT 2, a PRPG 3, a MISR 4, an LBIST controller 5, a seqSFF60, and a seqSFF70. In FIG. 34, seqSFF60 is indicated as seqSFF, and seqSFF70 is indicated as seqSFF2.

  In the semiconductor device 1H, at least one scan chain 6H among the plurality of scan chains includes the seqSFF60 and the seqSFF70. In the example shown in FIG. 34, a seqSFF 70 is arranged at the head of the scan chain 6H, a shift register structure including a seqSFF 60 and two normal FFs is arranged at the subsequent stage, and the seqSFF 60 is connected at the subsequent stage.

  As the seqSFF 60, the one shown in FIG. 16 is used. Although the seqSFF 60 is used in the example illustrated in FIG. 34, a seqSFF having another configuration that satisfies the function of the truth table illustrated in FIG. 21 may be used instead of the seqSFF 60. Structures other than the seqSFF 70 are the same as those described with reference to FIG. 33, and thus detailed description will be omitted.

  In the other scan chains, the SFF is arranged at the head, and the SFF, two normal FFs, and the SFF are sequentially connected to the subsequent stage. That is, the other scan chains include shift registers. However, the present invention is not limited to this, and seqSFF60 and seqSFF70 may be included in all scan chains.

  In the semiconductor device 1H according to the ninth embodiment, in the clock sequential test, the fault propagated to the last seqSFF 60 can be held on the scan chain 6H. As shown in FIG. 34, the seqSFF 70 includes an AND gate 71, an XOR gate 72, a MUX 73, an FF 74, a data input terminal DATA, a data input terminal DATA2, a test enable input terminal SEQ_TEST_EN, a scan-in terminal SIN, a control input terminal SMC, and a clock terminal. CLK and a data output terminal Q.

  The output of the seqSFF 70 is connected to the scan-in terminal SIN of the subsequent seqSFF 60. The output of the last seqSFF 60 is connected to the data input terminal DATA2 of the seqSFF 70. Like the seqSFF 60, the seqSFF 70 can capture the operation result from the DUT 2 with each of a plurality of capture clocks during one capture operation period.

  The calculation result from the DUT 2 is input to the data input terminal DATA during the capture operation period. Further, a first operation result captured by the last seqSFF 60 with the first capture clock during the capture operation period is input to the data input terminal DATA2. That is, the seqSFF 70 has two data input terminals.

  AND gate 71 outputs a logical product of a signal input from data input terminal DATA2 and a test enable signal. The XOR gate 72 receives the signal input from the data input terminal DATA and the logical product input from the AND gate 71, and outputs an exclusive OR.

  The MUX 73 receives a signal input from the scan-in terminal SIN and a signal output from the XOR gate 72. The MUX 73 switches between a scan shift operation and a capture operation according to a scan enable signal input from the control input terminal SMC. In the example shown in FIG. 34, the input from the scan-in terminal SIN of the MUX 73 becomes valid when the scan enable signal is high (1). When the scan enable signal is low (0), the output from the XOR gate 72 of the MUX 73 is valid.

  The FF 74 takes in the value output from the MUX 73 in response to the clock signal (clock 2) input from the clock terminal CLK, and outputs the value from the data output terminal Q to the scan-in terminal SIN of the seqSFF 60 at the subsequent stage.

  The seqSFF 70 takes in the value of the scan-in terminal SIN when the scan enable signal = 1. When the test enable signal = 0 and the scan enable signal = 0, the seqSFF 70 takes in the value from the data input terminal DATA. When the test enable signal = 1 and the scan enable signal = 0, the exclusive OR of the value of the data input terminal DATA and the value of the data input terminal DATA2 is captured by the second capture clock following the first capture clock.

  That is, the seqSFF 70 can simultaneously capture failures that have reached both the data input terminal DATA and the data input terminal DATA2. Therefore, the first operation result captured by the last seqSFF 60 of the scan chain 6H with the first capture clock is transmitted to the forefront seqSFF 70 with the second capture clock after the first capture clock.

  As described above, in the semiconductor device 1H according to the ninth embodiment, even when a plurality of capture clocks are applied during one capture operation period in the clock sequential test, the semiconductor device 1H captures the data into the last seqSFF 60 of the scan chain 6H with a certain capture clock. The fault that has occurred is propagated to the seqSFF 70 at the forefront stage at the next capture clock and does not disappear.

  In the configurations of the fifth to eighth embodiments, in the clock sequential test, the operation result taken into the seqSFF 60 at the last stage of the scan chain with a certain capture clock has no propagation destination and disappears in the next capture cycle.

  However, when the circuit configuration shown in FIG. 34 is used as in the ninth embodiment, the operation result captured in the last seqSFF 60 can be propagated to the foremost seqSFF 70 by the capture clock of the next capture cycle, and the disappearance can be reduced. Can be prevented. As a result, when the capture clock is applied a plurality of times during the capture operation, the number of detectable faults increases, and the test time can be reduced and the fault detection rate can be improved.

  The seqSFF2 is not limited to the logical structure of the seqSFF 70 shown in FIG. The configuration of the seqSFF 70 is a schematic configuration of the scan flip-flop for the sequential test shown in FIG. 35, and any configuration may be used as long as it satisfies the functions shown in the truth table shown in FIG.

又は否定排他的論理和

が取り込まれる。 That is, when the scan enable signal = 0 and the test enable signal = 0, the value of the data input terminal DATA is taken in. When the scan enable signal = 0 and the test enable signal = 1, the exclusive OR of the values of the data input terminals DATA and DATA2 is obtained.

Or negated exclusive OR

Is taken in.

が取り込まれる。 When the scan enable signal = 1, the value of the scan-in terminal SIN (SIN) or the value of the scan-in terminal SIN is negated regardless of the value of the test enable signal.

Is taken in.

Embodiment 10 FIG.
A semiconductor device according to the tenth embodiment in which a scan flip-flop for sequential test (seqSFF) is inserted will be described with reference to FIG. FIG. 37 shows a configuration of a semiconductor device 1I according to the tenth embodiment in which a seqSFF is inserted. As shown in FIG. 37, the semiconductor device 1I includes a DUT 2, a PRPG 3, a MISR 4I, an LBIST controller 5, and a seqSFF60. In the semiconductor device 1I, in the clock sequential test, a fault propagated to the last seqSFF 60 can be held by the MISR 4I.

  In the semiconductor device 1I, at least one scan chain 6I among the plurality of scan chains includes a seqSFF 60 and a normal FF. In the example shown in FIG. 37, the seqSFF60 is arranged at the head of the scan chain 6I, a shift register structure including the seqSFF60 and two normal FFs is arranged at the subsequent stage, and the seqSFF60 is connected at the subsequent stage.

  As the observation SFF 30, one having the configuration shown in FIG. 16 is used. Although the seqSFF 60 is used in the example illustrated in FIG. 34, a seqSFF having another configuration that satisfies the function of the truth table illustrated in FIG. 21 may be used instead of the seqSFF 60. In other scan chains, an SFF is arranged at the head, and an SFF, two normal FFs, and an SFF are sequentially connected at the subsequent stage. The configuration of the scan chain is the same as that in the example of FIG. 33, and thus detailed description is omitted.

  The first operation result captured by the last seqSFF 60 of the scan chain 6I at the first capture clock is transmitted to the MISR 4I at the second capture clock after the first capture clock. In the example shown in FIG. 37, the clock signal (clock2) is input to the MISR 4I. The MISR 4C captures a value output from the last seqSFF 60 in synchronization with the clock signal (clock2).

  In a normal scan test, it is not necessary to observe the output of the last flip-flop of the scan chain during the capture operation. For this reason, the normal MISR does not have a function of capturing the output value of the last-stage flip-flop during the capture operation.

  In the tenth embodiment, the MISR 4I operates while being supplied with a clock even during the capture operation. Thus, the MISR 4I can capture the output value of the seqSFF 60 at the last stage of the scan chain 6I even when a plurality of capture clocks in the clock sequential test are applied.

  As described above, in each capture cycle, the fault that has reached the last seqSFF 60 can be captured by the MISR 4I and can be observed without losing the fault. Thus, the number of faults that can be detected during one capture operation period of the clock sequential test can be increased, and the test time can be reduced.

  A design apparatus 200 according to the embodiment will be described with reference to FIGS. FIG. 38 is a diagram showing a configuration of a design apparatus 200 for designing a semiconductor device according to the fifth to tenth embodiments. FIG. 39 is a diagram showing a design flow of the semiconductor device according to the embodiment. The design device 200 is for designing a semiconductor device using the above-described seqSFF and having high efficiency in a clock sequential test.

  The design device 200 includes an arithmetic processing device 210, a storage device 220, a control input device 230, and a display output device 231. The control input device 230 and the display output device 231 have the same configuration as the control input device 130 and the display output device 131 described with reference to FIG.

  The arithmetic processing unit 210 is a device capable of loading a program required for designing the semiconductor devices 1D to 1I and executing each functional process required for the design, and includes a CPU, a memory, and the like. The arithmetic processing unit 210 has a scanning program 212. The scanning program 212 replaces the general scanning function with the seqSFF that satisfies the function of the truth table in FIG. It has a function to select a user FF that is more effective.

  The storage device 220 has a function library 222, a test constraint DB 223, and a scan netlist 226. The storage device 220 refers to a storage medium such as an HDD disk or a memory for storing library and netlist information.

  The netlist 221 stores cell information of an AND gate, an OR gate, an XOR gate, etc., connection information between terminals, and the like, in addition to the above-described seqSFF cell information. The function library 222 stores cell functions and the like. The test constraint DB 223 stores information necessary for circuit operation at the time of testing.

  The design device 200 inserts the seqSFF described in the fifth to tenth embodiments using the scan program 212 of the arithmetic processing device 210 and referring to the netlist 221 and the function library 222 and the test constraint DB 223 of the storage device 220. A semiconductor device is generated.

  Here, a design flow of the semiconductor device will be described with reference to FIG. As shown in FIG. 39, first, predetermined information is input to the net list 221, the function library 222, and the test constraint DB 223 (step S31). Then, by analyzing the input information, circuit information and test constraint information are identified (step S32). Here, a scan-capable user FF in the circuit, test constraint information, and the like are acquired. Then, the user FF having the shift register structure is identified from the circuit structure (step S33).

  Then, based on the information of the identified user FFs that can be converted into scans, an arbitrary specified number of user FFs to be replaced with seqSFFs are selected in consideration of the area overhead, and candidates for replacement with seqSFFs are determined (step S34). The algorithm for selecting the replacement target candidate to the seqSFF can be reduced to, for example, a problem of finding the maximum number of observable faults on the input logic cone of the replacement target user FF.

  When the candidate to be replaced with seqSFF has been determined, the user FF to be replaced with seqSFF is replaced with seqSFF, and a scan chain is constructed using the subsequent shift register structure (step S35). Then, the other user FFs are replaced with SFFs to construct a scan chain (step S36). Thus, the scanned netlist into which the seqSFF has been inserted is output (step S37), and the netlist generation processing ends. By using the design apparatus 200 shown in FIG. 38, it is possible to generate a scanned netlist having a circuit structure with high efficiency of the sequential test.

  By using the scan netlist generated in this manner, a semiconductor device capable of increasing the number of faults detectable during one capture operation period of the clock sequential test and reducing the test execution time is provided. It becomes possible to design.

  In the following steps, a compression scan circuit or an LBIST circuit is added by a general compression circuit addition program, and a clock sequential test pattern is generated by a general test generation program. Thereby, the effect of reducing the test time as shown in FIG. 31 can be obtained.

  Note that the above embodiments can be combined as appropriate. For example, it is also possible to configure a semiconductor device in which both the test point circuit and the scan flip-flop for sequential test described above are inserted. FIG. 40 shows a configuration example of a semiconductor device in which the test point circuit 20 and the seqSFF 60 are inserted.

  As shown in FIG. 40, at least one of the plurality of scan chains is constituted only by the observation SFF 20. Further, at least one of the other scan chains is constituted only by the seqSFF 60. In the example shown in FIG. 40, five observation SFFs 20 are serially connected in one scan chain. In another scan chain, five seqSFFs 60 are serially connected.

  As described above, by inserting the observation SFF 20 and the seqSFF 60, when performing the clock sequential test, it is possible to suppress an increase in the area overhead due to the insertion of the test point, and to shorten the test time and increase the fault detection rate. It becomes possible.

  As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment described above, and various changes may be made without departing from the gist of the invention. It goes without saying that it is possible.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 1A-1I Semiconductor device 2 DUT
3 PRPG
4 MISR
4C MISR
4I MISR
5 LBIST controller 6A-6I scan chain 7A-7D shift register structure 8 shift register 10 SFF
11 MUX
12 FF
20 SFF for observation
21 XOR gate 22 MUX
23 FF
30 Observation SFF
31 NOR gate 32 XOR gate 33 FF
40 Observation SFF
41 XOR gate 42 MUX
43 FF
50 Observation SFF
51 XOR gate 52 MUX
53 FF
60 seqSFF
60A-60C seqSFF
61 NOR gate 62 NAND gate 63 XOR gate 64 FF
65 OR gate 66 OR gate 67 XOR gate 68 MUX
69 MUX
70 seqSFF
71 AND gate 72 XOR gate 73 MUX
74 FF
SEQ_TEST_EN Test enable input terminal 100 Design device 110 Processing unit 111 Test point insertion program 112 Scanning program 120 Storage device 121 Netlist 122 Function library 123 Test constraint DB
124 Test Point Inserted Netlist 125 Test Point Insertion Information DB
126 scan netlist 130 control input device 131 display output device 200 design device 210 arithmetic processing device 212 scan program 220 storage device 221 netlist 222 function library 223 test constraint DB
226 Scanned netlist 230 Control input device 231 Display output device DATA Data input terminal SIN Scan-in terminal SMC Control input terminal CLK Clock terminal Q Data output terminal

Claims (26)

A test point circuit inserted into a combinational circuit that outputs an operation result according to a test signal to be scanned in,
The test point circuit includes:
A scan-in terminal to which the test signal is input during a scan shift operation period;
A data input terminal to which an operation result from the combinational circuit is input;
An XOR gate that receives an operation result input to the data input terminal and a first operation result input to the scan-in terminal, and outputs an exclusive OR, during one capture operation period of the clock sequential test ;
A flip-flop that captures the exclusive OR with a second capture clock after the first capture clock;
With
The plurality of test point circuits form a scan chain,
In the capture operation period, the first operation result captured by the test point circuit at the preceding stage of the scan chain is captured by the second capture clock after the first capture clock ,
The scan-in terminal receives the first operation result,
Test point circuit. In the capture operation period, further includes a NOR gate that receives an operation result input to the data input terminal and a control signal for switching from the scan shift operation to the capture operation, and outputs a NOR operation ,
The XOR gate receives the first operation result input to the scan-in terminal and the NOR, and outputs an exclusive OR ,
The flip-flop captures the exclusive OR input from the XOR gate with the second capture clock.
The test point circuit according to claim 1. A second data input terminal to which the first operation result captured by the last-stage test point circuit of the scan chain during the capture operation period is input ;
The XOR gate, said in the capture operation period, to receive the said data input of the first arithmetic results input inputted calculation result and said second data input terminal to the terminal, and outputs the exclusive logical sum,
The flip-flop captures the exclusive OR with the second capture clock.
The test point circuit according to claim 1. A combinational circuit that outputs an operation result according to a test signal to be scanned in;
A plurality of test point circuits inserted into the combinational circuit,
With
The plurality of test point circuits form a scan chain,
The scan chain is
In one capture operation period of the clock sequential test,
A first test point circuit for capturing a first operation result with a first capture clock;
A second test point circuit that captures the first operation result captured by the first test point circuit at a second capture clock after the first capture clock;
Only including,
The second test point circuit includes:
A scan-in terminal to which the test signal is input during a scan shift operation period and the first operation result captured by a test point circuit at a preceding stage of the scan chain during the capture operation period;
A data input terminal to which an operation result from the combinational circuit is input;
An XOR gate that receives an operation result input to the data input terminal and the first operation result input to the scan-in terminal during the capture operation period, and outputs an exclusive OR;
A flip-flop that captures the exclusive OR with the second capture clock;
Comprising,
Semiconductor device. The second test point circuit is provided at a stage subsequent to the first test point circuit.
The semiconductor device according to claim 4 . A third test point circuit provided at the last stage of the scan chain;
The first test point circuit is provided at the forefront of the scan chain,
The third test point circuit captures a second operation result with the first capture clock,
The first test point circuit receives the second operation result captured by the third test point circuit at the second capture clock;
The semiconductor device according to claim 5 . The first test point circuit is provided at the last stage of the scan chain,
The second test point circuit is provided at the forefront of the scan chain.
The semiconductor device according to claim 4 . Further comprising a compressor for compressing the response result output from the scan chain,
The compressor captures, with the second capture clock, a calculation result captured by a test point circuit provided at the last stage of the scan chain with the first capture clock.
The semiconductor device according to claim 4 . The second test point circuit includes:
In the capture operation period, further includes a NOR gate that receives an operation result input to the data input terminal and a control signal for switching from the scan shift operation to the capture operation, and outputs a NOR operation ,
The XOR gate receives the first operation result input to the scan-in terminal and the NOR, and outputs an exclusive OR ,
The flip-flop captures the exclusive OR input from the XOR gate with the second capture clock.
The semiconductor device according to claim 4 . The second test point circuit includes:
A second data input terminal to which the first operation result is input during the capture operation period ;
The XOR gate, said in the capture operation period, to receive the said data input of the first arithmetic results input inputted calculation result and said second data input terminal to the terminal, and outputs the exclusive logical sum,
The flip-flop captures the exclusive OR with the second capture clock.
The semiconductor device according to claim 4 . A pseudorandom number generator provided on the input side of the scan chain and supplying a pseudorandom number as the test signal,
The semiconductor device according to claim 5 . A semiconductor device design device including an arithmetic processing device capable of executing a predetermined process according to a preset program,
The semiconductor device includes:
A combinational circuit that outputs an operation result according to a test signal to be scanned in;
A plurality of test point circuits inserted into the combinational circuit,
With
The plurality of test point circuits form a scan chain,
The scan chain is
In one capture operation period of the clock sequential test,
A first test point circuit for capturing a first operation result with a first capture clock;
A second test point circuit that captures the first operation result captured by the first test point circuit at a second capture clock after the first capture clock;
Including
The arithmetic processing device is a design device that executes a circuit generation process of generating the semiconductor device with reference to a netlist ,
The second test point circuit includes:
A scan-in terminal to which the test signal is input during a scan shift operation period and the first operation result captured by a test point circuit at a preceding stage of the scan chain during the capture operation period;
A data input terminal to which an operation result from the combinational circuit is input;
An XOR gate that receives an operation result input to the data input terminal and the first operation result input to the scan-in terminal during the capture operation period, and outputs an exclusive OR;
A flip-flop that captures the exclusive OR with the second capture clock;
Comprising,
Design equipment. The arithmetic processing unit,
Performing an analysis process for analyzing the probability that the operation result from the combinational circuit becomes a predetermined logic state,
Based on the result of the analysis processing, select the insertion position of the test point circuit,
Inserting the first test point circuit and the second test point circuit at the selected insertion position;
Configuring the scan chain using the first test point circuit and the second test point circuit;
The design device according to claim 12 . The arithmetic processing unit,
Executing a process of connecting the second test point circuit to a stage subsequent to the first test point circuit in the scan chain;
The design device according to claim 12 . The semiconductor device includes:
A third test point circuit that configures the scan chain together with the first and second test point circuits and captures a second operation result with the second capture clock;
The arithmetic processing unit,
Connecting the first test point circuit to the first stage of the scan chain and the third test point circuit to the last stage of the scan chain so that the first test point circuit receives the second operation result. Execute,
The design device according to claim 12 . The arithmetic processing unit,
Executing a process of connecting the first test point circuit to the last stage of the scan chain and connecting the second test point circuit to the foremost stage of the scan chain;
The design device according to claim 12 . The arithmetic processing device executes a process of inserting a compressor that compresses a response result output from the scan chain on an output side of the test point circuit provided at the last stage of the scan chain,
The design device according to claim 12 . The compressor captures, with the second capture clock, a calculation result captured by a test point circuit provided at the last stage of the scan chain with the first capture clock.
The design device according to claim 17 . A scan flip-flop for a sequential test, which configures a scan chain and can switch between a scan shift operation that operates as a shift register and a capture operation that captures an operation result from the combinational circuit,
The scan flip-flop for the sequential test,
A test enable input terminal to which a test enable signal is input;
In response to the test enable signal, during one capture operation period of the clock sequential test,
At the second capture clock after the first capture clock, the first cell of the preceding stage of the scan flip-flop for the sequential test in the scan chain or the last cell of the scan chain from the combinational circuit captured by the first capture clock. Capturing the first operation result of
Scan flip-flop for sequential test. The scan flip-flop for the sequential test,
Taking in the second capture clock an exclusive OR or a negative exclusive OR of the first operation result and the second operation result from the combinational circuit captured by the sequential test scan flip-flop;
The scan flip-flop for a sequential test according to claim 19 . A scan chain including the sequential test scan flip-flop according to claim 19 and a first cell, and a combination circuit,
A semiconductor device capable of switching between a scan shift operation in which the first cell and the sequential test scan flip-flop in the scan chain operate as a shift register and a capture operation to capture an operation result from the combinational circuit. ,
The first cell is
Capturing a first operation result with a first capture clock in one capture operation period of a clock sequential test;
The scan flip-flop for the sequential test,
A test enable input terminal to which a test enable signal is input;
Capturing the first operation result at a second capture clock after the first capture clock in response to the test enable signal;
Semiconductor device. The sequential test scan flip-flop is configured to perform an exclusive OR or negation of the first operation result and the second operation result from the combinational circuit captured by the sequential test scan flip-flop with the second capture clock. Including exclusive OR,
The semiconductor device according to claim 21 . The first cell is a scan flip-flop,
In the scan chain, the sequential test scan flip-flop is connected to a stage subsequent to the first cell.
The semiconductor device according to claim 21 . The first cell has a configuration similar to that of the sequential test scan flip-flop.
The semiconductor device according to claim 21 . The scan chain is
A second cell having a configuration similar to that of the sequential test scan flip-flop;
A flip-flop that directly captures a third operation result from the combinational circuit captured by the second cell;
Further comprising a shift register structure including:
The semiconductor device according to claim 21 . Further comprising a compressor for compressing the response result output from the scan chain,
The compressor observes, with the second capture clock, an operation result captured by the sequential test scan flip-flop provided at the last stage of the scan chain with the first capture clock.
The semiconductor device according to claim 23 .

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