JP2017062222A - Test point circuit, scan flip-flop for sequential test, semiconductor device and design device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress increase of area overhead, and to shorten a test time, by reducing the insertion number of test point circuits necessary for achieving a target fault detection rate.SOLUTION: A test point circuit in an embodiment constitutes a scan chain. In one-time capture operation period of a clock sequential test, a first arithmetic result captured in a first capture clock by a pre-stage test point circuit or by a last-stage test point circuit is taken in a second capture clock after the first capture clock.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a test point circuit, a sequential test scan flip-flop, a semiconductor device, and a design device, for example, a technique applicable to a logic built-in self test (LBIST).

  There is a scan test as a general test method of LSI (Large Scale Integration). In order to make the scan test executable, the flip-flop (FF) in the circuit is replaced with an FF with a multiplexer (MUX) called a scan FF. The MUX can switch between a test input and a normal operation input by a scan enable signal.

  During the scan test, the scan FFs are serially connected and operate as a shift register (this is called a “scan chain”) that can be controlled and observed from an external terminal of the LSI. By shifting the scan chain, an arbitrary test pattern (load data) is supplied from the test input to each scan FF (load). This is called a “scan shift operation”. The test pattern set in each scan FF is applied to the combinational circuit to be tested.

  Then, by switching the scan enable signal, the operation result in the combinational circuit is taken into the scan FF from the normal operation input. This is called “capture operation”. The calculation result obtained by the capture operation is shifted again by the scan FF, and a response is observed (unload). Simultaneously with this unloading, the next test pattern is applied (loaded). An LSI scan test is executed by comparing the value (unload data) unloaded by the tester with its expected value.

  In the scan test, since the number of shift cycles corresponding to the number of scan FFs connected to the scan chain is required, a very large number of test steps is required. In addition, in order to execute an LSI scan test, it is necessary to store test data including expected values of load data and unload data necessary for a scan shift operation in a tester memory. When the number of test steps is very large, the test data cannot be stored in the tester memory, and the necessary test cannot be performed.

  As an example of design for testability (DFT) that reduces the amount of test data, a Logic Built-in Self Test (LBIST) has been proposed (Non-Patent Document 1). In LBIST, the load data generated from the pseudo random number generator (PRPG) in the circuit is supplied to the scan chain to perform the scan shift operation, and the unload data after the capture operation is compressed in the response in the circuit. (Multiple Input Signature Register: MISR).

  Therefore, it is not necessary to apply test data from the external tester during the scan test period by LBIST, and the test can be executed only by supplying the clock. Then, after executing the test for an arbitrary time, the value compressed by the MISR is observed by an external tester to determine the presence or absence of a failure. Therefore, the amount of test data required for the external tester is only the control sequence of the LBIST controller, the initial values of PRPG and MISR, and the expected value output from the MISR.

Debaleena Das, Nur A. Touba, "Reducing test data volume using external / LBIST hybrid test patterns", International Test Conference 2000

  Power-on Self-Test (POST) is required in order to realize functional safety in accordance with ISO 26262, which is an international functional safety standard for in-vehicle devices for automobiles. In POST, the test of the logic unit is performed by LBIST due to the limitation of the test data amount. In LBIST, since a test is executed by applying a random number pattern, there is a high possibility that many faults in the circuit end without being detected. For this reason, test point insertion (TPI) is generally performed so that the probability of detecting a fault in the circuit increases when a random number is applied. In LBIST, a large amount of TPI is required to increase the failure detection rate, and there is a problem that the area overhead (hereinafter referred to as area OH) increases. Further, since there is a limit on the POST execution time, it is necessary to increase the failure detection rate while reducing the test time.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

According to one embodiment, the test point circuit constitutes a scan chain, and in the one capture operation period of the clock sequential test, the test point circuit of the previous stage or the test point circuit of the last stage is the first capture clock. The captured first calculation result is captured by the second capture clock after the first capture clock.
Note that a representation in which the circuit of the above embodiment is replaced with a method, apparatus, or system, and a program that causes a computer to execute a part of the processing in the circuit are also effective as an aspect of the present invention.

  According to the one embodiment, it is possible to reduce the number of test point circuits inserted to achieve the target failure detection rate, suppress an increase in area overhead, and shorten a test time. .

It is a figure which shows an example of the semiconductor device which can perform LBIST. It is a figure explaining insertion of the test point circuit for control. It is a figure explaining insertion of the test point circuit for observation. It is a figure which shows the example of an operation waveform of a scan test. It is a figure which shows the example of an operation | movement waveform of a clock sequential test. 1 is a diagram showing a configuration of a semiconductor device in which a test point circuit according to a first embodiment is inserted. FIG. 4 is a diagram showing a failure detection rate with respect to a scan test time of the semiconductor device according to the first embodiment. FIG. 5 is a diagram showing another configuration of the test point circuit according to the first embodiment. FIG. 6 is a diagram showing a configuration of a semiconductor device in which a test point circuit according to a second embodiment is inserted. It is a figure which shows the structure of the semiconductor device which inserted the test point circuit which concerns on Embodiment 3. FIG. FIG. 6 is a diagram showing a configuration of a test point circuit according to a fourth embodiment. It is a figure which shows the structure of the design apparatus which designs the semiconductor device which concerns on embodiment. It is a figure which shows the design flow of the semiconductor device which concerns on embodiment. It is a figure which shows the design flow of the semiconductor device which concerns on embodiment. FIG. 10 is a diagram illustrating a configuration of a semiconductor device in which a sequential test scan flip-flop according to a fifth embodiment is inserted. FIG. 10 is a diagram showing a configuration of a sequential test scan flip-flop according to a fifth embodiment. FIG. 16 is a diagram illustrating an example of operation waveforms of the semiconductor device according to FIG. 15. FIG. 16 is a diagram illustrating an example of operation waveforms of the semiconductor device according to FIG. 15. FIG. 17 is a truth table of the sequential test scan flip-flop shown in FIG. 16. FIG. It is a figure which shows schematic structure of the scan flip-flop for a sequential test. FIG. 21 is a truth table of the sequential test scan flip-flop shown in FIG. 20. FIG. FIG. 10 is a diagram showing another configuration of the sequential test scan flip-flop according to the fifth embodiment. FIG. 23 is a truth table of the sequential test scan flip-flop shown in FIG. 22. FIG. FIG. 10 is a diagram showing another configuration of the sequential test scan flip-flop according to the fifth embodiment. FIG. 25 is a truth table of the sequential test scan flip-flop shown in FIG. 24. FIG. FIG. 10 is a diagram showing another configuration of the sequential test scan flip-flop according to the fifth embodiment. FIG. 27 is a truth table of the sequential test scan flip-flop shown in FIG. 26. FIG. FIG. 27 is a diagram showing an example of operation waveforms of the semiconductor device in which the sequential test scan flip-flop shown in FIG. 24 or FIG. 26 is inserted. FIG. 27 is a diagram showing an example of operation waveforms of the semiconductor device in which the sequential test scan flip-flop shown in FIG. 24 or FIG. 26 is inserted. FIG. 10 is a diagram showing a configuration of a semiconductor device in which a sequential test scan flip-flop according to a sixth embodiment is inserted. FIG. 10 is a diagram illustrating a failure detection rate with respect to a scan test time of a semiconductor device according to a sixth embodiment. FIG. 10 is a diagram showing a configuration of a semiconductor device in which a sequential test scan flip-flop according to a seventh embodiment is inserted. FIG. 20 is a diagram illustrating a configuration of a semiconductor device in which a sequential test scan flip-flop according to an eighth embodiment is inserted. FIG. 20 is a diagram illustrating a configuration of a semiconductor device in which a sequential test scan flip-flop according to a ninth embodiment is inserted. FIG. 20 is a diagram showing a schematic configuration of a sequential test scan flip-flop used in the ninth embodiment. FIG. 36 is a truth table of the sequential test scan flip-flop shown in FIG. 35. FIG. It is a figure which shows the structure of the semiconductor device which inserted the scan flip-flop for sequential tests based on Embodiment 10. FIG. It is a figure which shows the structure of the design apparatus which designs the semiconductor device which concerns on embodiment. It is a figure which shows the design flow of the semiconductor device which concerns on embodiment. 1 is a diagram showing a configuration of a semiconductor device in which a test point circuit and a sequential test scan flip-flop according to an embodiment are inserted. FIG.

  Hereinafter, embodiments will be described with reference to the drawings. For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. Specific numerical values and the like shown in the following embodiments are merely examples for facilitating understanding of the invention, and are not limited thereto unless otherwise specified. Note that, in each drawing, the same element is denoted by the same reference numeral, and redundant description is omitted as necessary.

  Each element described in the drawings as a functional block for performing various processes can be configured by a CPU, a memory, and other circuits in terms of hardware, and a program loaded in the memory in terms of software. Etc. Therefore, it is understood by those skilled in the art that these functional blocks can be realized in various forms by hardware only, software only, or a combination thereof, and is not limited to any one.

  The embodiment relates to a semiconductor device capable of executing a logic built-in self test (LBIST), a test point circuit used for the semiconductor device, and a design apparatus for the semiconductor device. First, a semiconductor device capable of executing LBIST will be described with reference to FIG. FIG. 1 is a diagram illustrating an example of a semiconductor device capable of executing LBIST. In the following description, the combinational circuit to be tested is referred to as DUT (Design Under Test).

  As shown in FIG. 1, the semiconductor device 1 includes a DUT 2, a pseudo random number generator (Pseudo Random Pattern Generator: hereinafter referred to as PRPG) 3, a response compressor (Multiple Input Signature Register: hereinafter referred to as MISR) 4, an LBIST. A controller 5 and a scan flip-flop (hereinafter referred to as SFF) 10 are provided.

  In the semiconductor device 1, a plurality of scan chains are constructed by serially connecting a plurality of SFFs 10. In the example shown in FIG. 1, five SFFs 10 are connected to one scan chain. The SFF 10 is a shift scan flip-flop that can switch between a scan shift operation and a capture operation. The SFF 10 includes a MUX (multiplexer) 11, an FF (flip-flop) 12, a data input terminal DATA, a scan-in terminal SIN, a control input terminal SMC, a clock terminal CLK, and a data output terminal Q.

  The MUX 11 receives the test signal input from the scan-in terminal SIN and the calculation result from the DUT 2 input from the data input terminal DATA. The MUX 11 switches between a scan shift operation and a capture operation according to a scan enable signal (scan-enable) input from the control input terminal SMC. That is, the scan enable signal is a control signal for switching between a scan shift operation and a capture operation.

  In the example shown in FIG. 1, the scan-in terminal SIN is valid when the scan enable signal is high (1). Further, when the scan enable signal is low (0), the data input terminal DATA becomes valid. The FF 12 takes in a value output from the MUX 11 according to a clock signal (clock 1 or clock 2) input from the clock terminal CLK, and outputs the value from the data output terminal Q to the scan-in terminal SIN of the SFF 10 in the subsequent stage. Although FIG. 1 shows an example in which the clock signals supplied to each scan chain are different, they may be the same.

  The PRPG 3 is connected to the input side of the plurality of scan chains. The PRPG 3 generates load data (test signal) in LBIST and supplies it to the scan chain. The SFF 10 outputs a test signal input from the scan-in terminal SIN to the subsequent SFF 10 during the scan shift operation period. An arbitrary test pattern is set in each SFF 10 by shifting the scan chain.

  In the capture operation, the value set in each SFF 10 in the shift operation period is supplied to the DUT 2, and the operation result in the DUT 2 is captured in each SFF 10. The MISR 4 is connected to the output side of the plurality of scan chains. The MISR 4 compresses unload data from a plurality of scan chains after the capture operation. This compression result is called a “signature”. The signature compressed by the MISR 4 is compared with an expected value by a control circuit in the circuit at the time of POST operation and by an external tester at the time of a non-defective product test to determine the presence or absence of a failure.

  The LBIST controller 5 is connected to the PRPG 3 and the MISR 4. The LBIST controller 5, PRPG3, and MISR4 are each supplied with a clock signal tck. The LBIST controller 5 supplies an initial value to the PRPG 3. The PRPG 3 generates load data based on the initial value supplied from the LBIST controller 5 in synchronization with the clock signal tck. The initial value of PRPG3 can be arbitrarily rewritten by a test data input signal tdi supplied from the outside.

  The LBIST controller 5 outputs the compression result compressed by the MISR 4 to the external tester as a test data output signal tdo. After the execution of the test for an arbitrary time, the presence or absence of a DUT failure is determined by comparing the compression result with an expected value using an external tester.

  A test point circuit is inserted into the semiconductor device 1 so that the probability of detecting a failure in the circuit increases when a random number is applied. Here, the test point circuit is a logic circuit inserted for the purpose of improving the controllability and observability of signal lines and terminals in the test target circuit.

  “Controllability” is a measure representing how easily the internal state of a DUT can be controlled from an external terminal. Specifically, “controllability” refers to the minimum value of the number of signal lines that must be set to a logical value in order to set the value of any signal line or terminal included in the DUT to 0 or 1. “Observability” is a measure representing how easily the internal state of a DUT can be observed at an external terminal. Specifically, it means the minimum value of the number of signal lines for which a logical value must be set in order to propagate a signal to an observation point.

  By inserting a test point circuit into the circuit to be tested, the failure detection rate in the DUT can be increased when a random number is applied in LBIST. Here, a test point circuit inserted for the purpose of improving controllability is referred to as a control test point circuit. The control test point circuit is a logic circuit that functions as a control point that can set the value of the signal line in the DUT to 0 or 1. The control test point circuit includes, for example, a combinational circuit such as an AND gate and an OR gate, an external input terminal, a flip-flop, and the like.

  A test point circuit inserted for the purpose of improving observability is defined as an observation test point circuit. The observation test point circuit functions as an observation point capable of observing the calculation result of the DUT. The observation test point circuit corresponds to an external output terminal or SFF. Hereinafter, the test point may be abbreviated as TP. Further, in order to improve testability (inspectability, testability), inserting a TP circuit into a signal line of a DUT may be abbreviated as TPI (Test Point Insertion).

  FIG. 2 is a diagram for explaining insertion of the control TP circuit. In the example shown in FIG. 2, as indicated by a broken line, an AND gate, an OR gate, and a control FF are inserted as a control TP circuit with respect to a signal line having a low control probability of a value of 1. Propagation of the value from the control FF can increase the probability of setting the portion where the AND gate and the OR gate are inserted to 1, thereby improving the failure detection rate.

  FIG. 3 is a diagram for explaining the insertion of the observation TP circuit. In the example shown in FIG. 3, as shown by the broken line, the observation FF is inserted in the portion where the failure propagation probability is low up to the end point FF as the observation TP circuit. By connecting the observation FFs by fan-out, the failure can be observed by the observation FF, and the failure detection rate can be improved.

  As described above, in LBIST, in order to increase the failure detection rate, a large amount of TPI is required, and there is a problem that the area OH is increased. In view of such a problem, the present inventors devised applying a clock sequential test (multi-cycle test) in LBIST in order to reduce the number of inserted TPs or LBIST execution time.

  The clock sequential test is a scan test in which a plurality of capture clocks are input during one capture operation period and the response of the test signal by the DUT 2 is captured by the plurality of capture clocks. Here, with reference to FIGS. 4 and 5, operation waveforms of a scan test using a single clock and a clock sequential test using a plurality of clocks will be described.

  4 and 5, the shift of the test signal during the scan shift operation period and the capture of the calculation result during the capture operation period are performed in synchronization with the clock edge of the test clock (test clock). In the following description, the test clock in the capture operation period is referred to as “capture clock”.

  FIG. 4 is a diagram illustrating an example of operation waveforms of a scan test for a single stuck-at fault model in which a single clock is applied during one capture operation period. When the scan enable signal is low (0), the operation result of DUT2 input from the data input terminal DATA is captured. In the example shown in FIG. 4, only one capture clock is input during one capture operation period.

  FIG. 5 is a diagram illustrating an example of operation waveforms of a clock sequential test in which a plurality of clocks are applied during one capture operation period. In the example shown in FIG. 5, three capture clocks are applied during one capture operation period. In FIG. 5, as in FIG. 4, when the scan enable signal is low (0), the operation result of DUT2 input from the data input terminal DATA is captured.

  As described above, in the clock sequential test, the operation result of the DUT 2 can be captured with a plurality of capture clocks in one capture operation period. As a result, it is possible to expand the range in which failures are activated during one capture operation period and increase the number of detectable failures. Therefore, it is possible to reduce the number of inserted TPs necessary for achieving the target failure detection rate or to reduce the LBIST execution time.

  The observation FF used as the observation TP circuit described in FIG. 3 has the same configuration as the SFF described in FIG. 1, and does not assume a clock sequential test. In order to further improve the effect of the clock sequential test, the present inventors have devised a test point circuit in consideration of the clock sequential test.

  The test point circuit according to the embodiment constitutes a scan chain capable of executing an LSI scan test, and performs a clock sequential test. The test point circuit according to the embodiment has a logic structure that can suppress an increase in area overhead due to test point insertion, shorten a test time, and increase a failure detection rate. Specifically, the test point circuit according to the embodiment captures the first capture point captured by the previous test point circuit or the last test point circuit with the first capture clock in one capture operation period of the clock sequential test. The calculation result is captured by the second capture clock after the first capture clock.

  The semiconductor device using the test point circuit according to the embodiment can be applied to, for example, a product on which a power-on self-test (POST) compliant with the international standard ISO26262 is mounted. In addition, this semiconductor device can be applied to a product that is intended to reduce test costs when applying LBIST in a mass production test process, a design device (EDA (electronic design automation) tool) that implements LBIST, or the like. .

Embodiment 1 FIG.
A semiconductor device in which the test point circuit according to the first embodiment is inserted will be described with reference to FIG. FIG. 6 is a diagram showing a configuration of the semiconductor device 1A according to the first embodiment. As shown in FIG. 6, the semiconductor device 1 </ b> A includes a DUT 2, a PRPG 3, a MISR 4, an LBIST controller 5, an SFF 10, and an observation scan flip-flop (hereinafter referred to as an observation SFF) 20. In FIG. 6, the observation SFF 20 is indicated as obsSFF. The configuration other than the observation SFF 20 is the same as that described with reference to FIG.

  A plurality of scan chains are constructed in the semiconductor device 1A. At least one scan chain among the plurality of scan chains is composed of only the observation SFF 20. In the example shown in FIG. 6, one scan chain is configured by only the observation SFF 20, and the remaining scan chains are configured by the SFF 10. The scan chain configured by the SFF 10 is configured separately from the scan chain configured by only the observation SFF 20.

  In FIG. 6, the scan chain constituted by the observation SFF 20 is indicated as a scan chain 6A. In the scan chain 6A, five observation SFFs 20 are serially connected. In other scan chains, five SFFs 10 are connected in series.

  The observation SFF 20 is an observation test point circuit inserted for the purpose of improving the observability and having an effect of improving the efficiency of the clock sequential test. The observation SFF 20 is inserted into the DUT 2 that outputs a calculation result in accordance with the test signal to be scanned in. The observation SFF 20 has an XOR gate 21, MUX 22, FF 23, a data input terminal DATA, a scan-in terminal SIN, a control input terminal SMC, a clock terminal CLK, and a data output terminal Q. That is, the observation SFF 20 has the same input / output configuration as the SFF 10.

  The output of the observation SFF 20 is connected to the scan-in terminal SIN of the subsequent observation SFF 20, and the scan chain 6A is configured. The observation SFF 20 can switch between a scan shift operation and a capture operation.

  The observation SFF 20 takes in the calculation result from the DUT 2 at each of a plurality of capture clocks in one capture operation period. For example, a first capture clock applied during one capture operation period is a first capture clock, and a capture clock subsequent to the first capture clock is a second capture clock. In addition, the calculation result from the DUT 2 captured by the first capture clock is set as the first calculation result. A period in which one capture clock pulse operation is performed in one capture operation period is defined as a capture cycle.

  Note that the first capture clock may be applied after the capture clock is not applied first during one capture operation period. The second capture clock only needs to be applied after the first capture clock in one capture operation period.

  The data input terminal DATA receives the calculation result from the DUT 2 during the capture operation period. A test signal is input to the scan-in terminal SIN during the scan shift operation period, and a first calculation result captured by the observation SFF 20 in the previous stage of the scan chain with the first capture clock is input during the capture operation period.

  The XOR gate 21 receives a signal input from the scan-in terminal SIN and a signal input from the data input terminal DATA. Further, the XOR gate 21 calculates the calculation result from the DUT 2 input from the data input terminal DATA and the first calculation result captured by the observation SFF 20 in the previous stage of the scan chain input from the scan-in terminal SIN with the first capture clock. And the exclusive OR.

  The MUX 22 receives a signal input from the scan-in terminal SIN and a signal output from the XOR gate 21. The MUX 22 switches between a scan shift operation and a capture operation according to a scan enable signal input from the control input terminal SMC. In the example shown in FIG. 6, the MUX 22 performs a scan shift operation when the scan enable signal is high (1), and the input from the scan-in terminal SIN becomes valid. The MUX 22 performs a capture operation when the scan enable signal is low (0), and the output from the XOR gate 21 is valid.

  The FF 23 takes in the value output from the MUX 22 according to the clock signal (clock 2) input from the clock terminal CLK, and outputs the value from the data output terminal Q to the scan-in terminal SIN of the observation SFF 20 at the subsequent stage. During the scan shift operation period, the FF 23 takes in a test signal. Further, during the capture operation period, the FF 23 takes in the exclusive OR output from the MUX 22 with the second capture clock following the first capture clock. That is, the first calculation result captured by the observation SFF 20 in the previous stage of the scan chain 6A with the first capture clock is transmitted to the observation SFF 20 in the subsequent stage with the second capture clock after the first capture clock.

  If the SFF 10 is used instead of the observation SFF 20 in FIG. 6, the operation result that has reached the data input terminal DATA of the observation SFF 20 by the first capture clock in the clock sequential test is propagated by the next second capture clock. It disappears without a tip.

  On the other hand, in the semiconductor device 1A according to the first embodiment, the calculation result that has reached the observation SFF 20 with the first capture clock in one capture operation period is the subsequent stage on the scan chain 6A with the next second capture clock. To the observation SFF 20 via the XOR gate 21. As described above, in the semiconductor device 1A, it is possible to increase the probability that the calculation result that has reached the observation SFF 20 can be accumulated in the observation SFF 20 in the subsequent stage of the scan chain 6A without being lost in the next capture cycle.

  Further, the observation SFF 20 stores the calculation results from the DUT 2 via the XOR gate 21 from the data input terminal DATA of the observation SFF 20 in each capture cycle, together with the accumulation of the calculation results that have reached the previous observation SFF 20. it can. For this reason, when a plurality of capture clocks are applied in one capture operation period, the number of detectable failures increases. This makes it possible to reduce the number of inserted TPs necessary to achieve the target failure detection rate. Therefore, an increase in area overhead can be suppressed.

  In addition, by executing the clock sequential test in the semiconductor device 1A of FIG. 6, many failures can be detected in one capture operation period, and as a result, the test time can be reduced. In the scan test, since the scan shift operation time occupies most of the test time, increasing the number of capture clocks in the capture operation period has little effect on the test time.

  Here, the effect of reducing the test time will be described with reference to FIG. FIG. 7 is a diagram illustrating the failure detection rate with respect to the test time. In FIG. 7, the horizontal axis indicates the test time, and the vertical axis indicates the failure detection rate. In FIG. 7, the solid line indicates the result of the semiconductor device 1A using the observation SFF 20 according to the embodiment, and the broken line indicates the result of the semiconductor device in the case where the SFF 10 is configured instead of the observation SFF 20 of FIG. Is shown.

  In the example shown in FIG. 7, a clock sequential test is applied in which 10 capture clocks are applied in one capture operation period. As shown in FIG. 7, compared to the case where the SFF 10 is used, the use of the observation SFF 20 makes it possible to reduce the test time required to reach the target failure detection rate to half or less.

  As described above, according to the embodiment, the efficiency of the clock sequential test can be improved with a low area OH by the configuration of the scan chain by the observation SFF 20 without adding a special test circuit.

  Note that the semiconductor device 1A illustrated in FIG. 6 can execute LBIST and is mounted with PRPG3 and MISR4, but is not limited to this example. The clock sequential test exhibits a high effect of reducing the number of inserted TPs or reducing the LBIST execution time particularly in LBIST, but also has a certain effect in compressed scanning.

  A compressed scan is an example of design for testability (DFT) that reduces the amount of test data. In the compressed scan, the number of SFFs per scan chain is reduced by constructing more scan chains inside than the number of external terminals. Then, the value supplied from the external input terminal is expanded to the number of internal scan chains via the decompressor, and a test pattern is applied to each scan FF. The output from the scan chain is compressed by a compressor and observed at an external output terminal.

  In the compression scan, scan FF setting values (care bits) necessary for failure detection can be supplied with a small number of shift cycles, and each scan FF can be observed with a small number of shift cycles. For this reason, it is possible to increase the number of faults detected per bit of the external input / output terminal and reduce the amount of test data. The observation SFF 20 according to the embodiment can also be applied to a semiconductor device capable of executing a compression scan test.

  In a semiconductor device capable of executing a compression scan, an expander and a compressor that can be controlled and observed from the outside are connected instead of PRPG3 and MISR4 in FIG. Even in a semiconductor device capable of executing a compression scan, the efficiency of the clock sequential test can be improved by adopting a configuration similar to the configuration shown in FIG.

  In the example shown in FIG. 6, the clock signal (clock 2) supplied to the scan chain 6A is different from the clock signal (clock 1) supplied to other scan chains, but they may be the same. That is, the scan chain configured by the SFF 10 and the scan chain configured by the observation SFF 20 may be different clock domains or the same clock domain.

  FIG. 8 shows another example of the observation SFF 20. FIG. 8 is a diagram showing a configuration of another test point circuit 30 according to the first embodiment. The observation SFF 30 is used instead of the observation SFF 20 of the semiconductor device 1A of FIG. As shown in FIG. 8, the observation SFF 30 has a NOR gate 31, an XOR gate 32, an FF 33, a data input terminal DATA, a scan-in terminal SIN, a control input terminal SMC, a clock terminal CLK, and a data output terminal Q. .

  Similar to the scan chain 6A of FIG. 6, a plurality of observation SFFs 30 constitute one scan chain. In addition, at least one of the plurality of scan chains in the semiconductor device 1A is configured by only the observation SFF 30.

  Similar to the observation SFF 20, the observation SFF 30 captures the calculation result from the DUT 2 at each of the plurality of capture clocks in one capture operation period. An operation result from the DUT 2 is input to the data input terminal DATA during the capture operation period. A test signal is input to the scan-in terminal SIN during the scan shift operation period, and a first calculation result captured by the observation SFF 20 in the previous stage of the scan chain with the first capture clock is input during the capture operation period.

  A scan enable signal that is a control signal for switching between a scan shift operation and a capture operation is input to the control input terminal SMC. In the capture operation period, the NOR gate 31 receives the scan enable signal input from the control input terminal SMC and the signal input from the data input terminal DATA, and outputs a negative logical sum. The XOR gate 32 receives the first operation result input to the scan-in terminal SIN and the negative logical sum from the NOR gate 31, and outputs an exclusive logical sum.

  The FF 33 takes in the value output from the XOR gate 32 according to the clock signal input from the clock terminal CLK, and outputs it from the data output terminal Q to the scan-in terminal SIN of the observation SFF 20 in the subsequent stage. During the capture operation period, the FF 33 takes in the exclusive OR output from the XOR gate 32 at the second capture clock following the first capture clock.

  In the scan shift operation period (scan enable signal = 1), the value of the data input terminal DATA is cut off, and the test signal input from the scan-in terminal SIN is taken into the FF 33. In the capture operation period (scan enable signal = 0), the value of the data input terminal DATA is inverted and passed. The XOR gate 32 receives the inverted value of the data input terminal DATA and the value of the scan-in terminal SIN. The FF 33 takes in the output value of the XOR gate 32 according to the clock terminal CLK. The FF 33 of the observation SFF 30 has the same function as the FF 23 of the observation SFF 20 except that the value to be captured is inverted.

  When the observation SFF 30 is used, the inverted value of the value input from the data input terminal DATA is taken into the FF 33 via the XOR gate 32 during the capture operation period. Even when the inverted value of the input of the data input terminal DATA is captured by the observation SFF 30, there is no influence on the scan test operation and the normal user operation.

  In the clock sequential test, the first calculation result captured by the observation SFF 20 in the previous stage of the scan chain 6A with the first capture clock is transmitted to the observation SFF 20 in the subsequent stage with the second capture clock after the first capture clock. As a result, it is possible to improve the efficiency of the clock sequential test with a low area OH. In addition, the configuration of the observation SFF 30 is smaller in circuit area and delay than the configuration of the observation SFF 20. For this reason, by using the observation SFF 30 as the observation test point circuit, the area OH can be further suppressed, and a decrease in the operation speed can be suppressed.

Embodiment 2. FIG.
A semiconductor device in which the test point circuit according to the second embodiment is inserted will be described with reference to FIG. FIG. 9 is a diagram showing a configuration of the semiconductor device 1B according to the second embodiment. As illustrated in FIG. 9, the semiconductor device 1 </ b> B includes a DUT 2, a PRPG 3, a MISR 4, an LBIST controller 5, an SFF 10, an observation SFF 30, and an observation SFF 40. The observation SFF 30 and the observation SFF 40 are observation test point circuits that are inserted for the purpose of improving the observability and have an effect of improving the efficiency of the clock sequential test. In FIG. 9, the observation SFF 30 is indicated as obsSFF, and the observation SFF 40 is indicated as obsSFF2.

  In the semiconductor device 1B, at least one of the plurality of scan chains is composed of an observation SFF 30 and an observation SFF 40. In the example shown in FIG. 6, one scan chain is composed of the observation SFF 30 and the observation SFF 40, and the remaining scan chain is composed of the SFF 10. In FIG. 9, the scan chain constituted by the observation SFF 30 and the observation SFF 40 is indicated as a scan chain 6B.

  In the scan chain 6B, the observation SFF 40 is connected to the front stage, and four observation SFFs 30 are serially connected to the rear stage of the observation SFF 40. As the observation SFF 30, the one shown in FIG. 8 is used. Although the observation SFF 30 is used in the example shown in FIG. 9, the observation SFF 20 shown in FIG. 6 may be used instead of the observation SFF 30. That is, in the scan chain 6B, the observation SFF 40 and the four observation SFFs 20 may be serially connected. The configurations other than the observation SFF 30 and the observation SFF 40 are the same as those described with reference to FIG.

  The output of the observation SFF 40 is connected to the scan-in terminal SIN of the observation SFF 30. Further, the output of the observation SFF 30 is connected to the scan-in terminal SIN terminal of the subsequent observation SFF 30 to constitute the scan chain 6B. The output of the last observation SFF 30 is connected to the data input terminal DATA 2 of the observation SFF 40. Both the observation SFF 40 and the observation SFF 30 can switch between the scan shift operation and the capture operation. Similar to the observation SFF 30, the observation SFF 40 can capture the calculation results from the DUT 2 at each of a plurality of capture clocks in one capture operation period.

  In the semiconductor device 1B according to the second embodiment, the failure propagated to the last observation SFF 30 in the clock sequential test can be held on the scan chain 6B. As shown in FIG. 9, the observation SFF 40 has an XOR gate 41, a MUX 42, an FF 43, a data input terminal DATA, a data input terminal DATA2, a scan-in terminal SIN, a control input terminal SMC, a clock terminal CLK, and a data output terminal Q. doing.

  A test signal is input to the scan-in terminal SIN during the scan shift operation period. The data input terminal DATA receives the calculation result from the DUT 2 during the capture operation period. The first calculation result captured by the last observation SFF 30 with the first capture clock during the capture operation period is input to the data input terminal DATA2. That is, the observation SFF 40 has two systems of data input terminals.

  The XOR gate 41 receives a signal input from the data input terminal DATA and a signal input from the data input terminal DATA2. The XOR gate 41 includes the calculation result from the DUT 2 input from the data input terminal DATA, the first calculation result captured by the observation SFF 30 in the last stage of the scan chain input from the data input terminal DATA 2 with the first capture clock, and The exclusive OR of is output.

  The MUX 42 receives a signal input from the scan-in terminal SIN and a signal output from the XOR gate 41. The MUX 42 switches between the scan shift operation and the capture operation in accordance with the scan enable signal input from the control input terminal SMC. In the example shown in FIG. 9, the MUX 42 performs a scan shift operation when the scan enable signal is high (1), and the input from the scan-in terminal SIN becomes valid. The MUX 42 performs a capture operation when the scan enable signal is low (0), and the output from the XOR gate 41 is valid.

  The FF 43 takes in the value output from the MUX 42 in response to the clock signal (clock 2) input from the clock terminal CLK, and outputs it from the data output terminal Q to the scan-in terminal SIN of the observation SFF 30 in the subsequent stage.

  During the scan shift operation period (scan enable signal = 1), the FF 43 takes in a test signal input from the scan-in terminal SIN. Also, during the capture operation period (scan enable signal = 0), the FF 43 takes in the exclusive OR of the two data input terminals (DATA, DATA2) with the second capture clock following the first capture clock. That is, the first calculation result captured by the last observation SFF 30 of the scan chain 6B with the first capture clock is propagated to the foremost observation SFF 20 with the second capture clock after the first capture clock.

  As described above, in the semiconductor device 1B according to the second embodiment, even when a plurality of capture clocks are applied in one capture operation period in the clock sequential test, the last observation SFF 30 of the scan chain 6B is used with a certain capture clock. The failure taken in is propagated to the observation SFF 40 in the forefront stage with the next capture clock and does not disappear.

  Due to the circuit configuration, in the clock sequential test, the MISR 4 may not be used during the capture operation period or may not be observed by an external tester via a compressor. In such a case, the calculation result fetched by the last observation SFF 30 disappears without a propagation destination when the next capture clock is output.

  As in the second embodiment, when the circuit configuration shown in FIG. 9 is used, the calculation result captured in the last-stage observation SFF 30 can be propagated to the first-stage observation SFF 40 with the capture clock of the next capture cycle. Disappearance can be prevented.

  In the scan chain 6B, each observation SFF 30 connected to the subsequent stage of the observation SFF 40 is the first capture clock captured by the previous observation SFF 40 or the observation SFF 30 using the first capture clock, as described in the first embodiment. One calculation result is captured by the second capture clock. As a result, the number of failures that can be detected by one capture operation of the clock sequential test can be increased as compared with the first embodiment. As a result, it is possible to reduce the number of inserted TPs necessary for achieving the target failure detection rate or reduce the LBIST execution time.

Embodiment 3 FIG.
A semiconductor device in which the test point circuit according to the third embodiment is inserted will be described with reference to FIG. FIG. 10 is a diagram showing a configuration of a semiconductor device 1C according to the third embodiment. As shown in FIG. 10, the semiconductor device 1C includes a DUT 2, a PRPG 3, a MISR 4C, an LBIST controller 5, an SFF 10, and an observation SFF 30. In the semiconductor device 1C, the fault propagated to the last observation SFF 30 in the clock sequential test can be held by the MISR 4C.

  In the semiconductor device 1 </ b> C, at least one scan chain among the plurality of scan chains is configured only by the observation SFF 30. In the example shown in FIG. 6, one scan chain is configured by only the observation SFF 30, and the remaining scan chains are configured by the SFF 10. In FIG. 10, a scan chain composed of only the observation SFF 30 is indicated as a scan chain 6C.

  In the scan chain 6C, five observation SFFs 30 are serially connected. As the observation SFF 30, the one shown in FIG. 8 is used. Although the observation SFF 30 is used in the example shown in FIG. 9, the observation SFF 20 shown in FIG. 6 may be used instead of the observation SFF 30.

  During the capture operation period (scan enable signal = 0), the first calculation result captured by the observation SFF 30 in the last stage of the scan chain 6C with the first capture clock is the MISR4C with the second capture clock after the first capture clock. Is propagated to. In the example shown in FIG. 10, a clock signal (clock 2) is input to MISR4. The MISR 4C captures the value output from the last observation SFF 30 in synchronization with the clock signal (clock 2).

  The MISR 4C can compress unload data from a plurality of scan chains after the capture operation to generate a signature, and can capture the value of the last observation SFF 30 during the capture operation period to perform the compression operation. That is, the MISR 4C can capture the output value of the observation SFF 30 at the final stage for each capture cycle not only during the shift period but also when a plurality of capture clocks are applied in the clock sequential test.

  In this way, in each capture cycle, the fault propagation that reaches the last observation SFF 30 can be captured by the MISR 4C, and can be observed without losing the fault. As a result, the number of faults that can be detected during one capture operation period of the clock sequential test can be increased, and the number of inserted TPs necessary for achieving the target fault detection rate or the LBIST execution time can be reduced. It becomes possible.

Embodiment 4 FIG.
A test point circuit according to the fourth embodiment will be described with reference to FIG. FIG. 11 is a diagram illustrating a configuration of the observation SFF 50 according to the fourth embodiment. As shown in FIG. 11, the observation SFF 50 includes an XOR gate 51, MUX 52, FF 53, a data input terminal DATA, a scan-in terminal SIN, a control input terminal SMC, a clock terminal CLK, and a data output terminal Q.

  The observation SFF 50 is an observation test point circuit inserted for the purpose of improving the observability and having an effect of improving the efficiency of the clock sequential test. The observation SFF 50 is an SFF cell having a self-loop structure of the XOR gate 51. The observation SFF 50 has a function of holding a failure that has reached the data input terminal DATA in its own FF 53 when a plurality of capture clocks are applied in the clock sequential test.

  The XOR gate 51 receives the calculation result of the DUT 2 input from the data input terminal DATA and the value output from the FF 53. The exclusive OR of the XOR gate 51 is input to the MUX 52. Further, the test signal input from the scan-in terminal SIN is input to the MUX 52. The MUX 52 outputs either the exclusive OR or the test signal to the FF 53 according to the scan enable signal input from the control input terminal SMC.

  In the scan shift operation period (scan enable signal = 1), the value of the data input terminal DATA is cut off, and the test signal input from the scan-in terminal SIN is taken into the FF 53. In the capture operation period (scan enable signal = 0), the exclusive OR of the value of the data input terminal DATA and the value output from the FF 53 is captured by the FF 53.

  The FF 53 captures the first calculation result input from the data input terminal DATA with the first capture clock in one capture operation period. Then, at the second capture clock following the first capture clock, the FF 53 takes in the exclusive OR of the value input from the data input terminal DATA and the first calculation result.

  As described above, there is a possibility that a failure taken into the FF 53 of the observation SFF 50 in a certain capture cycle is taken into the FF 53 again via the self-loop XOR gate 51 in the next capture cycle and remains without disappearing. . As a result, the number of faults that can be detected during one capture operation period of the clock sequential test can be increased. In the above-described embodiment, it is necessary to construct a scan chain composed only of the observation test point circuit. However, the observation SFF 50 can improve the efficiency of the clock sequential test without depending on the configuration of the scan chain. It becomes possible.

  A design apparatus 100 according to an embodiment will be described with reference to FIGS. FIG. 12 is a diagram illustrating a configuration of a design apparatus for designing the semiconductor device according to the embodiment. 13 and 14 are diagrams showing a design flow of the semiconductor device according to the embodiment. The design apparatus 100 designs a semiconductor device with high efficiency of the above-described clock sequential test.

  The design device 100 includes an arithmetic processing device 110, a storage device 120, a control input device 130, and a display output device 131. The arithmetic processing unit 110 is a device that can load a program necessary for designing a semiconductor device and execute each functional process necessary for the design, and includes a CPU, a memory, and the like. The arithmetic processing unit 110 has a test point insertion program 111 and a scanning program 112.

  The storage device 120 includes a net list 121, a function library 122, a test constraint DB 123, a test point inserted net list 124, a test point insertion information DB 125, and a scanned net list 126. The storage device 120 refers to a storage medium such as an HDD disk or memory that stores library and netlist information. The design apparatus 100 uses the program of the arithmetic processing unit 110 and refers to the netlist or library of the storage device 120 to generate a semiconductor device in which the observation test point circuit described in the first to third embodiments is inserted. .

  The control input device 130 is a general term for devices for the user to operate the arithmetic processing device 110 and the storage device 120, and examples thereof include a keyboard and a mouse. The display output device 131 is used by the user to check the operations of the arithmetic processing device 110 and the storage device 120, and includes a display and the like.

  In addition to the cell information of the observation test point circuit described above, the netlist 121 stores cell information such as AND gates, OR gates, XOR gates, connection information between terminals, and the like. The function library stores cell functions and the like. The test constraint DB 123 stores information necessary for circuit operation during testing. The information stored in the test constraint DB 123 includes information such as fixing the external output terminal to 0, for example.

  The arithmetic processing unit 110 refers to the net list 121, the function library 122, and the test constraint DB 123, and executes the test point insertion program 111, thereby obtaining the test point inserted net list 124 into which the observation test point circuit is inserted. Generate. The test point insertion program 111 has a function of inserting the observation SFF 20, the observation SFF 30, or the observation SFF 40 as an observation test point circuit in addition to a general test point insertion function.

  Further, the arithmetic processing unit 110 refers to the function library 122, the test constraint DB 123, the test point inserted net list 124, and the test point insertion information DB 125, and executes the scanning program 112, thereby improving the efficiency of the clock sequential test. Producing high semiconductor devices. The test point insertion information DB 125 stores test point insertion information including connection information of the inserted test point circuit.

  The scanning program 112 has a function of constructing at least one scan chain with only the inserted observation SFF in addition to a general scan chain construction function. The scanning program 112 constructs at least one scan chain using only the observation SFF, based on the test point insertion information, using the net list after the test point circuit is inserted. The test point insertion information can be output from the test point insertion program 111 or can be generated from the cell name of the instance of the test point inserted netlist.

  The scan program 112 can also execute processing for connecting the SFF or obsSFF in the forefront stage of each scan chain to the PRPG 3 and processing for connecting the SFF or obsSFF in the last stage of each scan chain to the MISR 4. The arithmetic processing unit 110 can generate the scanned netlist 126 of the semiconductor device capable of executing LBIST with improved efficiency of the clock sequential test by executing the scanning program 112.

  Here, a design flow of the semiconductor device will be described with reference to FIGS. First, a process for generating a test point inserted netlist will be described with reference to FIG. FIG. 13 is a diagram showing an example of a test point insertion netlist generation algorithm.

  As shown in FIG. 13, first, predetermined information is input to the net list 121, the function library 122, and the test constraint DB 123 (step S11). Thereafter, by analyzing the input information, circuit information and test constraint information are identified (step S12). Here, an SFF in the circuit, a user FF having a shift register structure, test constraint information, and the like are acquired. In the test constraint information, a target number (target insertion number) of test point circuits to be inserted is defined.

  Based on the information of the identified SFF, controllability and observability analysis of the logic circuit based on random numbers in a general TPI algorithm is performed (step S13). Based on the analysis result of step S13, the insertion point of the control test point circuit / observation test point circuit is selected (step S14).

  After that, the insertion point of the test point circuit is selected until the insertion point reaches the target insertion number defined as the test constraint information (step S15). If the threshold value for the number of insertions has not been reached (NO in step S15), the processing from S13 to S15 is repeated. When the insertion location reaches the target insertion number (YES in step S15), the observation SFF is inserted into the selected insertion location. Note that the observation SFF 20, the observation SFF 30, or the observation SFF 40 is inserted into the observation point (step S16). Thereafter, the test point inserted netlist is output (step S17), and the test point inserted netlist generation process ends.

  Next, the scan netlist generation process will be described with reference to FIG. FIG. 14 is a diagram illustrating an example of a scan netlist generation algorithm. As shown in FIG. 14, first, predetermined information is input to the net list 121, the function library 122, the test constraint DB 123, and the test point insertion information DB 125 (step S21). Thereafter, by analyzing the input information, circuit information and test constraint information are identified (step S22). Then, from the identified circuit information, an SFF in the circuit and an observation SFF corresponding to the clock sequential test are identified (step S23).

  Thereafter, at least one scan chain is constructed with the identified observation SFF (step S24). The arithmetic processing unit 110 executes processing for serially connecting only the observation SFF 20 or the observation SFF 30 in the scan chain including the observation SFF as in the first embodiment. Alternatively, the arithmetic processing unit 110 connects the observation SFF 40 to the front stage as in the second embodiment, and connects the observation SFF 20 or the observation SFF 30 to the subsequent stage. In this case, the output of the last observation SFF is connected to the data input terminal DATA2 of the first observation SFF 40. In this way, by configuring the scan chain with the observation SFFs, it is possible to increase the number of faults that can be detected during one capture operation period of the clock sequential test.

  Then, apart from the scan chain composed of the observation SFFs, a scan chain is constructed with the SFFs (step S25). Thereby, the scanned netlist is output (step S26), and the scanned netlist generation process ends. By using the scanned netlist generated in this way, the number of faults that can be detected during one capture operation period of the clock sequential test is increased, and the number of inserted TPs necessary to achieve the target fault detection rate is reduced. Alternatively, a circuit capable of reducing the test execution time can be designed.

  As a process after the construction of the scan chain of FIG. 14, the arithmetic processing unit 110 executes LBIST by executing a general compression circuit addition program, such as PRPG3, MISR4, LBIST controller 5 and the like LBIST. Add circuit. When designing the semiconductor device according to the third embodiment, the output from the observation SFF is taken into the output side of the observation SFF in the last stage of the scan chain during one capture operation period of the clock sequential test. Insert possible MISR4. Thereby, MISR4 can capture the calculation result captured by the observation SFF provided in the last stage of the scan chain with the first capture clock in the next second capture clock in one capture operation. When performing the compression scan test, the arithmetic processing unit 110 adds a decompressor, a compressor, and the like for executing the compression scan.

  Then, the arithmetic processing unit 110 generates a test pattern for executing a clock sequential test by executing a general test pattern generation program on the circuit generated by the compression circuit addition program. As a result, as shown in FIG. 7, the target detection rate can be achieved in a short test time.

  It is also possible to design a logic circuit having high clock sequential test efficiency using the observation SFF 50 by using the design apparatus 100 shown in FIG. The design apparatus 100 executes the test point insertion program 111 to insert the observation SFF 50 at the observation point. Then, the design apparatus 100 does not construct a scan chain by the observation SFF 50, but constructs a scan chain by the SFF 10. That is, the process of step S25 is executed without performing the process of step S24 in FIG. As described above, by using the observation SFF 50, it is not necessary to have a function of a program for constructing a scan chain including only the observation SFF 50.

  Further, the above-described program can be stored using various types of non-transitory computer readable media and supplied to a computer. Non-transitory computer readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic recording media (for example, flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (for example, magneto-optical disks), CD-ROM (Read Only Memory) CD-R, CD -R / W, semiconductor memory (for example, mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM), flash ROM, RAM (Random Access Memory)). The program may also be supplied to the computer by various types of transitory computer readable media. Examples of transitory computer readable media include electrical signals, optical signals, and electromagnetic waves. The temporary computer-readable medium can supply the program to the computer via a wired communication path such as an electric wire and an optical fiber, or a wireless communication path.

  As described above, according to the embodiment, the data input and the scan input are configured by inputting the XOR output of the scan input and the data input to the flip-flop in one capture operation period of the clock sequential test. It is possible to capture the fault propagation that has reached As a result, when a plurality of capture clocks are applied in the clock sequential test, the failure propagation reaching the flip-flop in each capture cycle can be held and compressed without being lost. Thereby, it is possible to reduce the test time for reaching the target failure detection rate.

  The test point circuit according to the embodiment can also be expressed as follows. The test point circuit described below corresponds to FIG.

(Appendix 1)
A test point circuit inserted in a combinational circuit that outputs a calculation result in response to a test signal scanned in;
A flip-flop that captures a first operation result from the combinational circuit with a first capture clock in one capture operation period of a clock sequential test;
An XOR gate that outputs an exclusive OR of the first operation result and the second operation result from the combinational circuit to the flip-flop;
Including
The flip-flop captures the exclusive OR with the second capture clock following the first capture clock;
Test point circuit.

(Appendix 2)
A semiconductor device design apparatus including an arithmetic processing unit capable of executing predetermined processing according to a preset program,
The semiconductor device includes:
A scan flip-flop constituting the scan chain;
The test point circuit according to appendix 1,
Including
The arithmetic processing unit includes:
Performing an analysis process for analyzing a probability that an operation result from the combinational circuit becomes a predetermined logic state;
Based on the result of the analysis process, the insertion position of the test point circuit is selected,
Insert the test point circuit at the selected insertion position,
When constructing a scan chain by the scan flip-flop, do not execute the construction of the scan chain by the test point circuit,
Design equipment.

  In the above-described embodiment, the example in which the test point circuit is inserted (TPI) and the clock sequential test (multi-cycle test) is performed in order to increase the failure detection rate in the semiconductor device capable of executing LBIST has been described.

  In the following embodiments, an example in which a clock sequential test is performed to reduce test execution time without inserting a test point circuit in a semiconductor device capable of executing LBIST will be described.

  As described above, the clock sequential test is a multi-cycle test in which the operation result from the combinational circuit is captured with a plurality of capture clocks in one capture operation period. The clock sequential test is effective in reducing the LBIST execution time even when no test point circuit is inserted.

  Also in the following embodiments, the schematic configuration of a semiconductor device capable of executing LBIST is the same as the configuration of the semiconductor device shown in FIG. An example of the operation waveform of the clock sequential test using a plurality of clocks is as described in FIG.

  The SFF 10 used in FIG. 1 does not assume a clock sequential test. In order to further improve the effect of the clock sequential test, the present inventors devised a sequential test scan flip-flop (hereinafter referred to as “seqSFF”) that is used in place of the SFF 10 in FIG. .

  The sequential test scan flip-flop according to the embodiment constitutes a scan chain capable of executing an LSI scan test, and performs a clock sequential test. The seqSFF according to the embodiment has a logical structure capable of reducing the test execution time and increasing the failure detection rate.

  Specifically, the seqSFF according to the embodiment includes a test enable input terminal to which a test enable signal is input. seqSFF is a second capture clock after the first capture clock in the one capture operation period of the clock sequential test according to the test enable signal, and is connected to the previous stage of the sequential test scan flip-flop in the scan chain or the scan. The first cell in the last stage of the chain captures the first calculation result from the combinational circuit captured by the first capture clock.

  The semiconductor device using the seqSFF of the embodiment can be applied to a product in which POST is mounted, for example. In addition, this semiconductor device can be applied to a product that is intended to reduce the test cost when LBIST is applied in a mass production test process, a design device (EDA tool) for mounting LBIST, or the like.

Embodiment 5. FIG.
A sequential test scan flip-flop (seqSFF) used in a semiconductor device that performs a clock sequential test will be described with reference to FIGS. FIG. 15 is a diagram illustrating a configuration of a semiconductor device in which the seqSFF according to the fifth embodiment is inserted. The semiconductor device 1D of FIG. 15 has a minimum configuration capable of holding the failure propagation that has reached the SFF 10 when a plurality of clocks are applied in the clock sequential test without being lost even in the next capture cycle. In FIG. 15, only the minimum configuration of the semiconductor device 1D for illustrating the seqSFF 60 is illustrated.

  As shown in FIG. 15, the semiconductor device 1D includes a DUT 2, an SFF 10, and a seq SFF 60. The seq SFF 60 is serially connected to the subsequent stage of the SFF 10 to construct one scan chain. The DUT 2 and the SFF 10 are the same as those described in FIG.

  FIG. 16 is a diagram illustrating a configuration of the seqSFF 60 according to the fifth embodiment. As shown in FIG. 16, the seqSFF 60 includes a NOR gate 61, a NAND gate 62, an XOR gate 63, an FF 64, a data input terminal DATA, a control input terminal SMC, a scan-in terminal SIN, a test enable input terminal SEQ_TEST_EN, a clock terminal CLK, data An output terminal Q is provided. The input / output configuration of the seqSFF 60 is the same as that of the SFF 10 except for the test enable input terminal SEQ_TEST_EN. That is, the seqSFF 60 has a test enable input terminal SEQ_TEST_EN in addition to the input / output configuration of the SFF 10.

  The output of SFF10 is connected to the scan-in terminal SIN of seqSFF60. The seqSFF 60 can switch between a normal user operation and a scan test operation. Furthermore, the seqSFF 60 can switch between a scan shift operation and a capture operation during the scan test operation period. The seqSFF 60 takes in the calculation result from the DUT 2 at each of a plurality of capture clocks in one capture operation period.

  For example, a first capture clock applied during one capture operation period is a first capture clock, and a capture clock subsequent to the first capture clock is a second capture clock. In addition, the calculation result from the DUT 2 captured by the first capture clock is set as the first calculation result. A period in which one capture clock pulse operation is performed in one capture operation period is defined as a capture cycle.

  Note that the first capture clock may be applied after the capture clock is not applied first during one capture operation period. The second capture clock only needs to be applied after the first capture clock in one capture operation period.

  The data input terminal DATA receives the calculation result from the DUT 2 during the capture operation period. A test signal is input to the scan-in terminal SIN during the scan shift operation period, and a first calculation result captured by the SFF 10 in the previous stage of the scan chain with the first capture clock is input during the capture operation period.

  A test enable signal (seq_test_enable) is input to the test enable input terminal SEQ_TEST_EN. The seqSFF 60 switches between a normal user operation and a scan test operation according to the test enable signal. For example, the user operation is performed when the test enable signal is low (0), and the scan test operation is performed when the test enable signal is high (1).

  A scan enable signal (scan_enable) is input to the control input terminal SMC. The seqSFF 60 switches between the scan shift operation and the capture operation according to the scan enable signal. For example, when the test enable signal is high (1), the scan shift operation is performed when the scan enable signal is high (1), and the capture operation is performed when the scan enable signal is low (0).

  The NOR gate 61 receives a scan enable signal (scan-enable) input from the control input terminal SMC and a signal input from the data input terminal DATA, and outputs a negative logical sum. The NAND gate 62 receives the first operation result input to the scan-in terminal SIN and the test enable signal, and outputs a negative logical product. The XOR gate 63 receives the negative logical sum from the NOR gate 61 and the negative logical product from the NAND gate 62, and outputs an exclusive logical sum.

  The FF 64 takes in the value output from the XOR gate 63 according to the clock signal (clock) input from the clock terminal CLK, and outputs it from the data output terminal Q. During the scan shift operation period, the FF 64 takes in a test signal. In the capture operation period, the FF 64 takes in the exclusive OR output from the XOR gate 63 at the second capture clock following the first capture clock. That is, the first calculation result captured by the first capture clock by the SFF 10 in the previous stage of the scan chain is propagated to the subsequent seqSFF 60 by the second capture clock after the first capture clock.

  Here, the operation of the semiconductor device 1D will be described. 17 and 18 are diagrams illustrating examples of operation waveforms of the semiconductor device 1D according to FIG. As shown in FIG. 17, during a user operation, the scan enable signal = 0 (constant LOW) and the test enable signal = 0 (constant LOW) are set. At this time, both SFF10 and seqSFF60 take in the value input from the data input terminal DATA.

  As shown in FIG. 18, during the scan test operation, the test enable signal is set to 1 (constant HIGH). During the scan test operation, the scan enable signal = 1 (HIGH) is set during the scan shift operation period. At this time, the SFF 10 and seq SFF 60 take in the value from the scan-in terminal SIN, and the scan shift operation is performed.

  During the scan test operation, the scan enable signal = 0 (LOW) is set during the capture operation period. At this time, the SFF 10 captures a value from the data input terminal DATA, and the seqSFF 60 captures an exclusive OR of the values from the data input terminal DATA and the scan-in terminal SIN. FIG. 19 shows a truth table of the sequential test scan flip-flop shown in FIG. The seqSFF 60 has a configuration that satisfies the functions shown in the truth table of FIG.

  Here, consider a case where two capture clocks are applied in the clock sequential test. Assume that the SFF 10 captures the influence of fault propagation in the first capture cycle. That is, the output value of the data output terminal Q of the SFF 10 after the first capture clock application is inverted between when it is normal and when a failure occurs.

  Since the seqSFF 60 captures the exclusive OR of the values from the data input terminal DATA and the scan-in terminal SIN in the second capture cycle, when the value of the data output terminal Q of the SFF 10 is inverted, the value captured by the seq SFF 60 is also inverted. To do. As described above, the failure captured by the SFF 10 in the first capture cycle is held in the seqSFF 60 in the second capture cycle.

  Consider a case where the SFF 10 is configured instead of the seq SFF 60 in FIG. In the clock sequential test, the calculation result that has reached the data input terminal DATA of the preceding SFF 10 by the first capture clock is lost without being propagated by the next second capture clock unless it reaches the subsequent SFF 10 via the DUT 2. End up. This erasure probability increases as the number of logic gate stages increases. In general logic, since there are a large number of logic gates, it is unlikely that a failure can be held by applying a capture clock multiple times.

  On the other hand, in the semiconductor device 1D according to the fifth embodiment, the calculation result that has reached the SFF 10 with the first capture clock in one capture operation period is transferred to the subsequent seq SFF 60 on the scan chain with the next second capture clock. Propagated. Thus, in the semiconductor device 1D, it is possible to increase the failure detection rate when a plurality of capture clocks are applied.

  In addition, by executing the clock sequential test in the semiconductor device 1D, it becomes possible to detect many failures in one capture operation period, and as a result, the test time can be reduced.

  The seqSFF 60 is not limited to the logical structure shown in FIG. The configuration of the seqSFF 60 is a schematic configuration of the sequential test scan flip-flop shown in FIG. 20, and may be any configuration as long as it satisfies the functions shown in the truth table shown in FIG.

又は否定排他的論理和

が取り込まれる。 That is, when the scan enable signal = 0 and the test enable signal = 0, the value of the data input terminal DATA is captured. When the scan enable signal = 0 and the test enable signal = 1, the values of the data input terminal DATA and the scan-in terminal SIN are exclusive ORed.

Or negative exclusive OR

Is captured.

が取り込まれる。 When the scan enable signal = 1, the value of the scan-in terminal SIN (SIN) or the value of the scan-in terminal SIN is negated regardless of the value of the test enable signal.

Is captured.

  Other logical circuit examples of the seqSFF 60 that satisfy the truth table of FIG. 21 are shown in FIGS. The truth tables of seqSFF 60A in FIG. 22, seq SFF 60B in FIG. 24, and seq SFF 60C in FIG. 23 are shown in FIGS.

  The seqSFF 60A illustrated in FIG. 22 includes a NOR gate 61, an XOR gate 63, an FF 64, and an OR gate 65. The NOR gate 61 receives a scan enable signal (scan-enable) input from the control input terminal SMC and a signal input from the data input terminal DATA, and outputs a negative logical sum.

  One input terminal of the OR gate 65 is negative logic. The OR gate 65 receives the value from the scan-in terminal SIN and the negative logic of the test enable signal, and outputs a logical sum. The XOR gate 63 receives the negative logical sum from the NOR gate 61 and the logical sum from the OR gate 65, and outputs an exclusive logical sum. The FF 64 takes in the value output from the XOR gate 63 and outputs it from the data output terminal Q.

  Note that the operation waveforms of the seqSFF 60A shown in FIG. 22 are the same as those shown in FIGS. That is, as shown in FIG. 17, during a user operation, the scan enable signal = 0 (constant LOW) and the test enable signal = 0 (constant LOW) are set. As shown in FIG. 18, the test enable signal = 1 (constant HIGH) is set during the scan test operation. During the scan test operation, the scan enable signal = 1 (HIGH) is set during the scan shift operation period.

  In this way, even in the configuration shown in FIG. 22, during the capture operation period, the first operation result captured by the SFF 10 in the previous stage of the scan chain with the first capture clock is the second capture after the first capture clock. It is propagated to the subsequent seqSFF 60 by the clock.

  The seqSFF 60B illustrated in FIG. 24 includes a NOR gate 61, a NAND gate 62, an XOR gate 63, an FF 64, and an OR gate 66. The NOR gate 61 receives a scan enable signal (scan-enable) input from the control input terminal SMC and a signal input from the data input terminal DATA, and outputs a negative logical sum.

  The OR gate 66 outputs a logical sum of the scan enable signal and the test enable signal. The NAND gate 62 receives the value from the scan-in terminal SIN and the logical sum from the OR gate 66, and outputs a negative logical product. The XOR gate 63 receives the negative logical sum from the NOR gate 61 and the negative logical product from the NAND gate 62, and outputs an exclusive logical sum. The FF 64 takes in the value output from the XOR gate 63 and outputs it from the data output terminal Q.

  The seqSFF 60C shown in FIG. 26 includes an XOR gate 67, MUX 68, MUX 69, and FF 64. The XOR gate 67 receives the value from the data input terminal DATA and the value from the scan-in terminal SIN, and outputs an exclusive OR. The MUX 68 receives the value from the data input terminal DATA and the exclusive OR from the XOR gate 67. The value from the data input terminal DATA is valid when the test enable signal is low (0), and the value from the XOR gate 67 is valid when the MUX 68 is high (1).

  The value from the MUX 68 is input to the MUX 69. Also, the MUX 69 receives a value from the scan-in terminal SIN. The value from the MUX 68 is valid when the scan enable signal is low (0), and the value from the scan-in terminal SIN is valid when the MUX 69 is high (1). The FF 64 takes in the value output from the MUX 69 and outputs it from the data output terminal Q.

  The operation waveforms of the semiconductor device into which the seq SFFs 60B and 60C shown in FIGS. 24 and 26 are inserted are shown in FIGS. As shown in FIG. 28, the scan enable signal = 0 (constant LOW) is set during user operation. At this time, the test enable signal may be 0/1 (don't care).

  As shown in FIG. 29, during the scan test operation, the scan enable signal = 0 (LOW) and the test enable signal = 1 (HIGH) are set during the capture operation period. During the scan test operation, the scan enable signal = 1 (HIGH) is set during the scan shift operation period. At this time, the test enable signal may be 0/1 (don't care).

  In this way, by having a structure that takes in an exclusive OR or a negative exclusive OR of the value of the scan-in terminal SIN and the value of the data input terminal DATA, failures that have reached the scan-in terminal SIN and the data input terminal DATA can be simultaneously performed Can be captured. As a result, when a capture clock is applied a plurality of times in the clock sequential test, it is possible to hold a fault that has reached the seqSFF 60 in each capture cycle. As a result, the number of faults that can be detected in one capture period increases, and the test time for reaching the target detection rate can be reduced.

Embodiment 6 FIG.
A semiconductor device in which the sequential test scan flip-flop (seqSFF) according to the sixth embodiment is inserted will be described with reference to FIG. FIG. 30 is a diagram illustrating a configuration of the semiconductor device 1E in which the seqSFF according to the sixth embodiment is inserted.

  As shown in FIG. 30, the semiconductor device 1E includes a DUT 2, a PRPG 3, a MISR 4, an LBIST controller 5, and a plurality of seq SFFs 60. The configuration other than the seqSFF 60 is the same as that described with reference to FIG.

  The semiconductor device 1E has one or more scan chains. In the example shown in FIG. 30, each scan chain is composed of only seqSFF60. In FIG. 30, one scan chain configured by the seqSFF 60 is indicated as a scan chain 6D. In the scan chain 6D, five seq SFFs 60 are serially connected.

  The seqSFF 60 has the same configuration as that shown in FIG. Instead of the seqSFF 60, it is also possible to use a seqSFF having another configuration that satisfies the function of the truth table shown in FIG.

  A scan enable signal is input to the control input terminal SMC of each seq SFF 60. A test enable signal is input to the test enable input terminal SEQ_TEST_EN of each seqSFF60. Note that the test enable input terminal SEQ_TEST_EN is not necessarily controlled by an external input terminal, and may be controlled from a test mode register or the like.

  During user operation, a test enable signal = 0 and a scan enable signal = 0 are given. A test enable signal = 0 and a scan enable signal = 0 are supplied to the control input terminal SMC and the test enable input terminal SEQ_TEST_EN of each seqSFF 60, respectively. As a result, the value input from the scan-in terminal SIN is blocked, and the seqSFF 60 takes in the value from the data input terminal DATA.

  During the scan test operation, the test enable signal = 1 is set. During the scan shift operation period, the scan enable signal = 1 is set. Each seq SFF 60 takes in a value from the scan-in terminal SIN to perform a scan shift operation. During the capture operation, the scan enable signal = 0 is set. Each seqSFF 60 takes in the exclusive OR of the value from the data input terminal DATA and the value from the scan-in terminal SIN.

  For this reason, when a plurality of capture clocks are applied by the clock sequential test, a failure that has reached the seqSFF 60 in a certain capture cycle is taken into the subsequent seqSFF 60 on the scan chain via the scan-in terminal SIN in the next capture cycle.

  For example, when the number of stages in the scan chain 6D is N, a failure captured in the head seqSFF 60 may be held in the seq SFF 60 on the scan chain 6D until N capture clocks are applied at the maximum. As a result, the number of faults that can be detected during the capture operation period in the clock sequential test can be increased.

  Here, the effect of reducing the test time will be described with reference to FIG. FIG. 31 is a diagram illustrating a failure detection rate with respect to a test time of the semiconductor device 1E according to the sixth embodiment. In FIG. 31, the horizontal axis represents the test time, and the vertical axis represents the failure detection rate. In FIG. 31, the solid line indicates the result of the semiconductor device 1E using the seq SFF 60 according to the embodiment, and the broken line indicates the result of the semiconductor device configured with the SFF 10 instead of the seq SFF 60 of FIG. .

  As shown in FIG. 31, in the semiconductor device 1E according to the sixth embodiment, by using the seq SFF 60, it is possible to achieve the target failure detection rate in a test time shorter than that when the SFF 10 is used.

Embodiment 7 FIG.
A semiconductor device in which the sequential test scan flip-flop (seqSFF) according to the seventh embodiment is inserted will be described with reference to FIG. FIG. 32 is a diagram illustrating a configuration of the semiconductor device 1F in which the seqSFF according to the seventh embodiment is inserted.

  In the semiconductor device 1F shown in FIG. 32, a part of SFF is replaced with seqSFF60 in a general LBIST configuration. Instead of the seqSFF 60, it is also possible to use a seqSFF having another configuration that satisfies the function of the truth table shown in FIG. In FIG. 32, “FF” indicates a flip-flop having no scan function such as scan-in and scan-out. Here, a flip-flop having no scan function is referred to as a normal flip-flop (hereinafter referred to as a normal FF).

  The semiconductor device 1F has one or more scan chains. In the example shown in FIG. 32, the shift register structure 7A in the user logic is incorporated in at least one scan chain 6E among the plurality of scan chains. In the shift register structure 7A, the head is replaced with seqSFF60, and two normal FFs are serially connected to the subsequent stage of seqSFF60. In the scan chain 6E, seqSFFs 60 are arranged at the front and rear stages of the shift register structure 7A, respectively.

  The data output terminal Q of the preceding seqSFF 60 is connected to the scan-in terminal SIN of the seqSFF 60 of the shift register structure 7A. The calculation result from the DUT 2 captured by the leading seqSFF 60 of the shift register structure 7A is directly taken into the subsequent normal FF. The data output terminal Q of the normal FF in the last stage of the shift register structure 7A is connected to the input to the DUT 2 and the scan-in terminal SIN of the next stage seqSFF 60 on the scan chain 6E.

  In the example shown in FIG. 32, a shift register structure 7B composed of one seqSFF, one normal FF, a shift register structure 7C composed of one seqSFF, and two normal FFs are configured in the user logic. The shift register structure 7B and the shift register structure 7C constitute one scan chain.

  In the shift register structure 7B, the normal FF is serially connected to the subsequent stage of the seqSFF 60. In the shift register structure 7C, two normal FFs are serially connected to the subsequent stage of the seqSFF 60. The data output terminal Q of the normal FF of the shift register structure 7B is connected to the input to the DUT 2 and the scan-in terminal SIN of the seqSFF 60 of the shift register structure 7C.

  Although not shown here, FFs other than the shift register structure are replaced with seqSFF60. The output of the seq SFF 60 or the shift register structure is connected to the scan-in terminal SIN of the seq SFF 60 connected to the subsequent stage, thereby forming a scan chain. Also in the shift register structures 7A to 7C and other shift register structures, the scan shift operation is performed as in the case where the scan chain is constructed by the SFF.

  As described in the sixth embodiment, also in the seventh embodiment, a scan enable signal is input to the control input terminal SMC of each seq SFF 60. A test enable signal is input to the test enable input terminal SEQ_TEST_EN of each seqSFF60.

  In the seventh embodiment, when a plurality of capture clocks are applied by the clock sequential test, a failure that has reached the first seqSFF 60 in the shift register structure in a certain capture cycle is not lost in the next capture cycle, and the subsequent stage of the shift register structure is lost. Propagates to normal FF. As a result, the efficiency of the clock sequential test can be improved.

  Further, in Embodiment 7, the shift register structure other than the top is incorporated into the scan chain with the normal FF as it is. For this reason, an increase in area can be suppressed as compared with a case where all are replaced with flip-flops having a scan function.

Embodiment 8 FIG.
A semiconductor device in which the sequential test scan flip-flop (seqSFF) according to the eighth embodiment is inserted will be described with reference to FIG. FIG. 33 is a diagram illustrating a configuration of a semiconductor device 1G in which the seqSFF according to the eighth embodiment is inserted.

  Some user FFs in the circuit do not contribute to improving the efficiency of the clock sequential test even if they are replaced with seqSFF60. Since the area of the seq SFF 60 is larger than that of the SFF, if all the user FFs are replaced with the seq SFF 60, the area increases.

  Therefore, the semiconductor device 1G according to the eighth embodiment has a structure in which the replacement target with the seqSFF 60 is limited to some user FFs. In FIG. 33, a flip-flop having no scan function is denoted as FF, and a flip-flop having a scan function is denoted as SFF.

  First, in Embodiment 8, when a plurality of capture clocks are applied in a clock sequential test, a user FF whose number of detected faults efficiently increases when faults reaching the data input terminal DATA are accumulated is selected.

  The selection of the user FF that contributes to improving the efficiency of the clock sequential test can be obtained by using a combination logic amount of input cones to the data input terminal DATA, a probability-based failure simulation, or the like. Then, only the selected user FF is replaced with seqSFF 60 to construct a scan chain.

  FIG. 33 shows an example of the semiconductor device 1G in which the replacement target with the seqSFF 60 is limited to some user FFs in this way. The semiconductor device 1G has one or more scan chains. In the example shown in FIG. 33, the shift register structure 7D in the user logic is incorporated in at least one scan chain 6F among the plurality of scan chains. The scan chain 6F does not include an SFF. The scan chain 6F includes two seqSFFs 60 and a shift register structure 7D that is arranged between the two seqSFFs 60 and has the seqSFF 60 at the head. The scan chain 6F has the same configuration as the scan chain 6E according to the seventh embodiment, and thus detailed description thereof is omitted.

  In FIG. 33, since the shift register structure 7D is included in the selected user FF, the shift register structure 7D is incorporated in the scan chain 6F. However, the present invention is not limited to this. All the selected user FFs may be replaced with seqSFF60, and the scan chain 6F may be configured with only seqSFF60.

  In addition, at least one scan chain 6G among the plurality of scan chains does not include the seqSFF 60. The scan chain 6G includes two SFFs, and a shift register 8 that is disposed between the two SFFs and that has an SFF at the head. The shift register 8 includes an SFF and two FFs. Although the scan chain 6G includes the shift register 8, there may be a scan chain that does not include the shift register.

  As described above, by limiting the replacement target to the seqSFF 60 to a part of the user FFs having a high effect of improving the efficiency of the clock sequential test, it is possible to suppress an increase in area and to shorten a test time. .

Embodiment 9 FIG.
A semiconductor device in which the sequential test scan flip-flop (seqSFF) according to the ninth embodiment is inserted will be described with reference to FIG. FIG. 34 is a diagram showing a configuration of the semiconductor device 1H in which the seqSFF according to the ninth embodiment is inserted. As illustrated in FIG. 9, the semiconductor device 1H includes a DUT 2, a PRPG 3, a MISR 4, an LBIST controller 5, a seq SFF 60, and a seq SFF 70. In FIG. 34, seqSFF60 is indicated as seqSFF, and seqSFF70 is indicated as seqSFF2.

  In the semiconductor device 1H, at least one scan chain 6H among the plurality of scan chains includes seqSFF60 and seqSFF70. In the example shown in FIG. 34, a seqSFF 70 is arranged at the head of the scan chain 6H, a shift register structure including a seqSFF 60 and two normal FFs is arranged at the subsequent stage, and the seq SFF 60 is connected at the subsequent stage.

  As the seqSFF 60, one having the configuration shown in FIG. 16 is used. In the example shown in FIG. 34, seqSFF60 is used, but seqSFF having another configuration satisfying the function of the truth table shown in FIG. 21 may be used instead of seqSFF60. Since the configuration other than the seqSFF 70 is the same as that described with reference to FIG. 33, a detailed description thereof will be omitted.

  In other scan chains, an SFF is arranged at the head, and an SFF, two normal FFs, and an SFF are sequentially connected to the subsequent stage. That is, the other scan chain includes a shift register. However, the present invention is not limited to this, and all the scan chains may include seqSFF60 and seqSFF70.

  In the semiconductor device 1H according to the ninth embodiment, the failure propagated to the last-stage seqSFF 60 in the clock sequential test can be held on the scan chain 6H. As shown in FIG. 34, the seqSFF 70 includes an AND gate 71, an XOR gate 72, a MUX 73, an FF 74, a data input terminal DATA, a data input terminal DATA2, a test enable input terminal SEQ_TEST_EN, a scan-in terminal SIN, a control input terminal SMC, and a clock terminal. CLK and data output terminal Q are provided.

  The output of the seq SFF 70 is connected to the scan-in terminal SIN of the subsequent seq SFF 60. The output of the last stage seqSFF60 is connected to the data input terminal DATA2 of seqSFF70. Similar to the seqSFF60, the seqSFF70 can capture the calculation results from the DUT2 at each of a plurality of capture clocks in one capture operation period.

  The data input terminal DATA receives the calculation result from the DUT 2 during the capture operation period. The first operation result captured by the last seqSFF 60 with the first capture clock during the capture operation period is input to the data input terminal DATA2. That is, the seqSFF 70 has two data input terminals.

  The AND gate 71 outputs a logical product of the signal input from the data input terminal DATA2 and the test enable signal. The XOR gate 72 receives the signal input from the data input terminal DATA and the logical product input from the AND gate 71, and outputs an exclusive OR.

  The MUX 73 receives a signal input from the scan-in terminal SIN and a signal output from the XOR gate 72. The MUX 73 switches between the scan shift operation and the capture operation in accordance with the scan enable signal input from the control input terminal SMC. In the example shown in FIG. 34, when the scan enable signal is high (1), the MUX 73 is enabled to input from the scan-in terminal SIN. Further, the MUX 73 is enabled to output from the XOR gate 72 when the scan enable signal is low (0).

  The FF 74 takes in the value output from the MUX 73 according to the clock signal (clock 2) input from the clock terminal CLK, and outputs the value from the data output terminal Q to the scan-in terminal SIN of the seq SFF 60 in the subsequent stage.

  The seqSFF 70 takes in the value of the scan-in terminal SIN when the scan enable signal = 1. The seqSFF 70 takes in a value from the data input terminal DATA when the test enable signal = 0 and the scan enable signal = 0. When the test enable signal = 1 and the scan enable signal = 0, the exclusive OR of the value of the data input terminal DATA and the value of the data input terminal DATA2 is captured at the second capture clock following the first capture clock.

  In other words, the seqSFF 70 can simultaneously capture failures that have reached both the data input terminal DATA and the data input terminal DATA2. Therefore, the first calculation result captured by the last seqSFF 60 in the scan chain 6H with the first capture clock is transmitted to the foremost seqSFF 70 with the second capture clock after the first capture clock.

  As described above, in the semiconductor device 1H according to the ninth embodiment, even when a plurality of capture clocks are applied during one capture operation period in the clock sequential test, they are taken into the last seqSFF 60 of the scan chain 6H with a certain capture clock. The fault that has been transmitted is propagated to the front-stage seqSFF 70 at the next capture clock and does not disappear.

  In the configurations of the fifth to eighth embodiments, in the clock sequential test, the operation result captured in the seqSFF 60 at the last stage of the scan chain with a certain capture clock is lost without being transmitted in the next capture cycle.

  However, as in the ninth embodiment, when the circuit configuration shown in FIG. 34 is used, the operation result captured in the last-stage seqSFF 60 can be propagated to the first-stage seqSFF 70 with the capture clock of the next capture cycle, and disappears. Can be prevented. As a result, when the capture clock is applied a plurality of times during the capture operation period, the number of faults that can be detected increases, and the test time can be shortened and the fault detection rate can be improved.

  Note that seqSFF2 is not limited to the logical structure of seqSFF70 shown in FIG. The configuration of the seqSFF 70 is the schematic configuration of the sequential test scan flip-flop shown in FIG. 35, and may be any configuration as long as it satisfies the functions shown in the truth table shown in FIG.

又は否定排他的論理和

が取り込まれる。 That is, when the scan enable signal = 0 and the test enable signal = 0, the value of the data input terminal DATA is captured. When the scan enable signal = 0 and the test enable signal = 1, the values of the data input terminal DATA and the data input terminal DATA2 are exclusive ORed.

Or negative exclusive OR

Is captured.

が取り込まれる。 When the scan enable signal = 1, the value of the scan-in terminal SIN (SIN) or the value of the scan-in terminal SIN is negated regardless of the value of the test enable signal.

Is captured.

Embodiment 10 FIG.
A semiconductor device in which the sequential test scan flip-flop (seqSFF) according to the tenth embodiment is inserted will be described with reference to FIG. FIG. 37 is a diagram showing a configuration of the semiconductor device 1I in which the seqSFF according to the tenth embodiment is inserted. As shown in FIG. 37, the semiconductor device 1I includes a DUT 2, a PRPG 3, a MISR 4I, an LBIST controller 5, and a seq SFF 60. In the semiconductor device 1I, in the clock sequential test, the fault propagated to the last seqSFF 60 can be held by the MISR 4I.

  In the semiconductor device 1I, at least one scan chain 6I among the plurality of scan chains is composed of a seqSFF 60 and a normal FF. In the example shown in FIG. 37, the seqSFF 60 is arranged at the head of the scan chain 6I, the shift register structure including the seq SFF 60 and two normal FFs is arranged at the subsequent stage, and the seq SFF 60 is connected at the subsequent stage.

  As the observation SFF 30, the one shown in FIG. 16 is used. In the example shown in FIG. 34, seqSFF60 is used, but seqSFF having another configuration satisfying the function of the truth table shown in FIG. 21 may be used instead of seqSFF60. In other scan chains, an SFF is arranged at the head, and an SFF, two normal FFs, and an SFF are sequentially connected to the subsequent stage. The configuration of the scan chain is the same as that of the example of FIG.

  The first operation result captured by the last seqSFF 60 of the scan chain 6I with the first capture clock is propagated to the MISR 4I with the second capture clock after the first capture clock. In the example shown in FIG. 37, a clock signal (clock 2) is input to MISR 4I. The MISR 4C captures the value output from the last-stage seqSFF 60 in synchronization with the clock signal (clock 2).

  In a normal scan test, it is not necessary to observe the output of the last stage flip-flop of the scan chain during the capture operation period. For this reason, the normal MISR does not have a function of capturing the output value of the final stage flip-flop during the capture operation period.

  In the tenth embodiment, MISR 4I operates with a clock supplied even during the capture operation period. Thus, MISR 4I can capture the output value of seqSFF 60 in the final stage of scan chain 6I even when a plurality of capture clocks are applied in the clock sequential test.

  In this way, in each capture cycle, the fault that has reached the last-stage seqSFF 60 can be captured by the MISR 4I, and can be observed without disappearing. As a result, the number of faults that can be detected during one capture operation period of the clock sequential test can be increased, and the test time can be reduced.

  A design apparatus 200 according to an embodiment will be described with reference to FIGS. FIG. 38 is a diagram showing a configuration of a design apparatus 200 for designing the semiconductor device according to the fifth to tenth embodiments. FIG. 39 is a diagram illustrating a design flow of the semiconductor device according to the embodiment. The design apparatus 200 is designed to design a semiconductor device using the above-described seqSFF and having high clock sequential test efficiency.

  The design device 200 includes an arithmetic processing device 210, a storage device 220, a control input device 230, and a display output device 231. The control input device 230 and the display output device 231 have the same configuration as the control input device 130 and the display output device 131 described with reference to FIG.

  The arithmetic processing unit 210 is a device that can load programs necessary for designing the semiconductor devices 1D to 1I and execute each functional process necessary for the design, and includes a CPU, a memory, and the like. The arithmetic processing unit 210 has a scanning program 212. In addition to the general scan function, the scan program 212 replaces the scan target user FF with a seq SFF that satisfies the function of the truth table in FIG. It has a function of selecting a user FF that is highly effective.

  The storage device 220 includes a function library 222, a test constraint DB 223, and a scanned netlist 226. The storage device 220 indicates a storage medium such as an HDD disk or a memory for storing library and netlist information.

  In addition to the above-described seqSFF cell information, the netlist 221 stores cell information such as AND gates, OR gates, and XOR gates, connection information between terminals, and the like. The function library 222 stores cell functions and the like. The test constraint DB 223 stores information necessary for circuit operation during testing.

  The design apparatus 200 uses the scan program 212 of the arithmetic processing unit 210 and inserts the seqSFF described in the fifth to tenth embodiments with reference to the netlist 221, the function library 222, and the test constraint DB 223 of the storage device 220. A semiconductor device is produced.

  Here, a design flow of the semiconductor device will be described with reference to FIG. As shown in FIG. 39, first, predetermined information is input to the net list 221, the function library 222, and the test constraint DB 223 (step S31). Thereafter, by analyzing the input information, circuit information and test constraint information are identified (step S32). Here, the scannable user FF in the circuit, test constraint information, and the like are acquired. Then, the user FF having the shift register structure is identified from the circuit structure (step S33).

  Then, based on the information of the identified scannable user FFs, the area overhead is taken into consideration, the user FFs to be replaced with the seqSFF are selected by an arbitrary designated number, and the replacement target candidates for the seqSFF are determined (step S34). The algorithm for selecting a replacement target candidate for seqSFF can be reduced to, for example, a problem of maximizing the number of observable faults on the input logic cone of the replacement target user FF.

  When the candidate for replacement with seqSFF has been determined, the seqSFF replacement target user FF is replaced with seqSFF, and a scan chain is constructed using the subsequent shift register structure (step S35). The other user FFs are also replaced with SFFs to construct a scan chain (step S36). As a result, the scanned netlist with the seqSFF inserted is output (step S37), and the netlist generation process ends. By using the design apparatus 200 shown in FIG. 38, a scanned netlist having a circuit structure with high sequential test efficiency can be generated.

  A semiconductor device capable of increasing the number of faults that can be detected during one capture operation period of the clock sequential test and reducing the test execution time by using the scanned netlist generated in this way. It becomes possible to design.

  As subsequent steps, a compression scan circuit or LBIST circuit is added by a general compression circuit addition program, and a clock sequential test pattern is generated by a general test generation program. Thereby, the test time reduction effect as shown in FIG. 31 is obtained.

  Note that the above-described embodiments can be combined as appropriate. For example, it is possible to configure a semiconductor device in which both the test point circuit and the sequential test scan flip-flop described above are inserted. FIG. 40 shows a configuration example of a semiconductor device in which the test point circuit 20 and the seqSFF 60 are inserted.

  As shown in FIG. 40, at least one of the plurality of scan chains is composed of only the observation SFF 20. In addition, at least one of the other scan chains is configured by only seqSFF60. In the example shown in FIG. 40, five observation SFFs 20 are serially connected in one scan chain. Further, five seqSFFs 60 are serially connected in the other one scan chain.

  In this way, by inserting the observation SFF 20 and the seq SFF 60, when performing a clock sequential test, an increase in area overhead due to test point insertion is suppressed, and the failure detection rate is increased while shortening the test time. It becomes possible.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 1A-1I Semiconductor device 2 DUT
3 PRPG
4 MISR
4C MISR
4I MISR
5 LBIST controller 6A-6I scan chain 7A-7D shift register structure 8 shift register 10 SFF
11 MUX
12 FF
20 SFF for observation
21 XOR gate 22 MUX
23 FF
30 SFF for observation
31 NOR gate 32 XOR gate 33 FF
40 SFF for observation
41 XOR gate 42 MUX
43 FF
50 SFF for observation
51 XOR gate 52 MUX
53 FF
60 seqSFF
60A-60C seqSFF
61 NOR gate 62 NAND gate 63 XOR gate 64 FF
65 OR gate 66 OR gate 67 XOR gate 68 MUX
69 MUX
70 seqSFF
71 AND gate 72 XOR gate 73 MUX
74 FF
SEQ_TEST_EN Test enable input terminal 100 Design device 110 Arithmetic processing device 111 Test point insertion program 112 Scanning program 120 Storage device 121 Netlist 122 Function library 123 Test constraint DB
124 Test point inserted net list 125 Test point inserted information DB
126 Scanned Net List 130 Control Input Device 131 Display Output Device 200 Design Device 210 Arithmetic Processing Device 212 Scanned Program 220 Storage Device 221 Net List 222 Function Library 223 Test Constraint DB
226 Scanned netlist 230 Control input device 231 Display output device DATA Data input terminal SIN Scan-in terminal SMC Control input terminal CLK Clock terminal Q Data output terminal

Claims (28)

A test point circuit inserted in a combinational circuit that outputs a calculation result in response to a test signal scanned in;
The plurality of test point circuits constitute a scan chain,
In one capture operation period of the clock sequential test, the first operation result captured by the test point circuit in the previous stage or the test point circuit in the last stage of the scan chain with the first capture clock is obtained after the first capture clock. Capture with the second capture clock of
Test point circuit. A scan-in terminal to which the test signal is input during a scan shift operation period, and the first calculation result captured by a test point circuit in the previous stage of the scan chain is input during the capture operation period;
A data input terminal to which an operation result from the combinational circuit is input;
An XOR gate that receives an operation result input to the data input terminal and the first operation result input to the scan-in terminal and outputs an exclusive OR in the capture operation period;
A flip-flop that captures the exclusive OR with the second capture clock;
Comprising
The test point circuit according to claim 1. A scan-in terminal to which the test signal is input during a scan shift operation period, and the first calculation result captured by a test point circuit in the previous stage of the scan chain is input during the capture operation period;
A data input terminal to which an operation result from the combinational circuit is input;
A NOR gate that receives a calculation result input to the data input terminal and a control signal for switching from the scan shift operation to the capture operation in the capture operation period and outputs a negative OR;
An XOR gate that receives the first operation result input to the scan-in terminal and the negative logical sum and outputs an exclusive logical sum;
A flip-flop that captures the exclusive OR input from the XOR gate with the second capture clock;
Comprising
The test point circuit according to claim 1. A scan-in terminal to which the test signal is input during a scan shift operation period;
A first data input terminal to which an operation result from the combinational circuit is input;
A second data input terminal to which the first operation result captured by the test point circuit at the last stage of the scan chain is input during the capture operation period;
An XOR gate that receives an operation result input to the first data input terminal and the first operation result input to the second data input terminal and outputs an exclusive OR in the capture operation period;
A flip-flop that captures the exclusive OR with the second capture clock;
Comprising
The test point circuit according to claim 1. A combinational circuit that outputs a calculation result according to a test signal scanned in;
A plurality of test point circuits inserted into the combinational circuit;
With
The plurality of test point circuits constitute a scan chain,
The scan chain is
In one capture operation period of the clock sequential test,
A first test point circuit for capturing a first operation result with a first capture clock;
A second test point circuit for capturing the first operation result captured by the first test point circuit at a second capture clock after the first capture clock;
including,
Semiconductor device. The second test point circuit is provided at a subsequent stage of the first test point circuit.
The semiconductor device according to claim 5. A third test point circuit provided at the last stage of the scan chain;
The first test point circuit is provided in the forefront stage of the scan chain,
The third test point circuit captures a second operation result with the first capture clock;
The first test point circuit receives the second operation result captured by the third test point circuit at the second capture clock;
The semiconductor device according to claim 6. The first test point circuit is provided at the last stage of the scan chain,
The second test point circuit is provided in the forefront stage of the scan chain.
The semiconductor device according to claim 5. A compressor for compressing a response result output from the scan chain;
The compressor captures an operation result captured by a test point circuit provided at the last stage of the scan chain with the first capture clock with the second capture clock.
The semiconductor device according to claim 5. The second test point circuit includes:
A scan-in terminal to which the test signal is input during a scan shift operation period, and the first calculation result captured by a test point circuit in the previous stage of the scan chain is input during the capture operation period;
A data input terminal to which an operation result from the combinational circuit is input;
An XOR gate that receives an operation result input to the data input terminal and the first operation result input to the scan-in terminal and outputs an exclusive OR in the capture operation period;
A flip-flop that captures the exclusive OR with the second capture clock;
Comprising
The semiconductor device according to claim 5. The second test point circuit includes:
A scan-in terminal to which the test signal is input during a scan shift operation period, and the first calculation result captured by a test point circuit in the previous stage of the scan chain is input during the capture operation period;
A data input terminal to which an operation result from the combinational circuit is input;
A NOR gate that receives a calculation result input to the data input terminal and a control signal for switching from the scan shift operation to the capture operation in the capture operation period and outputs a negative OR;
An XOR gate that receives the first operation result input to the scan-in terminal and the negative logical sum and outputs an exclusive logical sum;
A flip-flop that captures the exclusive OR input from the XOR gate with the second capture clock;
Comprising
The semiconductor device according to claim 5. The second test point circuit includes:
A scan-in terminal to which the test signal is input during a scan shift operation period;
A first data input terminal to which an operation result from the combinational circuit is input;
A test point circuit at the last stage of the scan chain during the capture operation period; a second data input terminal to which the first calculation result is input;
An XOR gate that receives an operation result input to the first data input terminal and the first operation result input to the second data input terminal and outputs an exclusive OR in the capture operation period;
A flip-flop that captures the exclusive OR with the second capture clock;
Comprising
The semiconductor device according to claim 5. A pseudo random number generator provided on the input side of the scan chain and supplying a pseudo random number as the test signal;
The semiconductor device according to claim 5. A semiconductor device design apparatus including an arithmetic processing unit capable of executing predetermined processing according to a preset program,
The semiconductor device includes:
A combinational circuit that outputs a calculation result according to a test signal scanned in;
A plurality of test point circuits inserted into the combinational circuit;
With
The plurality of test point circuits constitute a scan chain,
The scan chain is
In one capture operation period of the clock sequential test,
A first test point circuit for capturing a first operation result with a first capture clock;
A second test point circuit for capturing the first operation result captured by the first test point circuit at a second capture clock after the first capture clock;
Including
The arithmetic processing unit executes a circuit generation process for generating the semiconductor device with reference to a net list.
Design equipment. The arithmetic processing unit includes:
Performing an analysis process for analyzing a probability that an operation result from the combinational circuit becomes a predetermined logic state;
Based on the result of the analysis process, the insertion position of the test point circuit is selected,
Inserting the first test point circuit and the second test point circuit at the selected insertion position;
The scan chain is configured using the first test point circuit and the second test point circuit.
The design apparatus according to claim 14. The arithmetic processing unit includes:
In the scan chain, a process of connecting the second test point circuit to a subsequent stage of the first test point circuit is executed.
The design apparatus according to claim 14. The semiconductor device includes:
A third test point circuit that configures the scan chain together with the first and second test point circuits and captures a second operation result with the second capture clock;
The arithmetic processing unit includes:
A process of connecting the first test point circuit to the forefront stage of the scan chain and the third test point circuit to the last stage of the scan chain so that the first test point circuit receives the second operation result. Run,
The design apparatus according to claim 14. The arithmetic processing unit includes:
Executing a process of connecting the first test point circuit to the last stage of the scan chain and connecting the second test point circuit to the front stage of the scan chain;
The design apparatus according to claim 14. The arithmetic processing unit executes a process of inserting a compressor for compressing a response result output from the scan chain on the output side of the test point circuit provided in the last stage of the scan chain.
The design apparatus according to claim 14. The compressor captures an operation result captured by a test point circuit provided at the last stage of the scan chain with the first capture clock with the second capture clock.
The design apparatus according to claim 19. A scan flip-flop for a sequential test that can switch between a scan shift operation that constitutes a scan chain and operates as a shift register, and a capture operation that captures an operation result from a combinational circuit,
The sequential test scan flip-flop
A test enable input terminal for inputting a test enable signal is provided.
In response to the test enable signal, in one capture operation period of the clock sequential test,
From the combination circuit captured by the first capture clock by the first cell at the last stage of the scan chain in the scan chain or at the last stage of the scan chain at the second capture clock after the first capture clock. The first calculation result of
Scan flip-flop for sequential test. The sequential test scan flip-flop
In the second capture clock, an exclusive OR or a negative exclusive OR of the first operation result and the second operation result from the combinational circuit captured by the sequential test scan flip-flop is captured.
The sequential test scan flip-flop according to claim 21. A scan chain including the sequential test scan flip-flop according to claim 21 and a first cell, and a combinational circuit,
A semiconductor device capable of switching between a scan shift operation for operating the first cell in the scan chain and the scan flip-flop for sequential test as a shift register and a capture operation for capturing a calculation result from the combinational circuit. ,
The first cell is
Capture the first operation result with the first capture clock in one capture operation period of the clock sequential test,
The sequential test scan flip-flop
A test enable input terminal for inputting a test enable signal is provided.
In response to the test enable signal, the first operation result is captured at a second capture clock after the first capture clock.
Semiconductor device. The sequential test scan flip-flop is an exclusive OR or negation of the first operation result and the second operation result from the combinational circuit captured by the sequential test scan flip-flop at the second capture clock. Incorporating exclusive OR
24. The semiconductor device according to claim 23. The first cell is a scan flip-flop;
In the scan chain, the sequential test scan flip-flop is connected to the subsequent stage of the first cell.
24. The semiconductor device according to claim 23. The first cell has a configuration similar to the sequential test scan flip-flop,
24. The semiconductor device according to claim 23. The scan chain is
A second cell having the same configuration as the sequential test scan flip-flop;
A flip-flop that directly captures the third operation result from the combinational circuit captured by the second cell;
Further comprising a shift register structure comprising:
24. The semiconductor device according to claim 23. A compressor for compressing a response result output from the scan chain;
The compressor observes the operation result captured by the sequential test scan flip-flop provided at the last stage of the scan chain with the first capture clock with the second capture clock.
The semiconductor device according to claim 25.

Images