WO2023169195A1

WO2023169195A1 - Method for generating test pattern, and electronic device and storage medium

Info

Publication number: WO2023169195A1
Application number: PCT/CN2023/077205
Authority: WO
Inventors: 王乃行; 王泽中; 余航; 黄宇
Original assignee: 华为技术有限公司
Priority date: 2022-03-07
Filing date: 2023-02-20
Publication date: 2023-09-14
Also published as: CN116775386A

Abstract

The present disclosure relates to a method for generating a test pattern, and an electronic device and a storage medium. The method for generating a test pattern comprises: during a test pattern generation process, particularly in an operation phase of test pattern tightening, detecting the test power of a tightened intermediate test packet, and adjusting a test packet of which the test power is higher than a threshold value, such that the test packet can meet power requirements. In this way, a test pattern which would originally be discarded in a simulation phase can meet power requirements after being adjusted during a test pattern generation process, such that the utilization rate of a test packet can be significantly improved. Therefore, when more test patterns are used instead of being discarded, a test circuit can be tested for more faults, thereby improving the coverage rate of tests for various faults.

Description

Methods, electronic devices and storage media for generating test vectors

This application claims the priority of the Chinese patent application submitted to the China Patent Office on March 7, 2022, with the application number 202210217081.5 and the invention name "Method, electronic device and storage medium for generating test vectors", and its entire content is approved This reference is incorporated into this application.

Technical field

The present disclosure relates to the field of electronics, and more particularly to methods and electronic devices for designing test circuits.

Background technique

During the manufacturing and packaging processes of chips, it is inevitable that chips will have defects due to various reasons (such as process, materials, etc.). Such defects will cause the chips to fail to work properly. The main task of chip testing is to pick out defective chips. Because the cost of such defective chips entering the market will be far greater than the cost of chip testing, chip testing is a crucial part of the chip manufacturing process.

Specifically, a design for testability (DFT) structure such as a scan chain can be added to the chip during the chip design stage, and a chip with a DFT structure can be manufactured. You can use automatic test pattern generation (ATPG) tools to generate multiple test patterns (test patterns) for various chip faults, and use automatic test equipment (automatic test equipment, ATE) to input test vectors for the chip under test. By comparing the response of the chip under test to the expected response, quality inspection can be performed immediately after production is completed.

As the complexity and scale of chip design continues to rise, chip power consumption also rises sharply. Modern chip designs based on scan chains will cause the chip to enter a state that it will not enter in functional mode during testing, thus causing additional power consumption. For example, during testing, the flipping of the logic values of registers in the scan chain generates power consumption during the test. Excessive test power consumption will cause the following problems: (1) causing power consumption hot spots in the chip, thereby causing breakdown and other damage to the chip; (2) excessive power consumption will cause electromigration, which will greatly affect the chip. reliability; (3) causing a reduction in the chip supply voltage, resulting in a loss of chip yield. According to the different stages of chip testing, test power consumption can be divided into the following two categories: shift power (shift power) in the stage when the logic value is shifted in the scan chain, and capture power (capture power) in the logic value capture stage. ). Shift power consumption represents the power consumption of the chip itself during the stages when the test vector is moved in and the test response is moved out. Capture power consumption refers to the power consumption generated when the chip enters the functional stage after the test vector is moved in and before the test response is moved out. In some conventional solutions, only after the final test vector is generated, it is verified whether the power consumption of the generated test vector meets the low power consumption requirements. This will lead to a large number of test vectors that do not meet the test power consumption requirements, thus affecting the performance of various test vectors. Test coverage for faults.

Contents of the invention

Based on the above problems, embodiments of the present disclosure aim to provide a method, an electronic device, a computer-readable storage medium and a program product for generating test vectors for generating test vectors for a circuit under test.

According to a first aspect of the present disclosure, a method for generating test vectors is provided. The method includes performing a test vector compaction operation on the first test package and the second test package to generate a first intermediate test package. The first test package and the second test package are used to test the circuit under test. The method also includes determining a test power consumption corresponding to the first intermediate test package; and in response to the test power consumption being higher than the first threshold power consumption, at least testing the first intermediate test based on a set of control clocks of a plurality of scan chains of the circuit under test. The package is adjusted to generate a second intermediate test package. A control clock set is used to control multiple registers in multiple scan chains. The method also includes determining the target test packet based on the second intermediate test packet in response to the adjusted second intermediate test packet not being higher than the first threshold power consumption. By detecting the test power consumption of the compressed intermediate test packets during the test vector generation process, especially during the test vector compression operation phase, and adjusting the test packets whose test power consumption is higher than the threshold, the performance of the test packets can be significantly improved. Utilization. Test packages are generated for each fault, so the test circuit can be detected for more faults when more test vectors are used instead of discarded.

In a possible implementation of the first aspect, generating the first intermediate test package includes: merging the first test package and the second test package to generate a combined test package; determining the shift power consumption corresponding to the combined test package ; In response to the shift power consumption not being higher than the second threshold power consumption, perform a dynamic compaction operation on the merged test packet to generate a first intermediate test packet. By first detecting the shift power consumption and performing the dynamic compaction operation only when the shift power consumption meets the requirements, test vectors that do not meet the shift power consumption requirements can be eliminated, thereby saving subsequent calculation time. This is because the shift Power Consumption It is often difficult to adjust a test package to meet shift power requirements.

In a possible implementation of the first aspect, performing a dynamic compression operation on the merged test package to generate the first intermediate test package further includes: performing a shift power consumption detection on the merged test package on which the dynamic compression operation is performed, in response to the If the power consumption of the merged test packet on which the dynamic compression operation is performed is not higher than the first threshold, the merged test packet on which the dynamic compression operation is performed is determined as the first intermediate test vector. During the process of performing dynamic compaction, unknown states in some test vectors in the merged test package will be assigned certain values, which may cause the shift power consumption of the merged test package to change. By once again detecting the shift power consumption, the safety of automatic vector testing can be ensured.

In a possible implementation of the first aspect, determining the test power consumption corresponding to the first intermediate test package includes: determining capture flip rates of multiple scan chains corresponding to the first intermediate test package; and generating a second intermediate test Including: in response to the capture flip rate being higher than the capture threshold flip rate, adjusting the first intermediate test packet based on at least a control clock set of a plurality of scan chains of the circuit under test to generate a second intermediate test packet. By detecting the capture toggle rate, the test power consumption can be determined in a simple way.

In a possible implementation of the first aspect, determining the shift power consumption corresponding to the merged test packet includes: determining shift flip rates of multiple scan chains corresponding to the merged test packet; and generating the first intermediate test includes: In response to the shift flip rate not being higher than the shift threshold flip rate, a dynamic compaction operation is performed on the merged test packet to generate a first intermediate test packet. By detecting the shift toggle rate, the test power consumption can be determined in a simple way.

In a possible implementation of the first aspect, generating the second intermediate test includes: in response to the test power consumption being higher than the first threshold power consumption, adjusting the first clock bit set in the first intermediate test packet. The adjusted first clock bit set is used to turn off the first clock in the control clock set, which is used to control registers in multiple scan chains, and the first clock is the clock that controls the most registers in the control clock set; and respond When the captured power consumption corresponding to the adjusted first intermediate test packet is not higher than the first threshold power consumption, the adjusted first intermediate test packet is determined as the second intermediate test packet. Some clocks can be turned off by adjusting the clock bits of the intermediate test packets. Because the clock is turned off, registers in the scan chain that are configured to receive this clock cannot change their logic values. Correspondingly, the number of flipped logic values of registers in the scan chain can be reduced, thereby reducing capture power consumption.

In a possible implementation of the first aspect, the method further includes: generating a first initial vector packet for the first test fault; determining a first test bit set corresponding to the first test fault; based on the first test bit a set to determine a set of clocks to be turned off; and based on the set of clocks to be turned off, adjust the first initialization vector packet to generate a first test packet. In a possible implementation of the first aspect, the method further includes: generating a second initial vector packet for the second test fault; determining a second test bit set corresponding to the second test fault; based on the second test bit set, determine the second set of clocks to be turned off; and based on the second set of clocks to be turned off, adjust the second initialization vector packet to generate Second test package. During fault testing, if a clock gate needs to be closed for a certain fault, the assignment combination corresponding to the clock gate can be used to close the clock gate. In this way, it can be clearly known in the subsequent simulation process that the corresponding clock gate is in a closed state, so that the possible logic value flip rate of the scan chain can be calculated more accurately.

In a possible implementation of the first aspect, the method further includes: determining clock gates for controlling multiple scan chains based on netlist data used to represent the circuit under test and a sample test vector set for the circuit under test Collection of distribution and clock control bits. The clock gate distribution represents a correspondence between multiple clock gates and registers in multiple scan chains that they respectively control. The clock gate is configured to close the clock gate based on the clock control bits in the received clock control bit set. corresponding register. In the pre-analysis stage, a small amount of ATPG and simulation can be performed on the original circuit under test. After this process is completed, the scan chain distribution and register distribution used in the circuit under test can be obtained. Through further analysis of these scan chain distributions and register distributions, the clock gate distribution can be obtained. The clock gate distribution can be used to close the clock gate in the subsequent test vector generation for faults, thereby more accurately calculating the possible logic value flip rate of the scan chain.

In a possible implementation of the first aspect, the method further includes: performing simulation using the netlist data and the sample test vector set to determine, for the circuit under test, a low-power circuit, each scan chain of the plurality of scan chains at least one of a toggle rate during a logic value shift process and a logic value toggle rate in a logic value capture stage for each register in the plurality of scan chains. In a possible implementation of the first aspect, determining the clock gate distribution and clock control bit set used to control multiple scan chains includes: determining the scan chain distribution based on the netlist data and the sample test vector set, and the scan chain distribution Represents the scan chains used in the automatic vector test generation process in multiple scan chains; determines the register distribution based on the netlist data and sample test vector set, and the register distribution represents the number of registers in multiple scan chains. The registers used in the automatic vector test generation process; and based on the scan chain distribution and register distribution, determine the clock gate distribution and clock control bit set. By analyzing the above data, a low-power control circuit can be generated that can have improved encoding capabilities and use fewer encoding bits. In addition, the shift flip rate of the scan chain and the capture flip rate of the register obtained through analysis can be used to constrain the shift power consumption and capture power consumption of the scan chain in subsequent stages. In addition, the shift toggle rate of the scan chain and the capture toggle rate of the register can also be used to determine the clock gate distribution.

According to a second aspect of the present disclosure, there is provided a computer-readable storage medium storing a plurality of programs configured to be executed by one or more processors, the plurality of programs including a program for executing the method according to the first aspect. instruction.

According to a third aspect of the present disclosure, a computer program product is provided. The computer program product includes a plurality of programs configured to be executed by one or more processors. The plurality of programs include a method for executing the method according to the first aspect. instructions.

According to a fourth aspect of the present disclosure, an electronic device is provided. The electronic device includes: one or more processors; and a memory including computer instructions that when executed by the one or more processors of the electronic device cause the electronic device to perform the method according to the first aspect.

According to a fifth aspect of the present disclosure, an electronic device is provided. The electronic device includes a generation unit, a test power consumption determination unit, an adjustment unit and a target test package determination unit. The generating unit is configured to perform a test vector compaction operation on the first test package and the second test package to generate a first intermediate test package, and the first test package and the second test package are used for testing the circuit under test. The test power consumption determining unit is configured to determine the test power consumption corresponding to the first intermediate test package. The adjustment unit is configured to adjust the first intermediate test package based on at least a control clock set of a plurality of scan chains of the circuit under test in response to the test power consumption being higher than the first threshold power consumption to generate a second intermediate test package, control Clock sets are used to control multiple registers in multiple scan chains. The target test packet determining unit is configured to determine the target test packet based on the second intermediate test packet in response to the adjusted second intermediate test packet not being higher than the first threshold power consumption. By detecting the test power consumption of the compressed intermediate test packets during the test vector generation process, especially during the test vector compression operation phase, and adjusting the test packets whose test power consumption is higher than the threshold, the performance of the test packets can be significantly improved. Utilization. Test packages are generated for individual faults, so more tests With vectors used instead of discarded, the test circuit can be detected for more faults.

In a possible implementation of the fifth aspect, the generation unit is further configured to: merge the first test packet and the second test packet to generate a merged test packet; determine the shift power consumption corresponding to the merged test packet; In response to the shift power consumption not being higher than the second threshold power consumption, a dynamic compaction operation is performed on the merged test packet to generate a first intermediate test packet. By first detecting the shift power consumption and performing the dynamic compaction operation only when the shift power consumption meets the requirements, test vectors that do not meet the shift power consumption requirements can be eliminated, thereby saving subsequent calculation time. This is because the shift Power Consumption It is often difficult to adjust a test package to meet shift power requirements.

In a possible implementation of the fifth aspect, the test power consumption determination unit is further configured to: determine capture flip rates of the plurality of scan chains corresponding to the first intermediate test packet; and the adjustment unit is further configured to include: responding When the capture flip rate is higher than the capture threshold flip rate, the first intermediate test packet is adjusted based on at least control clock sets of multiple scan chains of the circuit under test to generate a second intermediate test packet. By detecting the capture toggle rate, the test power consumption can be determined in a simple way.

In a possible implementation of the fifth aspect, the generation unit is further configured to: determine shift flip rates of the plurality of scan chains corresponding to the merged test packet; and flip in response to the shift flip rate not being higher than the shift threshold rate, perform a dynamic compaction operation on the merged test package to generate the first intermediate test package. By detecting the shift toggle rate, the test power consumption can be determined in a simple way.

In a possible implementation of the fifth aspect, the adjustment unit is further configured to: in response to the test power consumption being higher than the first threshold power consumption, adjust the first clock bit set in the first intermediate test packet. The adjusted first clock bit set is used to turn off the first clock in the control clock set, which is used to control registers in multiple scan chains, and the first clock is the clock that controls the most registers in the control clock set; and respond When the captured power consumption corresponding to the adjusted first intermediate test packet is not higher than the first threshold power consumption, the adjusted first intermediate test packet is determined as the second intermediate test packet. Some clocks can be turned off by adjusting the clock bits of the intermediate test packets. Because the clock is turned off, registers in the scan chain that are configured to receive this clock cannot change their logic values. Correspondingly, the number of flipped logic values of registers in the scan chain can be reduced, thereby reducing capture power consumption.

In a possible implementation of the fifth aspect, the generation unit is further configured to: generate a first initial vector packet for the first test fault; determine a first test bit set corresponding to the first test fault; based on the first test a set of bits to determine a set of clocks to be turned off; and based on the set of clocks to be turned off, adjust the first initialization vector packet to generate a first test packet. During fault testing, if a clock gate needs to be closed for a certain fault, the assignment combination corresponding to the clock gate can be used to close the clock gate. In this way, it can be clearly known in the subsequent simulation process that the corresponding clock gate is in a closed state, so that the possible logic value flip rate of the scan chain can be calculated more accurately.

In a possible implementation of the fifth aspect, the electronic device further includes: a distribution determination unit configured to determine, based on the netlist data used to represent the circuit under test and the sample test vector set for the circuit under test, the distribution determination unit for controlling the circuit under test. Clock gate distribution and clock control bit set of multiple scan chains. The clock gate distribution represents the correspondence between multiple clock gates and the registers in the multiple scan chains they control respectively. The clock gate is configured to be based on the received clock. Clock control in a set of control bits Control bits to turn off the register corresponding to the clock gate. In the pre-analysis stage, a small amount of ATPG and simulation can be performed on the original circuit under test. After this process is completed, the scan chain distribution and register distribution used in the circuit under test can be obtained. Through further analysis of these scan chain distributions and register distributions, the clock gate distribution can be obtained. The clock gate distribution can be used to close the clock gate in the subsequent test vector generation for faults, thereby more accurately calculating the possible logic value flip rate of the scan chain.

In a possible implementation of the fifth aspect, the electronic device is further configured to perform simulation using the netlist data and the sample test vector set to determine, for the circuit under test, the low-power circuit, each scan in the plurality of scan chains At least one of a toggle rate during a logic value shift process of the chain and a logic value toggle rate in a logic value capture phase for each register in the plurality of scan chains. In a possible implementation of the fifth aspect, the distribution determination unit is further configured to determine the scan chain distribution based on the netlist data and the sample test vector set, where the scan chain distribution represents the automatic vector test generation process in multiple scan chains. The scan chain used in the scan chain; determine the register distribution based on the netlist data and the sample test vector set, and the register distribution represents the registers used in the automatic vector test generation process among the multiple registers in multiple scan chains; and Based on the scan chain distribution and register distribution, the clock gate distribution and clock control bit set are determined. By analyzing the above data, a low-power control circuit can be generated that can have improved encoding capabilities and use fewer encoding bits. In addition, the shift flip rate of the scan chain and the capture flip rate of the register obtained through analysis can be used to constrain the shift power consumption and capture power consumption of the scan chain in subsequent stages. In addition, the shift toggle rate of the scan chain and the capture toggle rate of the register can also be used to determine the clock gate distribution.

It should be understood that what is described in this summary is not intended to identify key or important features of the embodiments of the disclosure, nor to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the description below.

Description of the drawings

The above and other features, advantages and aspects of various embodiments of the present disclosure will become more apparent with reference to the following detailed description taken in conjunction with the accompanying drawings. In the drawings, the same or similar reference numbers represent the same or similar elements, where:

FIG. 1 shows a schematic diagram of a simulation system of a logic circuit according to some embodiments of the present disclosure.

FIG. 2 shows a schematic structural diagram of a chip applying test compression technology according to some embodiments of the present disclosure.

3 shows a schematic diagram of a two-dimensional sparse two-dimensional switch matrix circuit applied to a low-power decoder and a mask decoder according to some embodiments of the present disclosure.

Figure 4 shows a schematic diagram of scan chains and combinational logic in accordance with some embodiments of the present disclosure.

Figure 5 shows a schematic flow diagram of a method for generating test vectors according to some embodiments of the present disclosure.

Figure 6 shows a schematic flowchart of a method for determining a low power control circuit in accordance with some embodiments of the present disclosure.

Figure 7 shows a schematic flow diagram of a method for generating test vectors according to some embodiments of the present disclosure.

Figure 8 shows a schematic flowchart of a method for determining test power consumption according to some embodiments of the present disclosure.

Figure 9 shows a schematic block diagram of an electronic device according to some embodiments of the present disclosure.

Figure 10 shows a schematic block diagram of an example device that may be used to implement embodiments of the present disclosure.

Detailed ways

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the disclosure are shown in the drawings, it should be understood that the disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, which rather are provided for A more thorough and complete understanding of this disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the scope of the present disclosure.

In the description of embodiments of the present disclosure, the term "including" and similar expressions shall be understood as an open inclusion, that is, "including but not limited to." The term "based on" should be understood to mean "based at least in part on." The terms "one embodiment" or "the embodiment" should be understood to mean "at least one embodiment". The terms "first," "second," etc. may refer to different or the same object. Other explicit and implicit definitions may be included below.

Preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

As used herein, the term "include" and its variations mean an open inclusion, ie, "including but not limited to." Unless otherwise stated, the term "or" means "and/or". The term "based on" means "based at least in part on." The terms "one example embodiment" and "an embodiment" mean "at least one example embodiment." The term "another embodiment" means "at least one additional embodiment". The terms "first," "second," etc. may refer to different or the same object. Other explicit and implicit definitions may be included below.

In the electronic design automation (EDA) design process of the chip, the user inputs the configuration to the EDA software, the EDA software generates the logic circuit, and then the chip is obtained through pattern making and tape-out. In the process of testing the chip, the chip can be installed on the ATE and the test stimulus is input by the ATE to the input pin of the IC chip. By comparing the response of the chip's output pin with the expected response, you can determine whether the chip is qualified. As mentioned above, as chip integration and complexity continue to increase, the set of required test vectors also grows rapidly. This results in increased chip testing costs. In order to control test costs, test compression technology is proposed to compress test vectors while ensuring test coverage. The test compression technique is based on scan chains. Scan chain technology essentially connects flip-flops in a sequential circuit into multiple "shift registers (scan cells)", and the input and output values of each shift register can be independently observed.

The feasibility of testing compression techniques is based on the fact that a single raw test generated by ATPG contains the input values of all shift registers in the scan chain, and only the input values on a small number of shift registers are valid values. Therefore, the original test vector can be compressed and decompressed to recover the effective value by stimulating the decompression module (decompressor). In addition, the output values on the scan chain can also be compressed through the response compression module (compactor). The output compression value is sent to ATE through the output pin, and ATE compares the output compression value with the expected value to locate the scan chain shift register position where the error occurred.

In addition, during chip testing, various possible failures need to be tested. To this end, a test package (test cub) for each fault needs to be generated. The test package for each fault can be generated through a series of calculation, analysis, verification and other operations to generate the final test package set. This final set of test packages is provided to the ATE, which uses the final set of test packages to verify whether the circuit design is faulty. Specifically, ATE performs ATPG on each target fault in the target fault set (fault list) to generate multiple test packages. After a certain amount of test packages are generated, the entire process will enter steps such as test package fusion (cube merging) to make the final test package set as compact as possible. In the last step of the process, the final test package set is simulated and the logical value flip rate of each test vector is calculated. If the logic value flip rate does not meet the requirements set by the user, the test vector will be discarded. In this type of conventional scenario, the testing process only adds a verification step after the final set of test packages is generated. Although this method can ensure that the final generated test vectors meet the requirements of low-power testing, a large number of test vectors will be discarded, which greatly affects the test coverage. For example, some faults may go undetected because their corresponding test vectors are discarded.

In some embodiments of the present disclosure, during the test vector generation process, especially in the test vector compression operation stage, the test power consumption of the compressed intermediate test packet is detected, and the test packet whose test power consumption is higher than the threshold is detected. Adjustments can be made to meet power consumption requirements. In this way, the test vectors that would have been discarded during the simulation phase will be adjusted to meet the power consumption requirements during the test vector generation process, which can significantly improve the utilization of the test package. Therefore, more test vectors are When used instead of discarded, the test circuit can be detected for more faults, thereby improving test coverage for various faults.

FIG. 1 shows a schematic diagram of a simulation system 100 for a logic circuit according to some embodiments of the present disclosure. In one embodiment, the simulation system 100 includes an electronic device 10 and an ATPG device 20, for example. In one embodiment, the electronic device 10 is, for example, a computer. Electronic device 10 includes a processor 14 and memory 12 , where processor 14 includes cache 16 . Alternatively, in some embodiments, cache 16 may also be independent of processor 14, which is not limited to the scope of the present disclosure. ATPG device 20 is configured to generate ATPG data for logic simulation and transmit the ATPG data to electronic device 10 . Although the electronic device 10 and the ATPG device 20 are limited independently in FIG. 1 , in some embodiments, the ATPG device 20 may be integrated with the electronic device 10 , which is not limited by the present disclosure. Electronic device 10 may include input devices, communication devices, displays, audio devices, and other components not shown here. The electronic device 10 may include, for example, a desktop computer, a notebook, a workstation, a server, and other devices with computing functions. The netlist file used to describe the logic circuit can be transferred to the electronic device 10 through various wired or wireless methods. Alternatively, the electronic device 10 may also use a storage medium in which the netlist file is stored to read the netlist file. ATPG device 20 may generate different ATPG data for different logic circuits. In one embodiment, the ATPG data includes, for example, simulation cycle data, original data input, fault simulation data, and the like. The simulation cycle data includes, for example, tick data, ie, data representing a time frame executed by the processor for logic simulation and/or fault simulation. The time frames of logic simulation and fault simulation may be the same or different, and this disclosure does not limit this. The original inputs include, for example, the original data inputs for each original data input port in the logic circuit in the logic simulation and the original clock input corresponding to the original clock port used to calculate the logic value of the clock port of the sequential logic gate. Since a time frame is usually multiple time frames, the raw data input for a single raw data input port may be a raw data input set for the multiple time frames, which includes a series of bit values, such as a 64-bit bit value. It will be appreciated that depending on the time frame, there may be more or fewer bit values, such as 32-bit or 128-bit bit values. The fault simulation data includes, for example, a fault data input for a fault data input. Similarly, since the time frame in fault simulation is usually multiple time frames, the original fault data input for a single fault input terminal can be a fault input set, which includes a series of bit values, such as 64 bits, for the multiple time frames. bit value. Bit values can have more or fewer bits.

FIG. 2 shows a schematic structural diagram of a chip applying test compression technology according to some embodiments of the present disclosure. FIG. 2 shows a schematic structural diagram of a chip 200 applying test compression technology according to some embodiments of the present disclosure. As shown in Figure 2, the chip 200 includes a circuit to be tested 211, a low-power shift register 216, a mask register 218, a decompression module 212, a compression module 213, a low-power controller 214, a mask controller 215, and multiple One AND gate 207-1, 207-2...207-N and multiple AND gates 209-1, 209-2...209-N, where N represents an integer greater than 1. In the chip 200, a low-power shift register 216, a mask register 218, a decompression module 212, a compression module 213, a low-power controller 214, a mask controller 215, and a plurality of AND gates 207-1, 207- 2…..207-N and multiple AND gates 209-1, 209-2…209-N are used to test the circuit under test 211. Therefore, in one embodiment, the test circuitry of chip 200 may include at least one of low power controller 214 or mask controller 215. In another embodiment, the test circuit of the chip 200 may further include a low-power shift register 216, a mask register 218, a decompression module 212, a compression module 213, and a plurality of AND gates 207-1, 207-2... .207-N and multiple AND gates 209-1, 209-2...209-N. When actually testing the chip 200, ATE inputs ATPG test vectors to the low-power shift register 216 of the chip 200 through a small number of input pins of the chip 200. The ATPG test includes the input compression value of the decompression module 212, that is, the compressed seed, the encoding value of the low-power controller 214, the encoding value of the mask controller 215, and so on. Input compressed values are injected into decompression module 212 via low power shift register 216 and mask register 218. The encoded value of the low-power controller 214 is injected into the low-power controller 214 via the low-power shift register 216 , and the encoded value of the mask controller 215 is injected via the low-power shift register 216 and the mask register 218 Mask Controller 215. During the input phase, the low-power controller 214 decodes the encoded value to open the appropriate scan chain. untie The compression module 212 decompresses the input compressed value of the low-power shift register 216, and fills the decompressed value into the corresponding shift register through shifting under the control of the low-power controller 214.

In the output stage, the mask controller 215 decodes the encoded value, uses the decoded bit value to mask the X state in the scan chain output value, and sends the processed output value to the response compression module 213 for compression. In one embodiment, the circuit under test 211 includes a plurality of scan chains 211-1, 211-2...211-N (hereinafter individually or collectively referred to as 11), the number of scan chains is related to the number of AND gates 207-1, 207 -2...207-N (hereinafter individually or collectively referred to as 7) corresponds to a plurality of AND gates 209-1, 209-2...209-N (hereinafter individually or collectively referred to as 9) respectively. Each scan chain may include one or more sequential logic circuits, such as registers, in the circuit under test. The network of sequential logic XOR gates generates a shift output in response to the shift output. The low-power controller 214 includes a low-power register 214A and a decoder 214B. The decoder 214B generates a control signal through decoding to control one or more of the AND gates 207-1, 207-2...207-N. The AND gate is turned on or off. For example, in multiple cycles, the decoder 214B may continuously generate a logic value “1” to the AND gate 207-1, so that the decompressed value is successively shifted and input to the scan chain 211-1. At the same time, the decoder 214B may output "0" to turn off the AND gates 207-2...207-N, so that the scan chains 211-2...211-N continue to receive "0"s. Since there is no logic value change in the scan chains 211-2...211-N, the sequential logic gates in the chip do not operate. Since the sequential logic gates do not operate, power consumption during testing can be reduced. The mask controller 215 includes a mask register 215A and a mask decoder 215B. The mask decoder 215B generates a control signal through decoding to control one of the AND gates 209-1, 209-2...209-N. Turning on or off multiple AND gates. Similarly, the mask decoder 215B can generate a control signal through decoding to close the AND gate corresponding to the scan chain having the X state among the AND gates 209-1, 209-2...209-N.

It should be understood that the embodiment of the present application does not limit the structure of the decompression module 212. The decompression module 212 may be any circuit capable of expanding a small amount of test stimuli into a large number of scan chain test vectors and outputting the test vectors. The decompression module 212 may be a random signal generator, for example. Similarly, the embodiment of the present application does not limit the structure of the response compression module 213. The response compression module 213 may be any circuit capable of receiving test responses and performing logical operations on the received test responses to output from a small number of output channels. The response compression module 213 may be, for example, a compression module based on a multiple-input signature register (MISR) or an XOR gate (XOR) tree structure.

3 shows a schematic diagram of a two-dimensional sparse two-dimensional switch matrix circuit 300 applied to the low-power decoder 214B or the mask decoder 215B according to some embodiments of the present disclosure. The sparse two-dimensional switch matrix circuit 300 may be, for example, a specific implementation of the low-power decoder 214B or the mask decoder 215B. It can be understood that the two-dimensional sparse two-dimensional switch matrix circuit may have different switch distributions depending on the circuit 11 to be tested. As shown in FIG. 3, the sparse two-dimensional switch matrix circuit 300 includes a plurality of rows and a plurality of columns. Each row may be controlled by a corresponding row select signal from row selector 32 . Each column may be controlled by a corresponding column select signal of column selector 33 . Different from the switch matrix circuit 200 , the sparse two-dimensional switch matrix circuit 300 has switches coupled with the scan chain of the circuit under test 11 , such as switches 31 or 34 , at only some nodes among the row and column nodes. In other words, switches coupled to scan chains may not be provided at some nodes of rows and columns in the sparse two-dimensional switch matrix circuit 300 . Therefore, a sparse two-dimensional switch matrix circuit represents a two-dimensional switch matrix circuit in which at least one node does not have a switch. In Figure 3, although rows and columns are shown crossing at some nodes without switches, this is only to simplify the illustration. It can be understood that the conductive lines of the rows and columns are not coupled, but disconnected at the nodes.

The sparse two-dimensional switch matrix circuit 300 allows the number of scan chains (control granularity of each dimension) connected to each column encoding bit (column encoding bit) and row encoding bit (row encoding bit) to be flexibly adjustable. For example, the number of scan chains connected to each row encoding bit can be less than the number of groups n, and the number of scan chains connected to each column encoding bit can be less than the number of rows m. In this article, granularity means the number of switches controlled by a row or column. In some embodiments, the granularity of the sparse two-dimensional switch matrix circuit can be set to a uniform granularity. That is, the switches in each row and column are substantially equal to each other, and the number of controlled switches differs by at most one. Since each row and column has essentially the same or close switches, this The total number of switches that are mistakenly turned on can be minimized. For example, as a comparison, assuming that switch 34 is located at a node above switch 31, the conduction of switch 34 will affect the conduction of the two switches on the left and right sides and switch 31 (a total of 3 switches). This is because when switch 34 When on, it must have its row and column set to 1. In other words, in this case, the encoding success rate of the three switches will be affected. When switch 34 is in the position shown in Figure 3, switch 34 only affects the switch to its right as well as switch 31 (only 2 switches). In other words, in this case, only the coding success rate of two switches is affected. Therefore, the sparse two-dimensional switch matrix circuit 300 is set as a uniform-granularity coefficient matrix, which can improve the coding success rate. Although a 3×3 two-dimensional sparse two-dimensional switch matrix circuit 300 is shown in FIG. 3 , this is only for illustration and does not limit the scope of the present disclosure. In some embodiments, the two-dimensional sparse two-dimensional switch matrix circuit may have an n×m two-dimensional structure, where n represents a row and has an integer value greater than 1, m represents a column and has an integer value greater than 1, and m is the same as n can be the same or different.

The switch in Figure 3 could be an AND gate. In other embodiments, the switches may be other logic gates or other switches. For a codec, for example, an OR gate can be used as a switch. When the row selection signal and column selection signal are both 1, the control bit signal output by the switch is 1, that is, the switch will open the corresponding scan chain. When the row selection signal or the column selection signal is 0, the control bit signal output by the switch 31 is 0, that is, the switch will close the corresponding scan chain. The number of rows and columns in the sparse two-dimensional switch matrix circuit 300 may be related to the number of scan chains of the circuit under test 11 . The distribution of switches coupled to different scan chains in the sparse two-dimensional switch matrix circuit 300 may be random or arranged according to certain rules. In some embodiments of the present disclosure, an optimized two-dimensional sparse switching distribution for the circuit under test 11 may be obtained through ATPG learning, as described below.

Figure 4 shows a schematic diagram of scan chain 411 and combinational logic 42 in accordance with some embodiments of the present disclosure. In one embodiment, scan chain 411 may be a specific example of scan chain 211-N in FIG. 2 and includes three registers 44, 46, and 48. It is understood that in other embodiments, the scan chain 411 may include more or fewer registers. Scan chain 411 and combinational logic 42 may be part of circuit under test 211 in FIG. 2 . As mentioned above, the scan chain 411 includes two phases during the test process, namely the shift phase and the capture phase.

During the shift phase, the shift enable (SE) terminals of registers 44, 46, and 48 receive the SE establishment signal. Therefore, the registers 44, 46, and 48 are at their respective shift input (SI) terminals. Shift logic values are received in turn. In one example, scan chain 411 receives an SI of "110". In this case, the logic value of scan chain 411 is flipped once. The shift flip rate of scan chain 411 is therefore 1/2, or 50%. In other embodiments, a scan chain receives a P-bit shift input, and the number of logic value flips of the P-bit input is T, then the shift flip rate _RS of the scan chain =T/(P-1), where Both T and P represent positive integers, and T is smaller than P.

During the capture phase, registers 44, 46 and 48 of scan chain 411 have all been moved into initial logic values. The SE terminal of registers 44, 46 and 48 receives the solution establishment signal and the SI terminal is disabled. The logic values of registers 44, 46 and 48 are supplied to combinational logic 42 at the Q terminal. After a series of combinational logic operations, the combinational logic 42 provides the logic values obtained by the operations to the registers 44, 46 and 48 through a data input (DI) terminal. The registers 44, 46 and 48 perform calculations in response to receiving the clock pulse signal at the terminal CK to obtain an updated output logic value at the corresponding terminal Q. Combinational logic 42, in its functional operation phase, may generate corresponding logical outputs Y1 and Y2 based on the received inputs X1, X2 and X3. During the test phase, the combinational logic 42 may calculate the logic output to the DI terminal of the register based on the multiple outputs from the Q terminal of the register. In addition, the combinational logic 42 may also receive a clock signal set CKS of the chip, and the clock signal set CKS may include one or more system clock pulses. Some of the clock gates (logic gates) in combinational logic 42 may selectively provide clock signals to registers 44, 46, and 48 based on system clock pulses and logic inputs, where the logic outputs may be from registers of the same or different scan chains. In this disclosure, a logic gate or a combination of logic gates in combinational logic 42 for controlling the clock port CK of a register (eg, turning the register off or on) is referred to as a clock gate. In contrast, a logic gate for calculating a logic value supplied to the DI terminal of the register using a logic value from the Q terminal of the register is called a computational logic gate. For example, in one embodiment, a clock gate may be an AND gate that receives a clock pulse on one end and a logic value from a register on the other end. In the case of a logic value of "1", the clock signal may be provided to the clock terminal CK of the register, and in the case of a logic value of "0", the clock gate is closed, that is, no clock signal is provided to The clock terminal CK of the register. Although the clock gate is shown as an AND gate here, it can be understood that this is only illustrative and does not limit the scope of the present disclosure. A clock gate can be an OR gate, an XOR gate, or a combination of multiple logic gates. In this case, the clock gates used to control different registers can be different, and the bit combinations of different clock gates used to turn off the corresponding registers can also be different. Furthermore, in some embodiments, one or more clock gates may control one register, and one clock gate may control one or more registers. It can be understood that the manner and combination of clock gate control registers may be different, and this disclosure does not limit this.

The clock gates in the combinational logic 42 may be the same as, different from, or partially the same as the calculation logic gates in the combinational logic 42, which is not limited by this disclosure. Additionally, although both clock gates and computational logic gates are shown here as part of combinational logic 42, this is for illustration only and does not limit the scope of the present disclosure. In other embodiments, clock gates and computational logic gates may belong to different combinational logic circuits.

Figure 5 shows a schematic flow diagram of a method 500 for generating test vectors in accordance with some embodiments of the present disclosure. It will be appreciated that various aspects described above with respect to FIGS. 1-4 may be selectively applicable to the method 500. At 502, an electronic device, such as a computer, optionally determines clock gate distribution and clock control for controlling a plurality of scan chains based on netlist data representing the circuit under test and a set of sample test vectors for the circuit under test. A collection of bits. The clock gate distribution represents a correspondence between multiple clock gates and registers in multiple scan chains that they respectively control. The clock gate is configured to close the clock gate based on the clock control bits in the received clock control bit set. corresponding register. For example, an AND gate, which is a clock gate, receives the logic value "0" on one input and the system clock pulse on the other input. In this case, the logic value "0" is the clock control bit in a clock control bit set.

Specifically, in the pre-analysis stage, a small amount of ATPG and simulation can be performed on the original circuit under test. After this process is completed, the scan chain distribution and register distribution used in the circuit under test can be obtained. Through further analysis of these scan chain distributions and register distributions, the clock gate distribution can be obtained. The clock gate distribution can be used to close the clock gate in the subsequent test vector generation for faults, thereby more accurately calculating the possible logic value flip rate of the scan chain.

Additionally, in some embodiments, method 500 further includes performing simulations using the netlist data and the set of sample test vectors to determine logic value shifts for each of the plurality of scan chains for the low power circuit of the circuit under test. At least one of a toggle rate in the process and a logic value toggle rate in a logic value capture stage for each register in the plurality of scan chains. Figure 6 shows a schematic flowchart of a method 600 of determining a low-power circuit in accordance with some embodiments of the present disclosure. The low-power consumption circuit may be, for example, at least one of the low-power decoder 214B and the mask decoder 215B in FIG. 2 . At 602, one or more alternative switch distributions may be determined based on characteristics of the circuit under test 211. It can be understood that for specific requirements, there may be various distributions of two-dimensional switch matrix circuits.

For a two-dimensional switch matrix circuit, the number of corresponding scan chains is determined, which can be determined through step 402, for example. For example, the total number of scan chains is N, and N represents an integer greater than 1. In one embodiment, determining the candidate switch distribution includes determining the number of rows and the number of columns of the two-dimensional switch matrix circuit. Determining the candidate switch distribution also includes determining a distribution of the plurality of switches coupled to the scan chain at nodes in the two-dimensional switch matrix circuit. The initial sparsity can be obtained based on the characteristics of the circuit under test 11 . Using the initial sparsity, the number of rows and columns of the switch distribution can be calculated. Sparsity can be defined as Where m and n are the number of rows and columns in the two-dimensional switch matrix circuit, and N is the number of scan chains of the circuit 11 under test. For example, the initial sparsity may be determined based on a coding success rate estimation model. You can refer to formulas (1)-(3) to use the binary search algorithm to determine the initial sparsity.

Among them, N represents the total number of scan chains, s represents sparsity, P represents the encoding success rate, k represents a test package that uses k scan chains, and d _k represents the number of test packages that use k scan chains in the test package set collected by ATPG statistics. Proportion, α represents the maximum proportion of the scan chain opened after encoding and decoding that the user expects, α can also be called the low power consumption threshold. m0 and n0 represent the number of rows and columns after N scan chains are closely arranged into a square matrix, that is, m0×n0=N. f ^s (m ₁ , n ₁ , k) represents the number of combinations of k scan chains that are successfully encoded within an m ₁ × n ₁ submatrix of the switch distribution when the sparsity is s. m1 and n1 indicate that k open scan chains may be distributed in the m1 row and n1 column of the sparse two-dimensional switch matrix circuit. u and v represent that k open scan chains may be distributed in the u row and v column in the m1 row and n1 column in the sparse two-dimensional switch matrix circuit. S ^s (α) represents the success rate of successfully encoding k scan chains when the sparsity is s and given α. The weighted sum of the success rate S ^s (α) and d _k represents the coding success rate P ^s (α) of the switch distribution determined by the current sparsity s on the test packet set of ATPG statistics.

When the coding success rate P ^s (α) is greater than the maximum coding success rate P _max , the sparsity s can be used as the initial sparsity s ₀ . The greater the sparsity, the higher the hardware cost. In addition, the study found that when the sparsity reaches a certain level, the encoding success rate does not increase significantly. Therefore, you can also set the condition that the initial sparsity s ₀ should be less than the maximum sparsity s _max .

The maximum encoding success rate P _max can be adjustable, for example, P _max can be set to 99%. The maximum sparsity s _max is also adjustable, for example s _max can be set to 100%. The maximum sparsity s _max can be related to a switch power limit, which represents the ratio of the actual number of flips to the maximum number of flips in the registers on the scan chain when the input is shifted.

Based on the determined sparsity s, the number of rows m and the number of columns n in the two-dimensional switch matrix circuit can be determined with reference to formulas (4)-(5).

Based on the determined number of rows m and column number n, one or more alternative switch distributions may be determined at uniform granularity using a random strategy or a deterministic strategy. Uniform granularity means that any two rows of m number have the smallest difference in the number of switches and any two columns of n number have the smallest difference in the number of switches. In other words, based on the determined number of rows m and number of columns n, the distribution of switches coupled to N scan chains at the nodes can be determined. Switch distribution can be random or arranged according to deterministic rules. For details on stochastic and deterministic strategies, see PCT/CN2021/109508, the entire text of which is incorporated herein by reference.

At 604, using the one or more candidate switch distributions, one or more encoding success rates corresponding to the one or more candidate switch distributions can be obtained. For example, one or more encoding success rates for one or more alternative switch distributions can be verified on a test set. After the distribution of multiple switches in the two-dimensional switch matrix circuit is determined, the encoding success rate can be calculated for each determined candidate switch distribution. The electronic device may determine the test set based on the test packet set collected by ATPG statistics. In some embodiments, for the low-power decoder 214B, the test set may be a set of test packets determined through fault sampling and ATPG, and the test set may only save the identification of the scan chain. In some embodiments, for the mask decoder 215B, the test set may include an observation test set and a mask test set. The observation test set includes the identification of the scan chain where the value of the logic gate to be observed is located, and the value of the logic gate to be observed is the value of the logic gate corresponding to the test package. Mask test set package Includes the identification of the scan chain in which the X-state is located that prevents the value of the logic gate to be observed from being observed. By validating one or more alternative switch distributions on the test set, the corresponding encoding success rate can be obtained.

At 606, a switching distribution for the circuit under test 211 may be determined based at least on one or more encoding success rates. In one embodiment, the switch distribution may be determined based on encoding success rate. Additionally, the switch distribution can be determined based on both coding success rate and sparsity. For example, it can be determined whether the encoding success rate reaches the encoding success rate threshold. The coding success rate threshold may be the maximum coding success rate P _max . If the encoding success rate threshold is reached, the current switch distribution may be determined as the switch distribution for the circuit under test 211 . Alternatively or additionally, one or more coding success rates may be compared to a coding success rate threshold to determine a first set of alternative switch distributions. Each candidate switch distribution in the first set of candidate switch distributions has a coding success rate that is higher than a coding success rate threshold. Further, the candidate switch distribution with the smallest sparsity in the first candidate switch distribution set may be determined as the switch distribution for the circuit under test 211 .

Alternatively, if the encoding success rate does not reach the encoding success rate threshold but the sparsity reaches the sparsity threshold, the current switch distribution may be determined as the switch distribution for the circuit under test 211 . Alternatively, if the encoding success rate does not reach the encoding success rate threshold and the sparsity does not reach the encoding success rate threshold, the sparsity may be increased. Based on the increased sparsity, a new one or more candidate switch distributions may be determined and steps 604 and 606 repeated to determine the switch distribution for the circuit under test 211 .

In some embodiments, the method 600 described above may use a random strategy and a deterministic strategy respectively to determine the corresponding switch distribution. In other words, a random strategy can be used to determine the first switch distribution that satisfies the threshold condition. A deterministic strategy can also be used to determine the second switch distribution that satisfies the threshold condition. At least one of coding success rate and sparsity of the first switch distribution and the second switch distribution may be further compared to determine the final switch distribution. For example, if the difference between the coding success rates of the first switch distribution and the second switch distribution on the test set is greater than the threshold δ, then the switch distribution with a higher coding success rate is selected as the final switch distribution. On the contrary, if the difference in coding success rate is less than the threshold δ, the switch distribution with smaller sparsity, that is, using fewer coding bits, is selected as the final switch distribution.

As described above, based on the determined number of rows m and column number n, one or more alternative switch distributions may be determined at uniform granularity using a random strategy or a deterministic strategy. For example, N switches coupled with N scan chains can be placed at multiple nodes in a two-dimensional switch matrix circuit using a random strategy or a deterministic strategy. The plurality of nodes may be some of the nodes in the rows and columns of the two-dimensional switch matrix circuit. Multiple nodes to be switched in the two-dimensional switch matrix circuit may be determined with uniform granularity using a random strategy or a deterministic strategy based on the number of rows m and the number of columns n.

In some embodiments, based on the determined plurality of nodes, a plurality of switches may be placed at a plurality of nodes in a random manner to determine one or more alternative switch distributions. In one embodiment, each switch coupled to a corresponding scan chain may be randomly arranged at one of the plurality of nodes. In another embodiment, multiple switches may also be positioned at multiple nodes in a deterministic manner to determine one or more alternative switch distributions. In other words, each switch coupled to a corresponding scan chain may be arranged at one of the plurality of nodes according to a rule. For low-power decoders, rules can be related to frequency of use and dependency of use of scan chains. For mask decoders, the rules can be related to the X-state distribution of the scan chain.

In some embodiments, multiple switches may be arranged at multiple nodes in a spiral manner from the center to the periphery according to the usage frequency of the corresponding scan chain to determine one or more alternative switch distributions. Among the plurality of switches, a switch corresponding to the scan chain with the highest usage frequency among the plurality of scan chains is set at a central node among the plurality of nodes. Specifically, the activation probability of the scan chain can be determined based on the test packet set, and the scan chains are spirally arranged from the center to the periphery according to the activation probability from high to low.

Alternatively or additionally, for the mask decoder, the scan chains that do not contain X states can be arranged at the periphery, and then the scan chains are spirally wound from the center to the periphery according to the frequency of the X states in the scan chain from high to low. Row. In other words, switches coupled to scan chains that do not contain X states are distributed on the periphery of the two-dimensional switch matrix circuit, and switches coupled to scan chains with the highest frequency of The nodes are distributed at the center of the two-dimensional switch matrix circuit.

Alternatively or additionally, a plurality of switches may be arranged at a plurality of nodes in a spiral manner from the center to the periphery according to the usage correlation of the corresponding scan chain to determine one or more alternative switch distributions. The usage correlation of the scan chains corresponding to two switches among the plurality of switches that are adjacent in the first direction or the second direction is greater than the usage correlation of the other two switches among the plurality of switches that are not adjacent in the first direction or the second direction. The usage dependency of the corresponding scan chain. The usage correlation of a scan chain can refer to the probability that each scan chain is used simultaneously with other scan chains.

Returning to 502 of FIG. 5 , the shift flip rate of the scan chain and the capture flip rate of the register obtained through analysis can be used to constrain the shift power consumption and capture power consumption of the scan chain in subsequent stages. In addition, the shift toggle rate of the scan chain and the capture toggle rate of the register can also be used to determine the clock gate distribution.

At 504, the electronic device may optionally add control bits in the test packet for the fault based on the scan chain distribution and the register distribution. In one embodiment, the electronic device may generate a first initialization vector packet for the first test fault and determine a first set of test bits corresponding to the first test fault. For example, for a certain fault, the initial vector package includes a first logical value sequence "1xxxx01xxx" and a second logical value sequence "xxx11xxxxx". Since some bits need to present specific logic values, the electronic device can determine the clock set to be turned off based on the first test bit set. For example, the electronic device may use the clock gate distribution and clock control bit set obtained in 502. When the clock corresponding to those specific bits is turned off (for example, by setting one end of the AND gate to 0), the register controlled by the clock gate retains that value (because there is no clock stimulus to enable the register). The electronic device may then adjust the first initial vector packet to generate the first test packet based on the set of clocks to be turned off. That is, the electronic device may set the logic value of the clock gate in the first initialization vector packet for turning off the clock. It can be understood that for different faults, the initial vector package can be generated in a similar manner and then the corresponding test package can be generated, which will not be described again here.

In this way, it can be clearly known in the subsequent simulation process that the corresponding clock gate is in a closed state, so that the possible logic value flip rate of the scan chain can be calculated more accurately. Although a specific clock is turned off using the clock gate distribution and clock control bit set analyzed in 502, this is only illustrative and does not limit the scope of the present disclosure. At 506, an electronic device such as a computer may perform a test vector compaction operation on the plurality of test packages to generate corresponding intermediate test vectors. It can be understood that different test packages can be generated for different faults. For example, for 100 faults, 100 test packages can be generated, each test package including a combination of test vectors for different scan chains. For example, the first test package may be for the test vector combination of scan chain 211-1 and scan chain 211-3. The test vector combination may include, for example, a first test vector "10xxxxxx011xxxxxxx" for the scan chain 211-1 and a second test vector "xxxxx1xxxxxxxxxxxx" for the scan chain 211-3, where x represents an unknown state, that is, the logical value is uncertain state.

Since the number of test packets and the bits they contain are usually huge, test vector compression operations need to be performed on multiple test packets to reduce the number of test packets and the amount of data. In some embodiments, test vector compaction includes at least one of test packet merging and dynamic compaction. In one embodiment, one test packet may be represented as 1xxx1xx0 and another test packet may be represented as 1x1xxxx0. After considering logical value compatibility, the two test packages can be merged into 1x1x1xx0. In this way, the number of test packages can be reduced. It can be understood that although compatibility is taken as an example to illustrate the merging of test packages, this is only illustrative and does not limit the scope of the present disclosure. Other test package merging schemes can be used. In some embodiments, some test packets (eg, merged test packets) may include many "x" bits. In this case, a dynamic compaction operation can be performed on the test packet, that is, some bits of "x" are filled with bit values for merging of test vectors.

At 508, the electronic device may perform a power consumption check on the test vector compacted intermediate test packet. In one embodiment, after performing test packet merging, a power consumption check may be performed on the merged test packets. In another embodiment, while executing After dynamic compression, a power consumption check is performed on the dynamically compressed test packet. Only when the compressed test vector is within the set threshold range, this test vector compression will be accepted, otherwise the test vector compression operation will be cancelled. That is, merging or dynamic compaction are not accepted.

Specifically, power consumption can be determined by calculating the toggle rate of a scan chain's registers, since the number of flips is essentially proportional to the test power consumption. As mentioned above, during the test process, there are two types of power consumption: shift power consumption and capture power consumption. The calculation of the flip rate fs for shift power consumption follows the following calculation rules:

Among them, n represents the number of scan chains contained in the entire circuit 211 under test, p represents the shift flip rate of each opened scan chain, and p is calculated through simulation results in the pre-analysis stage of the circuit. For different For the circuit under test, p is determined by the characteristics of the circuit itself.

In order to capture power consumption, clock gates are closed according to the number of clock gate control registers. The clock gates with more control registers will be given priority for closing. In other words, you can try to turn off the clock in sequence according to the number of clock gate control registers and detect the effect after turning it off. For example, after each clock gate is closed, the logic value flip rate in the current circuit under test is recalculated based on the updated test vector, and the calculation process traverses each clock gate. The rules are as follows: (1) If the clock gate is closed, the logic value of the register controlled by the clock gate cannot be flipped, then the number of such registers is recorded as n1; (2) If the clock gate is opened, the logic value of the register controlled by the clock gate cannot be reversed. The logic value of the register may be flipped, then the number of such registers is recorded as n2; (3) If the clock gate does not define the open or closed state, the logic value of the register controlled by the clock gate may be flipped, then the number of such registers is recorded as n2 The number is n3. The capture flip rate fc of the entire circuit under test 211 is calculated as follows, where θ represents the logic value flip rate of the register capture stage calculated during the circuit analysis stage:

At 510, the electronic device may adjust the test package based on the results of the power consumption check. In one embodiment, in response to the test power consumption being higher than the first threshold power consumption, the electronic device adjusts the first intermediate test vector package based on at least a control clock set of multiple scan chains of the circuit under test 211 to generate a second Intermediate test vector package. In one embodiment, the test power consumption includes, for example, at least one of the shift toggle rate fs and the capture toggle rate fc, and the first threshold power consumption may be, for example, the reference toggle rate. Although the test power consumption is represented by the flip rate here, this is only for illustration and does not limit the scope of the present disclosure. Other attributes or parameters can be used to characterize test power consumption. The control clock set includes, for example, a bit set for the clock of the CK end of each register, which may be used to turn off the corresponding clock, for example. As mentioned above, in the pre-analysis stage of 502, the clock gate distribution and the clock control bit set can be obtained. Further, the corresponding clock can be turned off based on the clock gate distribution and the clock control bit set.

In one embodiment, in the shifting phase, the electronic device may merge the first test vector packet and the second test vector packet to generate a merged test vector packet; determine the shift power consumption corresponding to the merged test vector packet; In response to the shift power consumption not being higher than the second threshold power consumption, a dynamic compaction operation is performed on the merged test vector packet to generate a first intermediate test vector packet. By first detecting the shift power consumption and performing the dynamic compaction operation only when the shift power consumption meets the requirements, test vectors that do not meet the shift power consumption requirements can be eliminated, thereby saving subsequent calculation time. This is because the shift Power Consumption It is often difficult to adjust the test vector package to meet the shift power consumption requirements.

In another embodiment, in the capture phase after shifting, if the electronic device determines that the power consumption of the merged test packet after the test vector compaction is higher than the threshold power consumption, the electronic device may adjust the merged test packet to avoid the test. Vector compaction is not accepted and test packets for a certain fault are dropped. In one embodiment, the electronic device may adjust the merged test package using a greedy algorithm, as described below with reference to Figures 7 and 8. By detecting the test power consumption of the compressed intermediate test vector package during the test vector generation process, especially during the test vector package compression operation stage, and detecting the test power consumption higher than the threshold Adjusting the test vector package can significantly improve the utilization of the test vector package. The test vector package is generated for each fault, so the test circuit can be detected for more faults when more test vectors are used instead of discarded.

Figure 7 shows a schematic flow diagram of a method for generating test vectors according to some embodiments of the present disclosure. The method 700 of FIG. 7 can be combined with the method 600 of FIG. 6 , so various aspects described with respect to the method 600 can be selectively applied to the method 700 , and the present disclosure will not be repeated here. At 701, the electronic device can determine a list of target faults. The target fault list may be input by the designer or come from other devices, and includes faults that need to be tested for the circuit under test 211 in the simulation. At 702, the electronic device determines whether test packages for all faults in the target fault list have been generated. At 704, if it is not completed, select a fault for which no test package is generated from the target fault list, generate a test package for the fault, and add it to the test package pool. Further, control bits may also be added to the test packet, such as the control bits described in 504 of FIG. 5 .

At 706, optionally, the electronic device can determine whether the test packet pool is full. It is understandable that test packages of test vectors usually contain more data, and the test package pool will continue to grow as test packages are added. By determining whether the test packet pool is full, it can be ensured that subsequent operations can be performed correctly without placing a greater operating burden on the electronic device. In other embodiments, if the performance of the electronic device such as a computer is strong enough or the number of faults in the target fault list is small, step 706 may be omitted.

At 708, in the event that the test packet pool is full, the electronic device may perform test packet merging and calculate the power consumption of the merged test packets. In one embodiment, the electronic device may combine the first test packet and the second test packet, and calculate the combined shift power consumption and capture power consumption. If the shift power consumption is higher than the shift threshold power consumption, the first test packet and the second test packet are refused to be merged, and an unmerged third test packet is selected to be merged with the first test packet. If the shift power consumption is not higher than the shift threshold power consumption, a determination of capture power consumption is made. Merging is acceptable if the capture power consumption is not higher than the capture threshold power consumption. If the capture power consumption is higher than the threshold power consumption, test vector adjustments can be made to the merged test package. For example, close some clock gates appropriately to meet the requirements of capturing power consumption. As described above, in response to the test power consumption being higher than the capture threshold power consumption, the first clock bit set in the first intermediate test vector packet is adjusted, and the adjusted first clock bit set is used in the shutdown control clock set a first clock, a set of control clocks for controlling registers in a plurality of scan chains, the first clock being a clock in the set of control clocks that controls the most registers; and in response to the capture function corresponding to the adjusted first intermediate test vector packet If the power consumption is not higher than the first threshold power consumption, the adjusted first intermediate test vector packet is determined as the second intermediate test vector packet. Some clocks can be turned off by adjusting the clock bits in the intermediate test vector packets. Because the clock is turned off, registers in the scan chain that are configured to receive this clock cannot change their logic values. Correspondingly, the number of flipped logic values of registers in the scan chain can be reduced, thereby reducing capture power consumption.

If the capture power consumption of the merged test packet cannot be adjusted to be lower than the capture power consumption threshold, the second test packet may be rejected and the third test packet may be used to merge with the first test packet. It can be understood that the merging, power consumption judgment and comparison of the third test package and the first test package are similar to the situations described above for the first test package and the second test package, and will not be described again here. It can be understood that all test packages in the test package pool can be merged sequentially using a greedy algorithm until all test packages have been merged or are refused to be merged.

At 710, similar to 708, the electronic device can perform the dynamic compression operation as described above on the test package, such as the merged test package, and calculate the shift power consumption of the dynamically compressed test package and capture whether the power consumption satisfies Corresponding power consumption requirements. Dynamic compression is only accepted if power requirements are met. Further, when the capture power consumption does not meet the requirements, some clock gates can be similarly closed for adjustment, thereby reducing the capture power consumption.

It can be understood that in the case of 708 and 710, in the subsequent shifting process of the logical value of the scan chain after dynamic compression, the shift flip rate exceeds the threshold flip rate due to some assignments, so it can be adjusted for scanning The shift power consumption of the chain is detected and judged again.

Although the test vector compaction is described above in the order of executing 708 first and then executing 710, it can be understood that this is only illustrative and does not limit the scope of the present disclosure. In some embodiments, only either 708 or 710 may be present. In other embodiments, step 710 may be performed first and then step 708, and this disclosure does not limit this. At 712, the electronic device may perform simulation, analyze the test vector compacted set of test packets, and discard failed test vector packets.

Figure 8 illustrates a schematic flow diagram of a method 800 for determining test power consumption in accordance with some embodiments of the present disclosure. The method 800 of FIG. 8 can be combined with the method 600 of FIG. 6 and/or the method 700 of FIG. 7 , so various aspects described with respect to the method 600 or 700 can be selectively applied to the method 800, and the present disclosure will not be repeated here. As mentioned above, test power consumption is essentially proportional to the toggle rate of the logic values of the memory in the scan chain. At 802, the electronic device may first calculate the shift flip rate for the scan chain of the test packet, as shown in equation (6) above. At 804, since the capture power consumption exceeds the threshold, the first clock set can be turned off appropriately to further reduce the capture power consumption. It can be understood that when the clock of the CK port in the register of the scan chain is turned off, the output of the Q port of the register will no longer change. That is, the output value of the register whose clock is turned off will not flip, thus reducing the overall flip rate and thus reducing the capture power consumption. At 806, the electronic device can calculate the shift toggle rate after turning off the first clock set. It can be understood that since the first clock set needs to be turned off, some registers in the multiple scan chains need to be assigned some logical values to turn off the first clock set. In this case, the test vectors in the test packet may change, which results in a change in the shift flip rate during the shift process. Therefore, by calculating the shift flip rate after turning off the first clock set, it is possible to avoid the occurrence of a situation where the shift power consumption exceeds the threshold.

Figure 9 shows a schematic block diagram of an electronic device 900 in accordance with some embodiments of the present disclosure. The electronic device 900 may include a plurality of modules for performing corresponding steps in the methods discussed in FIGS. 5-8 . As shown in FIG. 9 , the electronic device 900 includes a generation unit 902 , a test power consumption determination unit 904 , an adjustment unit 906 and a target test vector packet determination unit 908 . The generation unit 902 is configured to perform a test vector packet compaction operation on the first test vector packet and the second test vector packet to generate a first intermediate test vector packet, and the first test vector packet and the second test vector packet are used for the circuit under test. carry out testing. The test power consumption determining unit 904 is configured to determine the test power consumption corresponding to the first intermediate test vector packet. The adjustment unit 906 is configured to adjust the first intermediate test vector package based on at least the control clock set of the plurality of scan chains of the circuit under test in response to the test power consumption being higher than the first threshold power consumption to generate a second intermediate test vector. Package,Control Clock Set is used to control multiple registers in,multiple scan chains. The target test vector packet determination unit 908 is configured to determine the target test vector packet based on the second intermediate test vector packet in response to the adjusted second intermediate test vector packet not being higher than the first threshold power consumption. By detecting the test power consumption of the compressed intermediate test vector package during the test vector generation process, especially during the test vector package compression operation stage, and adjusting the test vector package whose test power consumption is higher than the threshold, it can be significantly improved. Test vector package utilization. The test vector package is generated for each fault, so the test circuit can be detected for more faults when more test vectors are used instead of discarded.

In some embodiments, the generating unit 902 is further configured to: merge the first test vector packet and the second test vector packet to generate a merged test vector packet; determine the shift power consumption corresponding to the merged test vector packet; respond When the shift power consumption is not higher than the second threshold power consumption, a dynamic compression operation is performed on the combined test vector packet to generate a first intermediate test vector packet. By first detecting the shift power consumption and performing the dynamic compaction operation only when the shift power consumption meets the requirements, test vectors that do not meet the shift power consumption requirements can be eliminated, thereby saving subsequent calculation time. This is because the shift Power Consumption It is often difficult to adjust the test vector package to meet the shift power consumption requirements.

In some embodiments, the test power consumption determination unit 904 is further configured to: determine capture toggle rates for the plurality of scan chains corresponding to the first intermediate test vector packet; and the adjustment unit 906 is further configured to include: in response to the capture toggle If the rate is higher than the capture threshold flip rate, the first intermediate test vector packet is adjusted based on at least a control clock set of the plurality of scan chains of the circuit under test to generate a second intermediate test vector packet. By detecting the capture toggle rate, the test power consumption can be determined in a simple way.

In some embodiments, the generation unit 902 is further configured to: determine shift flip rates of the plurality of scan chains corresponding to the merged test vector packet; and in response to the shift flip rate being not higher than the shift threshold flip rate, the merge The test vector package performs a dynamic compaction operation to generate a first intermediate test vector package. By detecting the shift toggle rate, the test power consumption can be determined in a simple way.

In some embodiments, the adjustment unit 906 is further configured to: in response to the test power consumption being higher than the first threshold power consumption, adjust the first clock bit set in the first intermediate test vector packet, and the adjusted first a set of clock bits for turning off a first clock in a set of control clocks, the set of control clocks being used to control registers in multiple scan chains, the first clock being a clock that controls the most registers in the set of control clocks; and in response to the adjusted The capture power consumption corresponding to the first intermediate test vector packet is not higher than the first threshold power consumption, and the adjusted first intermediate test vector packet is determined as the second intermediate test vector packet. Some clocks can be turned off by adjusting the clock bits in the intermediate test vector packets. Because the clock is turned off, registers in the scan chain that are configured to receive this clock cannot change their logic values. Correspondingly, the number of flipped logic values of registers in the scan chain can be reduced, thereby reducing capture power consumption.

In some embodiments, the generating unit 902 is further configured to: generate a first initial vector packet for the first test fault; determine a first test bit set corresponding to the first test fault; determine based on the first test bit set, a set of clocks to be turned off; and based on the set of clocks to be turned off, adjusting the first initial vector package to generate a first test vector package. During fault testing, if a clock gate needs to be closed for a certain fault, the assignment combination corresponding to the clock gate can be used to close the clock gate. In this way, it can be clearly known in the subsequent simulation process that the corresponding clock gate is in a closed state, so that the possible logic value flip rate of the scan chain can be calculated more accurately.

In some embodiments, the electronic device 900 further includes: a distribution determination unit configured to determine, based on the netlist data used to represent the circuit under test and the sample test vector set for the circuit under test, for controlling the plurality of scan chains. Clock gate distribution and clock control bit set. Clock gate distribution represents the correspondence between multiple clock gates and registers in multiple scan chains that they control respectively. The clock gate is configured to be based on the received clock control bit set. The clock control bit is used to close the register corresponding to the clock gate. In the pre-analysis stage, a small amount of ATPG and simulation can be performed on the original circuit under test. After this process is completed, the scan chain distribution and register distribution used in the circuit under test can be obtained. Through further analysis of these scan chain distributions and register distributions, the clock gate distribution can be obtained. The clock gate distribution can be used to close the clock gate in the subsequent test vector generation for faults, thereby more accurately calculating the possible logic value flip rate of the scan chain.

In some embodiments, the electronic device 900 is further configured to perform simulation using the netlist data and the sample test vector set to determine the logic value shift for each of the plurality of scan chains for the low power circuit of the circuit under test. At least one of: a toggle rate in a bit process and a logic value toggle rate in a logic value capture stage for each register in the plurality of scan chains. In some embodiments, the distribution determination unit is further configured to determine a scan chain distribution based on the netlist data and the sample test vector set, the scan chain distribution representing the scans used in the automatic vector test generation process among the plurality of scan chains. chain; based on netlist number According to the sample test vector set, the register distribution is determined. The register distribution represents the registers used in the automatic vector test generation process among the multiple registers in multiple scan chains; and based on the scan chain distribution and register distribution, the clock gate is determined Collection of distribution and clock control bits. By analyzing the above data, a low-power control circuit can be generated that can have improved encoding capabilities and use fewer encoding bits. In addition, the shift flip rate of the scan chain and the capture flip rate of the register obtained through analysis can be used to constrain the shift power consumption and capture power consumption of the scan chain in subsequent stages. In addition, the shift toggle rate of the scan chain and the capture toggle rate of the register can also be used to determine the clock gate distribution.

Figure 10 shows a schematic block diagram of an example device 1000 that may be used to implement embodiments of the present disclosure. As shown, device 1000 includes a computing unit 1001 that may be loaded into RAM 1003 and/or from storage unit 1008 in accordance with computer program instructions stored in random access memory (RAM) and/or read only memory (ROM) 1002 Computer program instructions in ROM 1002 to perform various appropriate actions and processes. In RAM 1003 and/or ROM 1002, various programs and data required for operation of device 1000 may also be stored. The computing unit 1001 and the RAM 1003 and/or ROM 1002 are connected to each other via a bus 1004. An input/output (I/O) interface 1005 is also connected to bus 1004.

Multiple components in the device 1000 are connected to the I/O interface 1005, including: input unit 1006, such as a keyboard, mouse, etc.; output unit 1007, such as various types of displays, speakers, etc.; storage unit 1008, such as a magnetic disk, optical disk, etc. ; and communication unit 1009, such as a network card, modem, wireless communication transceiver, etc. The communication unit 1009 allows the device 1000 to exchange information/data with other devices through computer networks such as the Internet and/or various telecommunications networks.

Computing unit 1001 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of the computing unit 1001 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processing processor (DSP), and any appropriate processor, controller, microcontroller, etc. The computing unit 1001 performs various methods and processes described above, such as methods 500, 600, 700 or 800. For example, in some embodiments, method 500, 600, 700, or 800 may be implemented as a computer software program tangibly embodied in a machine-readable medium, such as storage unit 1008. In some embodiments, part or all of the computer program may be loaded and/or installed onto device 1000 via RAM and/or ROM and/or communication unit 1009 . When a computer program is loaded into RAM and/or ROM and executed by computing unit 1001, one or more steps of method 300 described above may be performed. Alternatively, in other embodiments, computing unit 1001 may be configured to perform method 500, 600, 700 or 800 in any other suitable manner (eg, by means of firmware).

Program code for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing device, such that the program codes, when executed by the processor or controller, cause the functions specified in the flowcharts and/or block diagrams/ The operation is implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media may include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media would include one or more wire-based electrical connections, laptop disks, hard drives, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination of the above.

The various embodiments of the present disclosure have been described above. The above description is illustrative, not exhaustive, and is not limiting. in each of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, practical applications, or technical improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely example forms of implementing the claims.

Claims

A method for generating test vectors consisting of:

Perform a test vector compaction operation on the first test package and the second test package to generate a first intermediate test package, the first test package and the second test package being used to test the circuit under test;

Determine the test power consumption corresponding to the first intermediate test package;

In response to the test power consumption being higher than the first threshold power consumption, adjusting the first intermediate test package based on at least a control clock set of a plurality of scan chains of the circuit under test to generate a second intermediate test package, The control clock set is used to control a plurality of registers in the plurality of scan chains; and

In response to the adjusted second intermediate test packet being no higher than the first threshold power consumption, a target test packet is determined based on the second intermediate test packet.
The method of claim 1, wherein generating the first intermediate test package includes:

Merge the first test package and the second test package to generate a merged test package;

Determine the shift power consumption corresponding to the combined test package;

In response to the shift power consumption not being higher than the second threshold power consumption, a dynamic compaction operation is performed on the merged test packet to generate the first intermediate test packet.
The method of claim 1 or 2, wherein determining the test power consumption corresponding to the first intermediate test packet includes: determining capture flip rates of a plurality of scan chains corresponding to the first intermediate test packet; and

Generating the second intermediate test includes adjusting the first intermediate test package based on at least a set of control clocks for a plurality of scan chains of the circuit under test in response to the capture toggle rate being greater than a capture threshold toggle rate, to generate a second intermediate test package.
The method according to claim 2 or 3, wherein determining the shift power consumption corresponding to the merged test packet includes: determining shift flip rates of a plurality of scan chains corresponding to the merged test packet; and

Generating the first intermediate test includes performing a dynamic compaction operation on the merged test packet to generate the first intermediate test packet in response to the shift toggle rate being not higher than a shift threshold toggle rate.
The method of any one of claims 1-4, wherein generating the second intermediate test includes:

In response to the test power consumption being higher than the first threshold power consumption, adjusting a first clock bit set in the first intermediate test packet, the adjusted first clock bit set being used to turn off the control clock A first clock in a set, the control clock set is used to control registers in the plurality of scan chains, the first clock is the clock that controls the most registers in the control clock set; and

In response to the captured power consumption corresponding to the adjusted first intermediate test packet being not higher than the first threshold power consumption, the adjusted first intermediate test packet is determined to be the second intermediate test packet.
The method according to any one of claims 1-5, further comprising:

Generate the first initialization vector packet for the first test fault;

Determine a first test bit set corresponding to the first test fault;

Based on the first set of test bits, determine a set of clocks to be turned off; and

Based on the set of clocks to be turned off, the first initialization vector packet is adjusted to generate the first test packet.
The method according to any one of claims 1-6, further comprising:

Based on the netlist data used to represent the circuit under test and the sample test vector set for the circuit under test, a clock gate distribution and a clock control bit set for controlling multiple scan chains are determined, the clock gate distribution Represents the corresponding relationship between multiple clock gates and registers in multiple scan chains that they respectively control, and the clock gate is configured to be based on the received clock The clock control bit in the clock control bit set is used to close the register corresponding to the clock gate.
The method of claim 7, wherein determining a clock gate distribution and a set of clock control bits for controlling multiple scan chains includes:

Based on the netlist data and the sample test vector set, determine a scan chain distribution, where the scan chain distribution represents a scan chain used in the automatic vector test generation process among multiple scan chains;

Determine a register distribution based on the netlist data and the sample test vector set, the register distribution representing a register used in an automatic vector test generation process among a plurality of registers in a plurality of scan chains; and

Based on the scan chain distribution and the register distribution, the clock gate distribution and the clock control bit set are determined.
A computer-readable storage medium storing a plurality of programs configured to be executed by one or more processors, the plurality of programs including a method for executing the method described in any one of claims 1-8. Method instructions.
A computer program product comprising a plurality of programs configured to be executed by one or more processors, the plurality of programs including a program for executing any one of claims 1-8 instructions for the method described.
An electronic device including:

one or more processors;

A memory comprising computer instructions that when executed by the one or more processors of the electronic device cause the electronic device to perform the method of any one of claims 1-8.
An electronic device including:

a generating unit configured to perform a test vector compaction operation on the first test package and the second test package to generate a first intermediate test package, the first test package and the second test package being used to test the circuit under test ;

a test power consumption determination unit configured to determine the test power consumption corresponding to the first intermediate test package;

an adjustment unit configured to, in response to the test power consumption being higher than a first threshold power consumption, adjust the first intermediate test package based on at least a control clock set of a plurality of scan chains of the circuit under test to generate A second intermediate test package, the control clock set is used to control multiple registers in the multiple scan chains; and

The target test packet determining unit is configured to determine the target test packet based on the second intermediate test packet in response to the adjusted second intermediate test packet not being higher than the first threshold power consumption.
The electronic device of claim 12, wherein the generating unit is further configured to:

Merge the first test package and the second test package to generate a merged test package;

Determine the shift power consumption corresponding to the combined test package;

In response to the shift power consumption not being higher than the second threshold power consumption, a dynamic compaction operation is performed on the merged test packet to generate the first intermediate test packet.
The electronic device according to claim 12 or 13, wherein the test power consumption determination unit is further configured to: determine capture flip rates of a plurality of scan chains corresponding to the first intermediate test packet; and

The adjustment unit is further configured to include: in response to the capture toggle rate being higher than a capture threshold toggle rate, adjusting the first intermediate test package based on at least a control clock set of a plurality of scan chains of the circuit under test , to generate the second intermediate test package.
The electronic device according to claim 13 or 14, wherein the generating unit is further configured to:

determining shift flip rates for a plurality of scan chains corresponding to the merged test packet; and

In response to the shift toggle rate being not higher than a shift threshold toggle rate, a dynamic compaction operation is performed on the merged test packet to generate the first intermediate test packet.
The electronic device according to any one of claims 12-15, wherein the adjustment unit is further configured to:

In response to the test power consumption being higher than the first threshold power consumption, adjusting a first clock bit set in the first intermediate test packet, the adjusted first clock bit set being used to turn off the control clock A first clock in a set, the control clock set is used to control registers in the plurality of scan chains, the first clock is the clock that controls the most registers in the control clock set; and

In response to the captured power consumption corresponding to the adjusted first intermediate test packet being not higher than the first threshold power consumption, the adjusted first intermediate test packet is determined to be the second intermediate test packet.
The electronic device according to any one of claims 12-16, wherein the generating unit is further configured to:

Generate the first initialization vector packet for the first test fault;

Determine a first test bit set corresponding to the first test fault;

Based on the first set of test bits, determine a set of clocks to be turned off; and

Based on the set of clocks to be turned off, the first initialization vector packet is adjusted to generate the first test packet.
The electronic device according to any one of claims 12-17, further comprising:

a distribution determination unit configured to determine clock gate distribution and clock control bits for controlling multiple scan chains based on netlist data representing the circuit under test and a sample test vector set for the circuit under test A set, the clock gate distribution represents a correspondence between a plurality of clock gates and registers in a plurality of scan chains that they respectively control, and the clock gate is configured to be based on the clock control bits in the received clock control bit set. bit to turn off the register corresponding to the clock gate.
The electronic device of claim 18, wherein the distribution determining unit is further configured to:

Based on the netlist data and the sample test vector set, determine a scan chain distribution, where the scan chain distribution represents a scan chain used in the automatic vector test generation process among multiple scan chains;

Determine a register distribution based on the netlist data and the sample test vector set, the register distribution representing a register used in an automatic vector test generation process among a plurality of registers in a plurality of scan chains; and

Based on the scan chain distribution and the register distribution, the clock gate distribution and the clock control bit set are determined.