CN112698994A

CN112698994A - Partial bit stream read-back technology for FPGA internal resource test

Info

Publication number: CN112698994A
Application number: CN202011476600.7A
Authority: CN
Inventors: 阮爱武; 杜鹏; 杨胜江
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2020-12-15
Filing date: 2020-12-15
Publication date: 2021-04-23

Abstract

The invention belongs to the field of FPGA, and particularly relates to a partial bit stream read-back technology for testing internal resources of FPGA, which can improve the defects of the existing FPGA internal resource testing method. The method comprises the following steps: the test access interface controller is first reset setting the start frame address for read-back from which the bitstream read-back operation will start. Then setting the data length of the read-back for specifying the total frame number from the start frame address to the time of completing the read-back, and then setting the FPGA to be in a read-back state. After the setting is completed, the last step is to read and store the data from the FPGA configuration register chain for the FPGA test platform based on the partial bit stream read-back technology. The invention adopts the partial bit stream read-back technology, thereby not only ensuring the high efficiency of the FPGA internal resource test, but also having the universality and being capable of being transplanted to different series of FPGAs for the test of the FPGA internal resources.

Description

Partial bit stream read-back technology for FPGA internal resource test

Technical Field

The invention belongs to the field of Field Programmable Gate Array (FPGA) testing technology, and particularly relates to a partial bit stream read-back technology for testing internal resources of an FPGA.

Background

Fpga (field Programmable Gate arrays), a field Programmable Gate array, is an important member of digital circuits, and is widely used in the design and production of integrated circuits due to its abundant logic resources, repeated programmability and fast automatic development capability. However, as the integration level of the FPGA is continuously increased, the internal structure is more complicated, the interconnection resource network required to be constructed to achieve the flexible programmability is also more huge, and the failure occurrence rate of the internal resources is also increased. Therefore, FPGA internal resource testing techniques become increasingly critical.

Read-back (Readback) is a method of reading out data in the form of a bit stream from a value in a memory location inside a chip, which is similar to the reverse process of configuring an FPGA. The read-back is divided into read-back verification (Readback Verify) and read-back Capture (Readback Capture), and the read-back verification can read the current values in a configuration storage unit and a user storage unit (such as a lookup table, a shift register and a Block RAM) in the chip; the read-back trap is a complement to read-back verification and can read more the current state of all internal CLB and IOB registers. Bit stream data is arranged in a minimum unit of a frame in an FPGA configuration space, a plurality of frame data types such as a Center type, a gclk (global clk) type, a clb (configurable Logic Block) type, an iob (input Output Block) type, a Block RAM (hereinafter, referred to as BRAM) type, and the like exist in a chip configuration space, and the frame data types and the number of frames included in each frame data increase with the increase in the capacity of the FPGA array.

For testing internal resources of an FPGA, different FPGA testing technologies are proposed at present, including a conventional hardware testing method, an ATE (Automatic-Test-Equipment) -based testing method, a built-in Self-Test (BIST) -based testing method, and a read-back-based testing method. The traditional hardware test method is to design a corresponding test circuit based on the logic resource and structure of the FPGA, and to manually perform a plurality of test processes to complete the test. The test method based on ATE is a method for automatically completing the test by writing a test program and controlling the test program by a computer. The test method based on the BIST is to embed the BIST circuit on the basis of the original FPGA test circuit so as to complete the test. The test method based on readback (document a bitstream readback-based automatic functional test and diagnosis method for Xilinx FPGAs) is realized by reading the state value of the internal memory cell of the FPGA after configuration.

The FPGA internal resource testing method has certain limitations. The traditional hardware testing method needs to complete manual testing procedures for many times, and is long in time consumption and high in cost. Although the test method based on the ATE accelerates the test process, the ATE test equipment is very expensive and has limited storage space, which can affect the complete test of the FPGA. Although the test cost is reduced by the test method based on the BIST, the BIST circuit is embedded in the FPGA, so that the whole FPGA internal resource can be covered by a plurality of tests, and the BIST circuit needs to spend a lot of time for design, so the universality is not strong. However, the test method based on read-back has the disadvantages of long read-back time and low overall test efficiency. The limitations of these test methods are the main problems that the present invention solves.

The test platform realized based on the invention uses boundary scan technology, which is a technology that can obtain test response by writing data into the register modules near the input and output of the chip as test stimulus and reading the data in the register modules through the control bus. The boundary scan architecture is mainly composed of a Test Access Port Controller (TAP Controller), a boundary scan Register chain, an Instruction Register (IR), a Data Register (DR), and a BYPASS Register (BYPASS). The Test access interface (TAP) and boundary scan architecture are collectively referred to as JTAG (Joint Test Action group).

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides a partial bit stream read-back technology for testing the internal resources of an FPGA. The method can effectively save cost and time, and has strong portability and universality.

In order to achieve the purpose, the invention adopts the technical scheme that:

a partial bit stream read-back technology for testing FPGA internal resources aims at improving the read-back technology, and in the background technology, a plurality of frame data types exist in an FPGA chip configuration space, but the data types for FPGA testing only need a CLB type and a BRAM type, when the configuration bit stream is large, if the read-back technology is directly used for reading completely, the read-back time can be obviously increased, and the testing efficiency is influenced. The main principle of the partial bit stream read-back technology is to read back only the frame data of CLB type and BRAM type which are useful for FPGA test, and by reasonably setting the read-back starting frame address and the read-back frame number for them, the total amount of the read-back frame data can be obviously reduced, thereby greatly saving the read-back time, and the method comprises the following steps:

1) resetting the TAP controller after the FPGA configuration is finished, and then selecting an FPGA configuration register chain;

2) writing the initial address of the frame into a frame address register, and determining the position of the read-back initial frame, wherein the step is one of key points of a partial bit stream read-back technology, and if the set initial frame address is deviated backwards relative to a correct address, the state value of a partial register in a read-back result is lost; if the address is shifted forward relative to the correct address, the result of the analysis in the test system based on the partial bit stream read-back will be wrong;

3) writing the read-back data length into a frame data output register, starting a read-back function, which is the second key point of a partial bit stream read-back technology, and if the set length is improper, the read-back result can have serious consequences on an analysis module of a test system;

4) and finally, selecting the FPGA configuration register chain to prepare read-back data, and writing the read-back data into a file for storage for the FPGA test platform based on the partial bit stream read-back technology.

In the partial bit stream read-back technology, the position of the read-back start frame is determined in the step (2), based on the basic functional unit in the field programmable gate array, and in combination with the allocation of the internal configuration space of the FPGA after the configuration is completed, according to the arrangement sequence of the frame data in the internal space, the frame addresses required to be read back by functional units such as CLBs or BRAMs to be tested can be respectively calculated, and the obtained frame addresses are written into the frame address register.

In the partial bit stream read-back technology, the read-back data length is determined in the step (3), and similarly, the total amount of frame data of the CLB type and the BRAM type can be respectively counted according to the arrangement of the configuration frame data in the configuration space by combining the allocation of the configuration space in the FPGA after the configuration is completed, and then the counted result is respectively written into the frame data output register as the read-back data length of the frame data of the CLB type and the BRAM type.

The partial bit stream read-back technology, the FPGA test platform in the step (4), is constructed based on the partial bit stream read-back technology provided by the present invention. The test platform can directly carry out automatic test on the configured FPGA and mainly comprises a main program module, a partial bit stream read-back technology module, a read-back data analysis module and a fault diagnosis and positioning module.

The advantages of the invention mainly include:

1. the method has universality and portability, and can be suitable for testing internal resources of different series of FPGA;

2. the method is simple to realize, and can effectively save the cost;

3. the method of the invention adopts a partial bit stream read-back technology, which can effectively save read-back time and improve test efficiency.

Drawings

FIG. 1 is a general implementation framework of partial bitstream read-back technique

FIG. 2 is a JTAG boundary scan architecture

FIG. 3 is an overall structure of an FPGA test scheme constructed based on a partial bit stream read-back technology

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the present invention is further described in detail below with reference to the following specific drawings and embodiments:

the general implementation framework of the partial bitstream read-back technique proposed by the present invention is shown in fig. 1, and specifically includes the following contents:

firstly, after the FPGA configuration is finished, resetting the TAP controller, and then selecting the FPGA configuration register chain. Referring to fig. 2, a boundary scan architecture of JTAG is shown, in which all information (instructions, test data, and test results) exchanged with the outside of a chip based on the boundary scan technology is serially communicated, and the test instructions and the related test data are written into the chip in a serial manner, and then the execution results of the test instructions are read out from the chip in a serial manner.

And step two, writing the initial address of the frame into a frame address register, and determining the position of the read-back initial frame. A frame is the smallest unit of bit stream data information, and data of one frame is shifted into a frame data register in a word (32bit) format. The position of the start frame is determined to be one of key points of the realization of the partial bit stream read-back technology, the frame addresses of frame data of a CLB type and a BRAM type which need to be read back can be respectively calculated according to the arrangement sequence of data frames configured in the FPGA to be tested, and the addresses are written into a frame address register as the start frame addresses.

And step three, starting read-back, and writing the read-back data length into a frame data output register. Determining the length of the readback data is the second key point for realizing the partial bit stream readback technology, which needs to count the number of CLB type frame data and BRAM type frame data of FPGAs with different models and the number of frames contained in the two frame data types, and taking the statistical results as the respective readback data lengths of the CLB type frame data and the BRAM type frame data respectively.

And step four, selecting the FPGA configuration register chain to prepare readback data. And the TAP controller reads read-back bit stream Data from a TDO (test Data output) port by using a boundary scanning main program through state switching, wherein the read-back bit stream Data comprises frame Data only containing a CLB type and frame Data only containing a BRAM type, and the frame Data are written into a file to be stored for an FPGA test platform built based on a partial bit stream read-back technology.

The general scheme structure of the FPGA test platform based on the partial bit stream read-back technology mentioned in the fourth step is shown in fig. 3, and specifically includes the following contents:

1) the main program module is responsible for checking JTAG cable connection, detecting FPGA device model and controlling the function of the whole process. Before the test starts, the main program module will check the connection of JTAG cable, and will perform test initialization operation after the connection is correct, and then call the test excitation file and the subsequent flow.

2) The partial bitstream read-back technique module has been described in detail above. In the test platform, the partial bit stream read-back technology module mainly has the function of reading back data in the configured chip, writing the data into a file for storage, wherein the data comprises CLB type frame data and BRAM type frame data.

3) The read-back data analysis module is used for analyzing the data containing the FPGA state value into the state values corresponding to different registers of the FPGA after the partial bit stream read-back technology module is completed. The data is a hexadecimal string in which the status values are arranged in bits, and the status values are response values after excitation is applied in the FPGA test process. Corresponding results of the read-back data in the FPGA physical position can be obtained through the corresponding relation between each state value and different physical positions in the FPGA, so that read-back data analysis files are obtained, wherein the read-back data analysis files are a CLB type read-back data analysis file and a BRAM type read-back data analysis file respectively.

4) The fault diagnosis and positioning module compares the read-back data analysis file obtained in the step 3) with the fault diagnosis list so as to obtain a test result. The fault diagnosis list stores correct response values expected after excitation is applied in FPGA test, the correct response values are compared with a read-back data analysis file, if the correct response values different from the fault diagnosis list are found in the read-back data analysis file, the FPGA is indicated to have faults, fault positions can be positioned according to specific physical positions corresponding to registers with the different response values, and finally diagnosis and positioning results are respectively stored in a CLB type test result file and a BRAM type test result file, so that the test of the whole FPGA internal resource test platform based on partial bit stream read-back technology is completed.

The foregoing embodiments have fully described the essential technical content of the present invention, and those skilled in the art can implement the invention according to the description, so that other technical details are not described in detail.

The foregoing is a description of specific embodiments of the invention only, and any feature disclosed in this specification may be replaced by alternative features serving an equivalent or specific purpose unless expressly stated otherwise; all of the disclosed features, or all of the method or process steps, may be combined in any combination, except mutually exclusive features and/or steps.

Claims

1. A partial bit stream read-back technology for FPGA internal resource test is characterized in that after read-back preparation work is finished, the position of a read-back initial frame is determined; then determining the length of the read-back data and starting a read-back function; and finally, writing the read-back data into a file for storage, and using the file for an FPGA test platform based on a partial bit stream read-back technology.

2. The method for determining the position of the start frame as claimed in claim 1, wherein the frame addresses of the frame data of the CLB type and the BRAM type to be read back are calculated respectively according to the arrangement sequence of the spatial data frames configured in the FPGA to be tested, and the obtained addresses are written into the frame address register as the start frame addresses.

3. The method for determining the length of readback data according to claim 1, wherein the number of the CLB type frame data and BRAM type frame data of FPGAs of different models and the number of frames included in the two frame data types are counted, and the counted results are respectively used as the respective readback data lengths of the CLB type frame data and the BRAM type frame data.

4. The FPGA test platform based on partial bit stream readback technique of claim 1, wherein the FPGA test platform mainly comprises a main program module, a partial bit stream readback technique module, a readback data parsing module and a fault diagnosis and location module. The main program module is responsible for checking JTAG cable connection, detecting the model of an FPGA device and controlling the function of the whole process; the partial bit stream read-back technology module is responsible for reading back CLB type and BRAM type frame data in the configured chip; the read-back data analysis module is responsible for analyzing data obtained by the partial bit stream read-back technology module into state values corresponding to different registers of the FPGA and storing the state values in a read-back data analysis file; and the fault diagnosis and positioning module compares the read-back data analysis file with the fault diagnosis list file to obtain a test result finally.