CN113435152A

CN113435152A - Test vector automatic generation method based on scanning chain structure

Info

Publication number: CN113435152A
Application number: CN202110761997.2A
Authority: CN
Inventors: 钱静洁
Original assignee: Wuxi Jiuyi Semiconductor Technology Co ltd
Current assignee: Wuxi Jiuyi Semiconductor Technology Co ltd
Priority date: 2021-07-06
Filing date: 2021-07-06
Publication date: 2021-09-24

Abstract

The invention discloses a method for automatically generating a test vector based on a scan chain structure, which comprises the steps of reading a netlist of a digital chip, converting the netlist into a database comprising a gate table and a net table, and adding corresponding configuration to enable the digital chip to be in a test mode. Analyzing the netlist of the database format to obtain a complete fault table, selecting a fault in the fault table, calculating a test vector of the fault table, and compressing the test vector to judge whether all gate circuits are processed. The invention realizes the purpose of customizing specific test vectors for each chip by the Scan Chain Scan Chain inserted in the design in advance, and can quickly and fully automatically generate the test vectors, thereby effectively improving the coverage rate of digital logic in the chip testability design process.

Description

Test vector automatic generation method based on scanning chain structure

Technical Field

The invention belongs to the technical field of testing or measuring specially applied to the process of manufacturing or processing semiconductors, and particularly relates to an automatic generation method of a test vector based on a scan chain structure.

Background

The manufacturing process of the semiconductor chip is very complicated and needs to be carried out through hundreds of processes such as doping, oxidation, photoetching, metal interconnection and the like. At present, the advanced process of chip manufacturing has entered the 3nm mass production stage, and the chip needs to be manufactured on the size of one hundred thousand of hair diameter, so the process is very precise. If the product manufacturing defects are caused by dust particles, process deviation and other factors in the manufacturing process, the normal work cannot be realized, the manpower and material resources are wasted, even important business opportunities are delayed, and even serious consequences are caused.

Design for Test (DFT) is a Design technique in the field of integrated circuits, which implants special structures into the circuit at the Design stage for circuit testing after the Design is completed. By adding a design structure for testability, such as a Scan Chain (Scan Chain), a test engineer can monitor the transmission process of internal signals and timely find various faults, so as to prevent the damaged chip from flowing into the next stage and causing larger loss. The scan chain technology in the testability design can check whether the internal sequential circuit of the chip is normal in a short time, and is the mainstream technology in the field of chip testing at present.

In practice, a chip designer will formulate a specific test vector for testing functional completeness for a chip. Such test vectors can only test whether the chip is functioning properly, essentially testing the circuitry of the chip that is functionally related, but there is no way to achieve a hundred percent coverage of the circuitry of other parts of the chip. If a chip designer is required to write all test vectors, it is time consuming and not guaranteed that all digital logic in the chip can be tested.

Disclosure of Invention

Aiming at the problems in the prior art, the invention provides a method for testing each gate-level circuit in a chip by customizing a specific test vector for each chip through a scan chain inserted in the design in advance, so as to find the defects of each gate-level circuit in the chip and achieve higher coverage rate, and the process of generating the vector is completely automatic, does not need manual participation and has the obvious advantage of simple operation process.

In order to achieve the above object, the solution proposed by the present invention is a method for automatically generating a test vector based on a scan chain structure, which specifically comprises the following steps:

s1: reading a netlist of a digital chip and converting the netlist into a database, wherein the database comprises a gate table and a net table, each node of the gate table stores a name of the gate and a corresponding input/output pin, and each node of the net table stores the connected gate and a value to be set;

s2, adding corresponding configuration to make the digital chip in test mode;

s3: analyzing the netlist of the database format generated in the step 1 to obtain a complete fault table;

s4: selecting a fault in the fault table, wherein the fault type can be stuck-0 or stuck-1 or transition-0 or transition-1, and a client can automatically define the fault type through an interface according to the fault type to be detected;

s5: calculating the test vector of the fault in the step 4;

s6: compressing the test vector;

s7: judging whether all the gate circuits are processed completely, if not, returning to the step S4, and if so, exiting the program;

s8: and (6) ending.

In step 2, the configuration is that when the pin SE is 1, the chip is in a shift state, when the pin SE is 0, the chip is in a capture state, and the pin CLK is used for inputting clock pulses in the shift or capture state.

Step 3 specifically includes that each net in the netlist after the database transformation corresponds to two fault types, namely stuck at and transition, and the faults are sorted into a table to generate a complete fault table.

Step4 specifically includes selecting a fault from the fault table in step 3, and putting a D value of 1/0 or 0/1 in the fault table.

In order to enable the D value to be observed, a test vector needs to be generated, and the specific process is as follows: first, the gate through which D passes needs to be set to a corresponding value to ensure that D can be conducted to the output port or D terminal of the scan cell, and in order to generate this valid D value, the gate at which this fault is located also needs to be set to a corresponding value, and this process is continued until the input port driving this D value or Q terminal of the scan cell becomes the corresponding value.

If the input ports and the scanning units used by the two test vectors are not the same, the two test vectors are combined into a new test vector.

Preferably, the derivation algorithm in step S5 may be a D algorithm, a fan algorithm or a podem algorithm.

The derivation algorithm is based on the following two principles: i.e. whether the fault can be observed and whether the fault can be activated.

In step S6, in order to satisfy that a certain fault can be observed and activated, only a part of the input pins and scan chain cells need to be configured with fixed 0 or 1 values, and the values of the rest pins and scan chain cells can be any values.

Preferably, the ratio of the partial input pins to the scan chain units is 0.5% -2%.

Compared with the prior art, the invention has the following beneficial technical effects:

1, customizing a specific test vector for each chip by a scan chain inserted in design in advance;

2, test vectors can be generated quickly and fully automatically;

3, the digital logic in the chip can be covered as much as possible, and the coverage rate of 90-98% can be achieved, so that the yield of mass production is ensured.

Drawings

FIG. 1 is a circuit schematic of one embodiment of the present invention;

FIG. 2 is a circuit database corresponding to the circuit diagram of FIG. 1;

FIG. 3 is a diagram of test vector configuration;

FIG. 4 is a schematic diagram of a fault setup on a netlist;

FIG. 5 is a schematic diagram of a vector calculation process using the D algorithm;

FIG. 6 is a schematic illustration of two vector combinations;

FIG. 7 is a flowchart of a method for automatically generating test vectors according to the present invention.

Detailed Description

The present invention will now be described in further detail with reference to the accompanying drawings.

The invention uses the multi-branch tree structure to realize the datamation of the digital netlist, and the digital netlist is formed by the interconnection and combination of a plurality of gate-level circuits. Wherein the gate level circuit includes: AND, OR, NAND, NOR, BUF, INV, OR, XOR, MUX, DFF, Latch. The gate level circuit forms a gate, and the connection between the gate and the gate is realized through net. In order for the computer to process these gates and nets, the present invention uses a multi-way tree structure to store the information of these gates and nets for the purpose of allowing the computer to solve these physical connections. For example, it can be seen that there are two driven nets, input pin A and net N4, via gate U1, while net N4 is driven by gate U7 and U7 is driven by net N3. By repeatedly searching for the gate and the net, the method can find out the connection relation of the whole circuit and provide circuit connection information for subsequent vector calculation.

The derivation algorithm can be a D algorithm, a fan algorithm or a podem algorithm, and the basic principle of algorithm derivation is two, namely a principle one: whether this fault can be observed; principle two whether this fault can be activated; the remaining circuit values are derived accordingly to satisfy these two points.

The flow chart of the automatic test vector generation method of the invention is shown in FIG. 7, and comprises the following steps:

and Step 1, reading the digital chip netlist into a database which can be processed by software. The database records gate, net and connection relation between them in the netlist;

step 2. there are several pin pins for configuration status in the chip for testing. When pin SE is 1, the chip belongs to the shift state. When pin SE is 0, the chip belongs to capture state. The Pin CLK is used for inputting a clock pulse in a shift or capture state. When the method is used for generating the test vector, the configuration is required to be added to the netlist after the datamation so as to enable the netlist to be in a test mode;

step 3, for the netlist after the database transformation, for each net, two faults are corresponded. The fault types include stuck at and transition. The faults are arranged into a table so as to be convenient for subsequent programs to operate the faults;

step4, selecting a fault from the fault tables in Step 3 by the method, and putting 1/0(stuck-at 0fault) or 0/1(stuck-at1 fault) which is the D value plug-in fault (fault) on the fault; it should be noted that the fault type here may also be transition-0 or transition-1, and the client may define itself according to the fault type to be detected, and this method will provide an interface for the client to define the fault type. For example, a stuck-at 0fault needs to be detected, and this D value needs to be put 1/0 at this fault point and inserted on the corresponding net in the database generated in step 1;

step 5. in order to make D value observed, the gate passed by D needs to be set to a corresponding value to ensure that D can be conducted to the output pin or D end of the SCAN CELL (SCAN CELL). At the same time, in order to generate the valid D value, the gate of the fault is also set to the corresponding value, and the process is continued until the input pin driving the D value or the Q terminal of the scan cell is set to the corresponding value. This process is a process of test vector generation;

step 6, generally, only 0.5% -2% of the input pin pins or the Q terminals of the scan units in a test vector need to be set to valid values, and the values of the other input pin pins or the scan units can be any values. By utilizing the characteristic, if the input pin foot and the scanning unit used by the two test vectors are different, the two vectors can be merged into a new vector, and the new vector can simultaneously detect the fault of the original two vector target detection (target), so that the number of the test vectors can be reduced, but the coverage rate of the test can be ensured not to be influenced;

step 7, repeating the process Step4-6 until all faults (fault) have been processed;

and Step 8, exiting the program.

The following examples are now provided to facilitate a better understanding of the concepts of the present invention by those skilled in the art. The present embodiment is directed to the circuit shown in fig. 1, which includes 9 gates, i.e., an AND, an OR, an Inverter, five buffers, AND a scan cell. Wherein U1, U2, U3, U4, U5, U6, U7, U8, sdff0 are the names of these gates, respectively. N1, N2, N3, N4, N5, N6, N7, N8 are the names of nets for connecting these gate pins. A, B, SI, SE, CLK is the name of an input port. SO is the name of the output port (output port).

According to the flow chart of the automatic test vector generation method shown in fig. 7, the following steps are respectively executed:

step 1, reading the netlist of the circuit, storing the gates and the connection relation into a database shown in fig. 2, wherein the database has a gate table, and each node stores a gate name and a corresponding input/output pin net;

step 2, dividing each test vector into 3 windows, namely shift in, capture and shift out. SE needs to be configured to be 1 when the vector is in shift in and shift out window, and to be 0 when the vector is in capture window. Meanwhile, clock port CLK needs to have pulse, CLK needs to be pulse 1 time at capture window if tested fault is stuck at, and needs to be pulse 2 time at least at capture window if tested fault is transition. The number of times of clock pulses required for Shift in and Shift out is determined by the length of the scan chain. In this embodiment, since the scan chain length is 1, the pulse is only needed once (as shown in fig. 3);

step 3: taking stuck at fault as an example only. The circuit has 8 nets and 6 ports, each of which has 2 faults and two faults, for example net N8. As shown in fig. 4, there are two faults of SA0 and SA1 on N8;

step 4: in the present embodiment, SA0 on N8 is taken as an example, as shown in fig. 5. SA0 needs to be tested, 1/0 on N8 represents that the fault needs to be tested, N8 needs a value of 1 for a target, and if the fault exists, the actually displayed value of the fault is 0;

step 5 As shown in FIG. 6, in order to set the target value of N8 to 1, it is necessary to set the values of N4 and A to 1. In order to observe 1/0 of N8, N1 needs to be set to 0, and it is inferred that B needs to be set to 1. Since the value of N4 can be controlled by N3 shift in value connected to sdff 0Q pin, the value of SI needs to be set to 1. And the final fault detected will be reflected on N2. The value of N2 can be observed by the action of shift out being output to SO. The whole speculation process is automatically set by software, and a user only needs to define the behaviors of the SE and the clock.

Step 6, the real circuit has tens to hundreds of input ports and output ports, and the length of the Scan Chain (Scan Chain) can reach millions. Each fault only needs 0.5% -2% of input ports and scan cells to set corresponding values, and in order to reduce the number of vectors (patterns), the patterns can be combined into a valid pattern, that is, 10 patterns may be needed to test 10 target faults. However, since the input port and scan cell needed between these patterns are different, these patterns can be merged, and this process is compression. Usually, in order to satisfy the condition that a certain fault can be observed and excited, only 0.5% -2% of input pins and scan chain units need to be configured with fixed 0 or 1 values, and the values of a large number of pins and scan chain units are left to be any values, which provides a good theoretical condition for vector compression; for example, there are 5 vectors, the input pins and scan chain units to be configured are different from each other, they can be combined into one vector, and a plurality of faults can be detected simultaneously, and the test cost can be reduced due to the reduction of the number of vectors.

Step 7, the above example only selects SA0 of N8 as the target fault, and next can select SA1 of N8, and also can select SA0 or SA1 of other nets. These steps of step4-6 are repeated.

Step 8: if all the faults have been processed, the routine may exit.

The invention realizes the purpose of customizing specific test vectors for each chip by the Scan Chain Scan Chain inserted in the design in advance, and can quickly and fully automatically generate the test vectors, thereby covering the digital logic in the chip as much as possible. The specific coverage rate is determined by the structure of the chip, and the invention can reach 98% coverage rate under ideal conditions, thereby effectively ensuring the yield of the chip in mass production.

It should be understood that the above description of specific embodiments is not intended to limit the invention, and any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. The method for automatically generating the test vector based on the scanning chain structure is characterized by comprising the following steps of:

s2, adding corresponding configuration to make the digital chip in test mode;

s5: calculating the test vector of the fault in the step 4;

s6: compressing the test vector;

s8: and (6) ending.

2. The method according to claim 1, wherein in step 2, the configuration is such that the chip is in a shift state when the pin SE is 1, the chip is in a capture state when the pin SE is 0, and the pin CLK is used to input a clock pulse in the shift or capture state.

3. The method according to claim 1, wherein step 3 comprises associating two failure types, stuck at and transition, with each net in the databased netlist, and sorting the failures into a table to generate a complete failure table.

4. The method of claim 1, wherein step4 comprises selecting a fault from the fault table of step 3, and placing 1/0 or 0/1D values in the fault table.

5. The method according to claim 4, wherein the test vector is generated to enable the D value to be observed, the method comprises: first, the gate through which D passes needs to be set to a corresponding value to ensure that D can be conducted to the output port or D terminal of the scan cell, and in order to generate this valid D value, the gate at which this fault is located also needs to be set to a corresponding value, and this process is continued until the input port driving this D value or Q terminal of the scan cell becomes the corresponding value.

6. The method of claim 5, wherein if the input port and the scan cell used by two test vectors are not the same, then combining them into a new test vector.

7. The method according to claim 1, wherein the derivation algorithm in step S5 is selected from a D algorithm, a fan algorithm, or a podem algorithm.

8. The method of claim 7, wherein the deriving is based on two principles: whether the fault can be observed and whether the fault can be activated.

9. The method according to claim 1, wherein in step S6, in order to satisfy a certain fault being observed and being activated, only some of the input pins and scan chain cells need to be configured with fixed 0 or 1 values, and the values of the other pins and scan chain cells can be any values.

10. The method according to claim 1, wherein the ratio of the partial input pins to the scan chain units is 0.5% -2%.