JP4899927B2 - Test pattern automatic generation method and test pattern automatic generation program - Google Patents

Description

  The present invention relates to a test pattern automatic generation method and a test pattern automatic generation program for automatically generating a test pattern used when a ROM (read only memory) mixed LSI is tested by an LSI (large scale integrated circuit) tester.

  An ATPG (automatic test pattern generator) that automatically generates a test pattern used when testing an LSI with an LSI tester is required to generate a test pattern with a high failure detection rate at high speed. The ATPG that automatically generates a scan-designed LSI test pattern handles a gate-level netlist as circuit information, but there are only a few gate types, such as AND gates and OR gates, and the operation is simple. Therefore, the process for automatic test pattern generation can be performed at high speed.

  For example, in the case of the 2-input AND gate shown in FIG. 5, when “0” is obtained for the output pin w, “0” is set to either the input pin a or b, and “0” is set to the output pin w. In order to obtain “1”, it is sufficient to incorporate a process of setting “1” in both the input pins a and b into the program. Even if the number of input pins is three or more, since each input pin has the same function, the processing burden is not great.

  However, in the case of the ROM, the operation is determined by the signal value set in the memory cell. Therefore, when the test pattern of the ROM mixed LSI is automatically generated, the ROM is a set of signal values set in the memory cell. Handling as a truth table leads to an increase in test pattern generation time.

  FIG. 6 shows an example of a ROM. ADR0 to ADR6 are address pins, and DO0 to DO7 are output data pins. In the case of this ROM, since the number of addresses is 128, a signal value of 128 × 8 bits is set. Here, for example, when “0” is obtained for the output data pin DO0, it is necessary to look at the truth table of the ROM and find the signal value of the address pins ADR0 to ADR6 where the output data pin DO0 is “0”. is there. This process becomes more burdensome on the ATPG as the number of address pins increases.

  Therefore, for a ROM mixed LSI, a method of generating a test pattern that treats the ROM as not subject to a stuck-at fault or a delay fault may be used. However, in this case, a stuck-at fault in the ROM pin or a delay fault in the path passing through the ROM cannot be detected.

  Therefore, for ROM mixed LSIs, a method of automatically generating test patterns with ATPG by replacing ROM with a combinational circuit that uses AND gates, OR gates, NAND gates and NOR gates as needed is used. Sometimes. In this method, verification of a test pattern generated by ATPG is performed using an original netlist.

  FIG. 7 is a flowchart showing a conventional method for automatically generating a test pattern of a ROM mixed LSI by ATPG by replacing the ROM with a combinational circuit. In this example, first, layout processing is performed by the CPU and the layout program based on the gate-level netlist 1 of the ROM-embedded LSI whose ROM is shown in the truth table, and delay information 2 is created (step P1).

  Next, the netlist 1 is input, and the CPU and ATPG replace the ROM shown in the truth table with a combinational circuit that uses AND gates, OR gates, NAND gates, and NOR gates as necessary. Then, the net list 1 is converted into a gate level net list 3 for ATPG (step P2). Next, based on the ATPG netlist 3, the CPU and ATPG generate a test pattern 4 consisting only of signal values of the input / output pins (step P3).

  Next, based on the test pattern 4 and the timing definition file 5 consisting only of the signal values of the input / output pins, the test pattern 6 having the signal values of the input / output pins and the timing description is generated by the CPU and ATPG (step P4). . Next, the test pattern 6 is verified by the CPU and the test pattern verification program based on the netlist 1 and the delay information 2 (step P5).

  8A and 8B are diagrams for explaining the advantages of the conventional test pattern automatic generation method shown in FIG. 7, in which FIG. 8A shows a part of a ROM mixed LSI indicated by the netlist 1, and FIG. 8B shows an ATPG net. A part of the ROM mixed LSI shown in the list 3 is shown. In FIG. 8, 11 is a ROM mixed LSI, 12 is a ROM, 13, 14 and 15 are AND gates, 16 and 17 are scan flip-flops, and ROM 12 is shown as a truth table in the netlist 1 and is used for ATPG. In the net list 3, the combinational circuit including AND gates 14 and 15 is shown.

According to the conventional test pattern automatic generation method shown in FIG. 7, since the ROM 12 is indicated by a combinational circuit in the ATPG netlist 3, a net stuck-at fault between the output pin of the AND gate 13 and the address pin of the ROM 12 A test pattern for detection and a test pattern for detecting a delay fault between the scan flip-flops 16 and 17 can be automatically generated.
Japanese Patent Laid-Open No. 03-029868

  By the way, when verifying the test pattern 6 created by the ATPG with the original netlist 1, the output signal is determined using the truth table of the ROM. For the ROM, any one of the address pins is used. There is a condition that the signal values of all the output data pins must be indefinite values if the signal value becomes an indefinite value (a state in which neither “0” nor “1” can be said).

  Here, for example, when the ROM shown in FIG. 6 is mounted on the ROM mixed LSI, all the signals of the output data pins DO0 to DO7 are affected by all the seven signals of the address pins ADR0 to ADR6. Not necessarily. For example, if the signal value of the output data pin DO0 is the same signal value regardless of whether the signal value of the address pin ADR0 is “0” or “1”, the signal value of the output data pin DO0 includes the address pin ADR0 will not be involved.

  In such a case, in the ATPG netlist 3 after the ROM shown in FIG. 6 is replaced with a combinational circuit, the address pin ADR0 is not included in the input tree of the output data pin DO0. Therefore, even if the signal value of the address pin ADR0 becomes an indefinite value, the ATPG generates a test pattern on the assumption that “0” or “1” is output to the output data pin DO0.

  As described above, in the conventional test pattern automatic generation method shown in FIG. 7, the test pattern 6 generated by ATPG does not satisfy the test pattern verification condition using the original netlist 1, and the test pattern verification is performed. There has been a problem that strobe errors may occur in the process (step P5).

  In view of this point, the present invention provides a test pattern generated in an original netlist even when a test pattern for a ROM mixed LSI is generated using an automatic test pattern generation tool that handles a gate-level netlist. To provide a test pattern automatic generation method and a test pattern automatic generation program that can satisfy a test pattern verification condition using a test pattern and prevent a strobe error from occurring in a test pattern verification process using an original netlist With the goal.

  According to the test pattern automatic generation method of the present invention, the CPU uses a second test pattern automatic generation tool for a gate-level netlist as a gate-level netlist of a ROM mixed LSI in which a ROM is represented by a truth table. A netlist conversion step for converting to a netlist, and a test pattern generation step for generating a test pattern for the ROM mixed LSI by the CPU and the test pattern automatic generation tool based on the second netlist and the timing definition file The netlist conversion step includes a combination circuit that satisfies the truth table, and a total output when any of the signal values of the address pins is an indefinite value. Indeterminate value generation with indeterminate value generation circuit that sets the signal value of the data pin to an indeterminate value It is intended to include the step of replacing the road with ROM.

  The test pattern automatic generation program of the present invention is a second test pattern automatic generation tool for handling a gate-level netlist as a gate-level netlist of a ROM mixed LSI in which a ROM is indicated by a truth table. A netlist conversion step for converting to a netlist, and a test pattern generation step for generating a test pattern for the ROM mixed LSI using the test pattern automatic generation tool based on the second netlist and the timing definition file A test pattern automatic generation program including a program for executing the program, wherein in the netlist conversion step, the ROM, the combinational circuit that satisfies the truth table, and the signal value of any of the address pins are indefinite values Is an indeterminate value generator that sets the signal values of all output data pins to indeterminate values. It is intended to include the step of replacing the undefined value generating circuit with ROM having a circuit.

  According to the present invention, in the net list conversion step, the ROM makes the signal values of all output data pins undefined when the combinational circuit satisfying the truth table and the signal value of any of the address pins are undefined. It is replaced with a ROM with an indeterminate value generation circuit having an indeterminate value generation circuit for setting the value. Therefore, even when a test pattern for a ROM mixed LSI is generated using a test pattern automatic generation tool that handles a gate level netlist, the test pattern generated is a test using the original first netlist. By satisfying the pattern verification condition, it is possible to prevent a strobe error from occurring in the test pattern verification process using the original first netlist.

  FIG. 1 is a flowchart showing an embodiment of a test pattern automatic generation method of the present invention. The test pattern automatic generation method of the present invention is executed using a computer. In one embodiment of the test pattern automatic generation method of the present invention, first, layout processing is performed by a CPU and a layout program based on a gate-level netlist 21 of a ROM-embedded LSI in which a ROM is indicated by a truth table, and delay information is obtained. 22 is created (step S1).

  Next, the netlist 21 is inputted, and the ROM in the ROM mixed LSI is made to satisfy the truth table of the ROM by the netlist conversion processing program improved from the conventional netlist conversion program in the CPU and ATPG. In addition, when a combinational circuit configured using an AND gate, an OR gate, a NAND gate, and a NOR gate as needed and any of the signal values of the address pins are indefinite values, the signal values of all output data pins Is replaced with a ROM with an indefinite value generation circuit having an indefinite value generation circuit for setting an indefinite value, thereby converting the net list 21 into an ATPG net list 23 (step S2).

  As described above, the ATPG used in one embodiment of the test pattern automatic generation method of the present invention uses an AND gate as a netlist conversion program so that the ROM in the ROM mixed LSI can satisfy the truth table of the ROM. When the signal value of any one of the address circuit and the combinational circuit configured using the OR gate, NAND gate and NOR gate as necessary is an indefinite value, the signal values of all output data pins are set to an indeterminate value. It has a net list conversion program for converting the net list 21 into the ATPG net list 23 by replacing it with a ROM with an indefinite value generation circuit having an indefinite value generation circuit to be set.

  Next, based on the ATPG net list 23, the CPU and ATPG generate a test pattern 24 consisting only of signal values of the input / output pins (step S3). Next, based on the test pattern 24 and the timing definition file 25 consisting only of the signal values of the input / output pins, the test pattern 26 having the signal values of the input / output pins and the timing description is generated by the CPU and ATPG (step S4). . Next, based on the original net list 21 and the delay information 22, the test pattern 26 is verified by the CPU and the test pattern verification program (step S5).

  Here, the indeterminate value generation circuit generated in the net list conversion step (step S2) is provided between the ROM address pin and the output data pin, and has, for example, the same number of input terminals as the address pins, and the signal value of the address pins. A first-stage exclusive OR gate (hereinafter referred to as an XOR gate) and a two-input second-stage where the first and second input terminals are connected to the output terminal of the first-stage XOR gate. An XOR gate is provided corresponding to each output terminal of the combinational circuit that satisfies the truth table of the ROM, the first input terminal is connected to the output terminal of the second-stage XOR gate, and the second input terminal is connected It is constituted by a 2-input third-stage exclusive OR gate connected to the corresponding output terminal of the combinational circuit that satisfies the ROM truth table.

  2A and 2B are diagrams for explaining a configuration example of an indefinite value generation circuit. FIG. 2A shows a part of a ROM mixed LSI indicated by the netlist 21, and FIG. 2B shows a ROM mixed indicated by an ATPG netlist 23. 2 shows a ROM with an indeterminate value generation circuit in an LSI. In FIG. 2, 31 is a ROM mixed LSI, 32 is a ROM, ADR 0 to ADR 2 are address pins of the ROM 32, DO 0 to DO 2 are output data pins of the ROM 32, and 33 is a ROM with an indefinite value generating circuit formed by replacing the ROM 32. To which an indefinite value generation circuit 34 is added. The ROM 32 is indicated by a truth table in the net list 21, and the ATPG net list 23 is indicated by a combinational circuit that includes AND gates 35 and 36 and the like and satisfies the truth value table of the ROM 32.

  In the example of FIG. 2, the indeterminate value generation circuit 34 is provided between the address pins ADR0 to ADR2 and the output data pins DO0 to DO2, and includes a three-input XOR gate 37 and two-input XOR gates 38 to 41. Has been. The XOR gate 37 has a first input terminal a connected to the address pin ADR0, a second input terminal b connected to the address pin ADR1, and a third input terminal c connected to the address pin ADR2. The second-stage XOR gate 38 connects the first input terminal a and the second input terminal b to the output terminal w of the XOR gate 37.

  The XOR gate 39 connects the first input terminal a to the output terminal w of the XOR gate 38, connects the second input terminal b to the output terminal 42-0 of the ROM 32, and connects the output terminal w to the output data pin DO0. Connected. The XOR gate 40 connects the first input terminal a to the output terminal w of the XOR gate 38, connects the second input terminal b to the output terminal 42-1 of the ROM 32, and connects the output terminal w to the output data pin DO1. Connected. The XOR gate 41 connects the first input terminal a to the output terminal w of the XOR gate 38, connects the second input terminal b to the output terminal 42-2 of the ROM 32, and connects the output terminal w to the output data pin DO2. Connected.

  3A and 3B are diagrams for explaining the operation of the indefinite value generation circuit 34. FIG. 3A is a truth table of the first-stage XOR gate 37, and FIG. 3B is a second-stage and third-stage XOR gate 38. The truth table of -41 is shown. X represents an indefinite value and Z represents a high impedance state. Here, when the signal values of the address pins ADR0, ADR1, and ADR2 are “000” or “111”, the output value of the first-stage XOR gate 37 = “0” and the output of the second-stage XOR gate 38 The value = “0”, and the third-stage XOR gates 39, 40, and 41 function as buffers for signals output to the output terminals 42-0, 42-1, and 42-2 of the ROM 32.

  When the signal values of the address pins ADR0, ADR1, and ADR2 are definite values other than “000” or “111”, the output value of the first-stage XOR gate 37 = “1” and the second-stage XOR gate The output value of 38 becomes “0”, and the third-stage XOR gates 39, 40, 41 function as buffers for signals output to the output terminals 42-0, 42-1, 42-2 of the ROM 32. .

  On the other hand, when any of the signal values of the address pins ADR0, ADR1, and ADR2 is an indefinite value X, the output value of the first-stage XOR gate 37 = the indefinite value X, the second-stage XOR gate 38 The output value = undefined value X, and the output values of the third-stage XOR gates 39, 40, 41 all become the undefined value X. Therefore, even when the test pattern 26 of the ROM mixed LSI is generated using ATPG, which is a test pattern automatic generation tool that handles the gate level netlist, the generated test pattern 26 is the original netlist 21. This satisfies the test pattern verification condition using.

  FIG. 4 is a diagram showing a computer for carrying out one embodiment of the test pattern automatic generation method of the present invention. In FIG. 4, 51 is a CPU, 52 is a memory used by the CPU 51 for calculation, 53 is an input device, 54 is a display device, 55 is an external memory, and the external memory 55 is one of the test pattern automatic generation methods of the present invention. Storage of a layout program 56, a netlist conversion program 57, test pattern generation programs 58 and 59, and a test pattern verification program 60 constituting an embodiment of an automatic test pattern generation program of the present invention for executing the embodiment, and a netlist 21, delay information 22, ATPG netlist 23, test pattern 24, timing definition file 25, and test pattern 26.

  The layout program 56 is for causing the CPU 51 to function as a layout processing means to execute step S1. The net list conversion program 57 is for causing the CPU 51 to function as a net list conversion means and to execute step S2. The test pattern generation program 58 is for causing the CPU 51 to function as test pattern generation means to execute step S3. The test pattern generation program 59 is for causing the CPU 51 to function as a test pattern generation unit to execute step S4. The test pattern verification program 60 is for causing the CPU 51 to function as a test pattern verification unit to execute step S5.

  As described above, according to the embodiment of the test pattern generation method of the present invention, the ATPG allows the ROM in the ROM mixed LSI to perform the AND gate, OR gate, NAND operation so as to satisfy the truth table of the ROM. Indeterminate value generation that sets the signal values of all output data pins to indefinite values when the combinational circuit is configured using gates and NOR gates as needed, and the signal value of any of the address pins is indefinite The net list 21 is converted into an ATPG net list 23 by replacing it with a ROM with an indeterminate value generation circuit having a circuit (step S2).

  Therefore, even when the test pattern 26 is generated using the ATPG which is a test pattern automatic generation tool for handling the gate level netlist, the generated test pattern 26 uses the original netlist 21. By satisfying the verification condition, it is possible to prevent a strobe error from occurring in the test pattern verification process using the original netlist 21.

It is a flowchart which shows one Embodiment of the test pattern automatic generation method of this invention. It is a figure for demonstrating the structural example of the indefinite value generation circuit produced | generated at the net list conversion process of one Embodiment of the test pattern automatic generation method of this invention. It is a figure for demonstrating operation | movement of the indefinite value generation circuit produced | generated by one Embodiment of the test pattern automatic generation method of this invention. It is a figure which shows the computer for implementing one Embodiment of the test pattern automatic generation method of this invention. It is a figure which shows an example of an AND gate. It is a figure which shows an example of ROM. It is a flowchart which shows the conventional method which replaces ROM with a combinational circuit and automatically produces | generates the test pattern of ROM mixed LSI by ATPG. It is a figure for demonstrating the advantage of the conventional test pattern automatic generation method shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Net list 2 ... Delay information 3 ... Net list for ATPG 4 ... Test pattern 5 ... Timing definition file 6 ... Test pattern 11 ... ROM mixed LSI
12 ... ROM
13, 14, 15 ... AND gate 16, 17 ... Scan flip-flop 21 ... Net list 22 ... Delay information 23 ... Net list for ATPG 24 ... Test pattern 25 ... Timing definition file 26 ... Test pattern 31 ... ROM mixed LSI
32 ... ROM
33 ... ROM with indeterminate value generation circuit
34: Undefined value generation circuit 35, 36 ... AND gate 37-41 ... Exclusive OR gate (XOR gate)
51 ... CPU
52 ... Memory 53 ... Input device 54 ... Display device 55 ... External memory 56 ... Layout program 57 ... Netlist conversion program 58, 59 ... Test pattern generation program 60 ... Test pattern verification program

Claims (2)

A netlist conversion step of converting, by the CPU, a gate-level first netlist of a ROM mixed LSI whose ROM is shown in a truth table into a second netlist for a test pattern automatic generation tool for handling a gate-level netlist; ,
A test pattern automatic generation method including a test pattern generation step of generating a test pattern of the ROM mixed LSI by the CPU and the test pattern automatic generation tool based on the second netlist and the timing definition file,
In the netlist conversion step, when the signal value of any of the combinational circuit that satisfies the truth table and the address pin is an indefinite value, the ROM sets the signal values of all output data pins to an indefinite value. a step of replacing the undefined value generating circuit with ROM having an indefinite value generating circuit seen including,
The indefinite value generating circuit is:
A first-stage exclusive OR gate that has the same number of input terminals as the address pins and inputs the signal values of the address pins in parallel;
A 2-input second-stage exclusive OR gate having first and second input terminals connected to an output terminal of the first-stage exclusive-OR gate;
The first input terminal is provided corresponding to each output terminal of the combinational circuit, the first input terminal is connected to the output terminal of the second-stage exclusive OR gate, and the second input terminal is a corresponding output of the combinational circuit. features and to ruthenate strike pattern automatically generating method in that it comprises an exclusive OR gate of the third stage of the two-input connected to the terminal. A netlist conversion step for converting into a computer a second netlist for a test pattern automatic generation tool for handling a gate-level netlist; Automatic test pattern generation including a program for executing a test pattern generation process for generating a test pattern of the ROM mixed LSI using the test pattern automatic generation tool based on the second netlist and the timing definition file A program,
In the netlist conversion step, when the signal value of any of the combinational circuit that satisfies the truth table and the address pin is an indefinite value, the ROM sets the signal values of all output data pins to an indefinite value. a step of replacing the undefined value generating circuit with ROM having an indefinite value generating circuit seen including,
The indefinite value generating circuit is:
A first-stage exclusive OR gate that has the same number of input terminals as the address pins and inputs the signal values of the address pins in parallel;
A 2-input second-stage exclusive OR gate having first and second input terminals connected to an output terminal of the first-stage exclusive-OR gate;
The first input terminal is provided corresponding to each output terminal of the combinational circuit, the first input terminal is connected to the output terminal of the second-stage exclusive OR gate, and the second input terminal is a corresponding output of the combinational circuit. features and to ruthenate strike pattern automatically generated program in that it comprises an exclusive OR gate of the third stage of the two-input connected to the terminal.

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