JP2007257440A - Logic equivalence verification method and pseudo logic circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the following problem: when a black-boxed circuit is present when setting of a fixed value signal is required in logic equivalence verification, and before and after test composition because the fixed value signal does not propagate in the black-boxed circuit, the logic equivalence verification of a succeeding circuit of the black-boxed circuit cannot be performed. <P>SOLUTION: This logic equivalence verification method uses: a first step for deciding an input terminal not affecting output; a second step for deciding connection with external input wherein the signal is set to a fixed value; a third step for black-boxing a target cell for reading a description file not having designation of a user or a function block; and a fourth step for replacing the target cell with a pseudo logic circuit that is a verification point in the logic equivalence verification, affecting succeeding logic of the target cell. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a logic equivalence verification method for verifying logic equivalence between two circuits, and a pseudo logic circuit.

  In the development of integrated circuits, it is important that no errors be introduced into the logic design during the design process. Therefore, it is verified whether or not the logical design has been correctly performed before the final integrated circuit is designed. In a large-scale integrated circuit design, the number of man-hours for logic verification is increasing, and the logic verification process may occupy half of the total man-hours for design. In logic verification in the design of a large scale integrated circuit (LSI) having millions of gates in recent years, the logic verification tool is required to have higher speed and higher reliability.

  Such logic verification is necessary for logic specifications such as insertion of a test scan circuit (Design For Testability, hereinafter referred to as DFT circuit) for performing signal timing adjustment and manufacturing test regarding the number of gates, delay time, and the like. This is a case where the realization configuration of the logic circuit is changed without changing. In addition, there are logic synthesis, optimization, layout design, and ECO (Engineering ChangeOrder). Such a change in the circuit configuration is called an implementation process, and there is a high possibility that the logic is changed by this implementation process. Therefore, it is verified whether the logic of the logic circuit called “Specification” before the implementation process matches the logic of the logic circuit called “Implementation” after the implementation process to improve the quality of the logic design. It has been broken. A technique for realizing such verification is called a logical equivalence verification technique, which is one of the techniques using CAD (Computer Aided design) (see, for example, Patent Document 1).

  Incidentally, the logic design of LSI is generally performed using HDL (Hardware Description Language). Then, an RTL (Register Transfer Level) description of a desired circuit configuration is performed using the HDL, and then the RTL description is logically synthesized to convert it into a gate level netlist. This RTL description expresses a structure constructed by registers such as latches and flip-flops and combinational circuits that realize specific functions in between. A netlist is a logical structure expressed by a logical expression of a gate element. In the logical equivalence verification, such logical data is compared before and after the implementation process.

  In the logical comparison of two LSIs, the LSI is divided into basic units of logical equivalence verification called logic cones, and verification is repeated to check whether the logics of the corresponding logic cones of the two LSIs match. It is executed by. In general, by dividing a circuit into registers, etc., and dividing it into logic cones composed only of combinational logic, it is mathematically determined whether the logics of the two logic cones to be verified are equivalent. Validate. The apex of this logic cone is a point where signals can be easily cut out, such as flip-flops, latches, external outputs, black box module input terminals, and cut points. The vertex of this logic cone becomes a verification point, and the comparison of the logics of the back-traced logic cones from the verification point to the previous verification point is performed by, for example, BDD (Binary Decision Diagram) method, ATPG (Automatic Test Pattern Generation) method, And a combination of the BDD method and the ATPG method (see, for example, Non-Patent Documents 1, 2, and 3).

  However, in such logic equivalence verification, even if it is determined that the logics of the two circuits are equivalent, the circuit operation and the LSI timing are not guaranteed to be correct. Logical equivalence verification is verification that provides assurance that two circuits are logically equivalent.

By the way, in the system LSI, when the logical equivalence verification of the circuit including the interface circuit is performed, a cell library corresponding to the interface circuit to be used is used. However, in the interface circuit, there are many open parts where dummy logic is described or subsequent logic is not described.
Also, behavioral descriptions, analog macros, and the like, which are descriptions of the operation level of the system LSI, cannot be expressed digitally, so formal logical equivalence verification such as the BDD method and ATPG method cannot be applied. There are also modules such as RAM that do not require logic verification.

  As described above, the logic connected to the interface circuit and the module not to be tested cannot be verified because the verification point is not set. Therefore, such a portion is made a black box by reading a description file having no user specification or function block instead of an actual file. Since the black box portion is a verification point, logic verification can be performed even for logic connected to an interface circuit or a module not to be inspected.

  In addition, since a circuit that does not affect the output signal does not need to be verified, it is normally excluded from the inspection target.

  In the LSI design flow, logical equivalence verification is performed when a partial circuit change such as the insertion of the DFT circuit described above or layout is performed. Here, the layout is a netlist arranged in the form of an actual integrated circuit, and in most cases, the efficiency of arrangement of elements and wiring is also taken into consideration.

  For example, such verification before and after inserting a DFT circuit is called a system mode in which a fixed value is set for an external input signal in order to verify logic equivalence without considering the inserted DFT circuit. It is common to verify the logic in the state.

  The insertion of the DFT circuit will be described with reference to FIG. FIG. 1A shows a synchronous flip-flop (hereinafter referred to as FF) 10a. FIG. 1B shows an FF 10b in which a DFT circuit is inserted into the FF of FIG.

The FF 10a in FIG. 1A outputs the signal input to DATA to QUIT in synchronization with the timing of the signal input to CLOCK.
The FF 10b in FIG. 1B is provided with SCANIN and SCANMODE as input terminals and SCANOUT as an output terminal with respect to the FF 10a in FIG. DATA and SCANIN are connected to the selector 11. DATA and SCANIN are selected by a signal from SCANMODE input to the selector 11. The selection of this signal is executed by the setting of the TAP controller 12. Then, inserting the SCANIN, the SCANMODE, the SCANOUT, the selector 11, the TAP controller 12, and the line connecting them into the FF on the chip is referred to as insertion of the DFT circuit.

  The insertion of a DFT circuit for a plurality of FFs will be described with reference to FIG. FIG. 2 shows a first FF 20, a second FF 21, a first selector 22, a second selector 23, a TAP controller 24, an I / O cell 25, and an external input pin 26. The first FF 20 has DATA20, SCANIN20, SCANMODE20, and CLOCK20 as input terminals, and QUIT20 and SCANOUT20 as output terminals. The second FF 21 has DATA 21, SCANIN 21, SCANMODE 21, and CLOCK 21 as input terminals, and QUIT 21 and SCANOUT 21 as output terminals. Further, the SCANOUT 20 of the first FF 20 is connected to the SCANIN 21 of the second FF. In addition, a signal is input to the first selector 22 from the SCANMODE 20 connected to the TAP controller 24 in order to switch the signal between the DATA 20 and the SCANIN 20 of the first FF 20. In addition, a signal is input to the second selector 23 from the SCANMODE 21 connected to the TAP controller 24 in order to switch the signal between the DATA 21 and the SCANIN 21 of the second FF 21. Signal switching in the first selector 22 and the second selector 23 is realized by using the setting of the TAP controller 24 and a test input signal applied to the external input pin 26 connected to the TAP controller 24. The external input pin 26 is connected to the I / O cell 25 and is connected to the TAP controller 24 and elements in the circuit.

  In verification before and after insertion of the DFT circuit, whether to select DATA or SCANIN in each FF in the circuit is determined by using the setting of the TAP controller 24 and the external input pin 26, and desired verification is executed.

By the way, there is disclosed a logic equivalence verification method in which, when there is a logic added by circuit synthesis, a logic equivalence verification is performed by deleting the additional logic based on the added logic information. (For example, refer to Patent Document 2).
JP 2004-213605 A JP 2001-67379 A FUJITSU.50, 6 (1999) R. E. Bryant, “Graph-based Algorithms for Boolean Function Manipulation”, IEEE Trans. on Computers, C-35, pp677-691 P. R. Stephan et al., “Combinatorial Test Generation Using Saturability”, IEEE Trans. on CAD / ICAS, 15, 9, pp 1167-1176 (1996)

  As described above, since a fixed value signal does not propagate in a black boxed circuit, if a signal is set to a fixed value when verifying logical equivalence, and a black boxed circuit exists, it is black boxed. There is a problem that logical equivalence cannot be verified in the subsequent circuit.

The present invention is a logic equivalence verification method for verifying logic equivalence between two circuits, the first step of determining an input terminal that does not affect the output, and an external input in which a signal is set to a fixed value. When there is no connection with the external input in the second step, and when there is no connection with the external input in the second step, the target cell is loaded with a description file that does not have a user designation or function block When there is a connection with the external input in the second step and the third step of making a black box, the target cell becomes a verification point in the logical equivalence verification and the subsequent logic of the target cell. And a fourth step of replacing with a pseudo-logic circuit that influences the above.

  Even if the signal is set to a fixed value, a circuit with a dummy or open terminal that does not affect the output signal by using a pseudo logic circuit that becomes a verification point and affects the subsequent logic The logic following the configuration can be verified. It is also possible to automatically search for a circuit configuration having a dummy or open terminal that does not affect the output signal.

  With reference to FIG. 3, the insertion of a test scan circuit (Design For Testability, hereinafter referred to as DFT circuit) into a plurality of flip-flops (hereinafter referred to as FF) will be described. FIG. 3 shows a first FF 30, a second FF 31, a first selector 32, a second selector 33, a TAP controller 34, an I / O cell 35, and an external input pin 36. The first FF 30 includes DATA 30, SCANIN 30, SCANMODE 30, and CLOCK 30 that are input terminals, and QUIT 30 and SCANOUT 30 that are output terminals. The second FF 31 has DATA 31, SCANIN 31, SCANMODE 31, and CLOCK 31 that are input terminals, and QUIT 31 and SCANOUT 31 that are output terminals. Further, the SCANOUT 30 of the first FF 30 is connected to the SCANIN 31 of the second FF. In addition, a signal is input to the first selector 32 from the SCANMODE 30 connected to the TAP controller 34 in order to switch the signal between the DATA 30 and the SCANIN 30 of the first FF 30. In addition, a signal is input to the second selector 33 from the SCANMODE 31 connected to the TAP controller 34 in order to switch the signal between the DATA 31 and the SCANIN 31 of the second FF 31. Signal switching in the first selector 32 and the second selector 33 is realized by using the setting of the TAP controller 34 and the test input signal applied to the external input pin 36 connected to the TAP controller 34. The external input pin 36 is connected to the I / O cell 35 and is connected to the TAP controller 34 and elements in the circuit.

  Inserting the SCANIN, SCANMODE, SCANOUT, TAP controller, and connecting lines into the FF on the chip in this way is referred to as DFT circuit insertion or test synthesis. However, the insertion of the DFT circuit is not limited to the two FFs shown in FIG.

  In the verification before and after the DFT circuit is inserted, whether to select DATA or SCANIN in each FF in the circuit is determined using the setting of the TAP controller 34 and the external input pin 36, and desired verification is executed.

  By the way, the I / O cell 35 may have an input other than the connection to the external input pin 36, and when dummy logic is described in the connection portion, the I / O cell 35 and the I / O cell 35 are connected to the I / O cell 35. The logic between the circuit 37 connected to the O cell 35 is not subject to logical equivalence verification (see, for example, FIG. 8). Therefore, when performing logic verification between the circuit 37 connected to the I / O cell 35 and the I / O cell 35, a method of black boxing the I / O cell 35 with a CAD tool or the like, In the O cell 35, a method in which the I / O cell 35 is converted into a black box by using a file whose contents are not described is used. By this black boxing, the I / O cell 35 is set as a verification point, and the logic verification of the circuit 37 up to the I / O cell 35 becomes possible.

In addition to the I / O cell 35, in a cell connected to the external input pin 36 and having an input terminal other than the connection to the external input pin 36, the input terminal is the output of the cell. If the circuit 37 is connected to the input terminal, the logic equivalence verification between the cell and the circuit 37 cannot be performed. Therefore, logic verification can be performed by making the cell a black box in the same manner as the I / O cell 35.
However, a black box circuit generally does not propagate a fixed value signal because the contents of the circuit cannot be referred to. That is, when the I / O cell 35 is black boxed, the test input signal which is a fixed value signal given to the external input pin does not propagate from the external input pin 36 to the TAP controller 34. Therefore, for example, a signal for selecting DATA 30 and SCANIN 30 in the first selector 32 cannot be given to SCANMODE. The same applies to the second FF.

In other words, if the signal is set to a fixed value at the time of logic equivalence verification, the fixed value signal does not propagate after the black boxed circuit, and the logic following the black boxed circuit cannot be verified. There's a problem.
FIG. 4 shows an embodiment of a logical equivalence verification method using the present invention. FIG. 4 shows a step S40 for selecting a circuit design and a cell library that realizes a desired logic, a step S41 for generating a new cell library, and a step S42 for verifying logical equivalence. In the present invention, if there is no library composed of black boxed cells or cells replaced with pseudo logic circuits, logic equivalence verification is performed by giving circuit design and setting of fixed value signals before and after inserting the DFT circuit. Before that, a process for generating a new cell library is executed. Here, the pseudo logic circuit is a circuit that has been changed to a circuit configuration having a circuit that serves as a verification point and affects subsequent logic with respect to the circuit configuration of a target cell.
On the other hand, if there is already a library of cells that have been replaced with black boxed cells or pseudo-logic circuits, logical equivalence verification is performed using the library.
The process S41 for generating a new cell library shown in FIG. 4 will be described in detail with reference to FIG. In FIG. 5, a first step S51 for selecting an evaluation target cell that has not been verified, a second step S52 for determining whether there is an input terminal that does not affect the output signal, and the signal are set to a fixed value. Third step S53 for determining whether or not to connect to an external input, fourth step S54 for making the evaluation target cell into a black box when the determination in the third step is NO, and determination in the third step When YES is YES, a fifth step S55 for replacing the evaluation target cell with a pseudo logic circuit and a sixth step S56 for determining whether or not all the evaluation target cells have been verified are shown.

  In the first step S51, an evaluation target cell is selected from the cell library. In the second step S52, it is determined whether there is a terminal that does not affect the output signal. An example of the second step S52 is a method of inserting an inverter as shown in FIG. 6, which will be described later. In the third step S53, it is determined whether to introduce a pseudo logic circuit to a terminal that does not affect the output signal or to make a black box. At the time of logical equivalence verification, if the terminal of interest is not connected to an external input whose signal is set to a fixed value, the process proceeds to black box formation in the fourth step S54. On the other hand, when the terminal of interest is connected to an external input whose signal is set to a fixed value at the time of logic equivalence verification, the process proceeds to the replacement of the pseudo logic circuit which is the fifth step S55. Here, whether it is the fourth step S54 or the fifth step S55, a verification point is generated at the connection destination of the target terminal. That is, it is possible to advance all the circuits that are targeted in the third step S53 to the fifth step S55. However, using a black box that can generate a verification point by using a description file that does not have a functional block has the effect of simplifying verification and shortening verification time.

  From here, 2nd step S52, 3rd step S53, and 5th step S55 are demonstrated in detail.

  In FIG. 6, when an inverter is not added before one input terminal of the evaluation target cell 60 (a) and (a), an inverter is added before one input terminal of the same evaluation target cell 60. Taking the case (b) as an example, the second step S52 will be described. FIG. 6A shows an evaluation target circuit 62a including an evaluation target cell 60, an input terminal IN (a) 00, an input terminal IN (a) 01, and an output terminal OUT (a). (B) shows an evaluation object cell 60, an input terminal IN (b) 00, an input terminal IN (b) 01, an output terminal OUT (b), and an inverter added to the input terminal IN (b) 00. 6 shows an evaluation target circuit 62b.

  The difference in circuit configuration between the evaluation target circuit 62a and the evaluation target circuit 62b is only the presence or absence of the inverter 61. Therefore, in order to determine whether the output from the output terminal OUT (b) connected to the evaluation target cell 60 depends on the input to the input terminal IN (a) 00 connected to the evaluation target cell 60. The logic equivalence verification between the evaluation target circuit 62a and the evaluation target circuit 62b may be executed. At this time, if the logics of the evaluation target circuit 62a and the evaluation target circuit 62b match the same input to each evaluation target circuit, the input terminal IN (a) 00 is connected to the output terminal OUT (b). It can be said that it does not affect. On the other hand, when the logics of the evaluation target circuit 62a and the evaluation target circuit 62b do not match for the same input to each evaluation target circuit, the input terminal IN (a) 00 is connected to the output terminal OUT (b). It can be said that it affects. By performing the verification described above for all the input terminals connected to the evaluation target cell 60, it is possible to verify whether or not there is an input terminal that does not affect the output signal in the evaluation target cell 60. .

FIG. 7 shows a step S70 for selecting an evaluation target cell, a step S71 for instantiating the evaluation target cell, a step S72 for adding an inverter to one input terminal of the evaluation target cell, and a logical equivalence verification. Step S73 for determining whether or not there is a logic mismatch, Step S74 for storing as an input terminal that does not affect the output signal when the determination in Step S73 is NO, and whether or not all input terminals have been verified. Step S75 for determination and step S76 for determining whether there is an input terminal that does not affect the output signal are shown.
The second step S52 of FIG. 5 is executed by the process using each step shown in FIG. Here, the relationship between FIG. 7 and the second step S52 in FIG. 5 will be described in detail. If the determination in step S76 in FIG. 7 is YES, the process proceeds to the third step S53 shown in FIG. . On the other hand, if the determination in step S76 is no, the process proceeds to a sixth step S56 shown in FIG. At this time, the cell determined by the determination in step S76 as having no input terminal that does not affect the output signal is stored in the library as it is.

  In the embodiment of the present invention, the process from S75 to S72 can be changed to the process from S75 to S71. Moreover, when looping a process from S75 to S71, the order of S71 and S72 can be changed.

  Further, as a method that does not use an inverter in the second step S52, there is a method of inputting all combinations of input values to all input terminals. Here, all combinations are all combinations of 0 (L: Low) and 1 (H: High) for all input terminals.

  Next, a third step S53 determines whether or not the signal is connected to an external input set to a fixed value using design data or the like.

  The fifth step S55 will be described with reference to FIGS.

  FIG. 8 shows a circuit 80 as an example of a circuit that does not affect the output. The circuit 80 is a dummy logic composed of a tristate 83 connecting the input terminals A8 and C8, the output terminal X8, and the bidirectional terminal EB8, the input terminal PC8, and the NAND circuit 81 and the AND circuit 82 connected to the input terminal PC8. A library cell having a circuit and a line connecting the above circuits. In the circuit 80, the output from the output terminal X8 does not depend on the input of the input terminal PC8. Therefore, when performing logic verification up to the input terminal PC8, the circuit 80 needs to be black boxed. Note that the circuit 80 merely shows an example in which the output from the output terminal X8 does not depend on the input of the input terminal PC8. That is, in implementing the present invention, the configuration of the AND circuit 81 and the logic element 82 of the circuit 80 is not limited.

By the way, the fixed value signal does not propagate to the black box circuit 80. Therefore, when the circuit 80 is connected to an external input whose signal is set to a fixed value, the dummy logic circuit portion including the NAND circuit 81 and the AND circuit 82 of the circuit 80 is transferred to the pseudo logic circuit 90 shown in FIG. Replace with
FIG. 9 shows a pseudo logic circuit 90, input terminals A8, C8, and PC8, an output terminal X8, a bidirectional terminal EB8, and a tristate 83. The pseudo logic circuit 90 includes a latch 91, a selector 92, an AND circuit 93, an inverter 94, and lines connecting the above terminals and circuits.

  The configuration of the pseudo logic circuit 90 will be described in more detail. In the pseudo logic circuit 90, the output terminal of the latch 91 having two input terminals including the input terminal R 9 and the PC 8 are connected to the AND circuit 93. The output terminal of the AND circuit 93 is input to an input terminal that is not the input terminal R9 of the latch 91. The output terminal of the AND circuit 93, the input terminal A8, and the output terminal of the inverter 94 connected to A8 are connected to the selector 92. The selector 92 refers to the signal from the output terminal of the AND circuit 93 and selects the signal from the input terminal A8 and the signal from the output terminal of the inverter 94 connected to A8.

  In the pseudo logic circuit 90, the latch 91 serves as an input of a logic cone and a verification point. That is, in the logic equivalence verification of the logic cone including the circuit shown in FIG. 9, the verification using the input value which is not influenced by the logic value connected to the input terminal of the latch 91 is possible, and the input is made from the input terminal PC8. When the signal is fixed at 0, the latch 91 can be excluded from the logic equivalence verification target. In the selector 92, switching between the signal from the input terminal A8 and the inversion of the signal from the input terminal A8 is executed by the logical product of the outputs of the PC 8 and the latch 91.

  The operation of the pseudo logic circuit 90 of FIG. 9 will be described in further detail. Here, when 0 is input to the PC 8, a signal given to the input terminal A8 is output to the output terminal X8. On the other hand, when 1 is input to the PC 8, a signal given to the input terminal A8 according to the output of the latch 91 or its inverted signal is output to the output terminal X8. Accordingly, since the signal applied to the input terminal PC8 affects the value of the output signal X8, it is detected as a mismatch when an incorrect logic is connected to the PC8. That is, the logic up to the input terminal PC8 can be verified.

  At the same time, when the signal to the input terminal A8 is set to a fixed value, a fixed value signal that causes the signal to be 0 is also input to the input terminal PC8. At this time, the signal applied to the input terminal A is output to the output terminal X8. Therefore, it is possible to propagate the fixed value signal given to the input terminal A8. At this time, the latch 91 is not verified.

  When comparing the pseudo logic circuit 90 of FIG. 9 and the circuit 80 of FIG. 8 from the viewpoint of logical equivalence verification, in the pseudo logic circuit 90 of FIG. 9, a point serving as a verification point of logical equivalence verification is set by the latch. , The signal of the input terminal PC8 has a circuit that affects the subsequent logic of the pseudo logic circuit 90. In addition, since the latch 91 becomes an input of the logic cone, the degree of freedom of signal input is improved.

  Note that the execution of the fifth step S55 of the present invention is not limited to the pseudo logic circuit 90 of FIG. Any circuit that serves as a verification point and affects subsequent logic may be used as the pseudo logic circuit.

  As described above, according to the present invention, a library composed of cells replaced with pseudo logic circuits and cells made into black boxes is created. Then, logical equivalence verification is executed based on this library. As a result, even when the signal is set to a fixed value, logical equivalence verification can be performed by replacement with a pseudo logic circuit.

  The present invention is applicable to logical equivalence verification in LSI design.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Appendix 1) A logic equivalence verification method for verifying logic equivalence between two circuits,
A first step of determining an input terminal that does not affect the output;
A second step of determining the presence or absence of connection with an external input whose signal is set to a fixed value;
A third step of reading a description file having no user designation or function block into a black box when the target cell is not connected to the external input in the second step;
When there is a connection with the external input in the second step, the target cell is replaced with a pseudo logic circuit that becomes a verification point in the logical equivalence verification and affects the subsequent logic of the target cell. 4. A logical equivalence verification method comprising four steps.

(Supplementary note 2) The logical equivalence verification method according to supplementary note 1, wherein
The logic in which the first step is a step of verifying logical equivalence between a circuit having a first input terminal and a circuit having an input terminal obtained by adding an inverter to the first input terminal. Equivalence verification method.

(Supplementary note 3) The logical equivalence verification method according to supplementary note 1, wherein
The pseudo logic circuit includes a first circuit serving as a verification point of logic equivalence verification;
A first input signal of the pseudo logic circuit and an output signal of the first circuit are respectively input, and a logical product signal of the first input signal and the output signal of the first circuit is obtained as the first signal. A second circuit for outputting to the first circuit;
A third circuit that receives a second input signal of the pseudo-logic circuit and outputs a signal of an inverse logic of the second input signal;
A second circuit that receives the second input signal and the inverse logic signal and outputs the second input signal or the inverse logic signal in accordance with the logical product signal; A logical equivalence verification method comprising:

(Supplementary Note 4) a first circuit that is a verification point of logical equivalence verification;
A first input signal of the pseudo logic circuit and an output signal of the first circuit are respectively input, and a logical product signal of the first input signal and the output signal of the first circuit is obtained as the first signal. A second circuit that outputs to the circuit of
A third circuit that receives a second input signal of the pseudo-logic circuit and outputs a signal of an inverse logic of the second input signal;
A second circuit that receives the second input signal and the inverse logic signal and outputs the second input signal or the inverse logic signal in accordance with the logical product signal; A pseudo-logic circuit comprising:

It is a figure which shows FF (10b) by which the scan circuit for a test (henceforth a DFT circuit) was inserted with respect to the flip-flop (10a) (henceforth FF). It is a figure which shows an example in which the DFT circuit was inserted with respect to several FF. The figure which shows that the DFT circuit is inserted with respect to several FF, and another circuit 37 is connected to the input of the I / O cell 35 connected to the TAP controller 34 and the external input pin 36. It is. It is a figure which shows one Example of this invention. It is a figure which shows the process process which produces | generates the new cell library in one Example of this invention. It is a figure which shows the circuit (62b) by which the inverter was added to one of the input terminals of the evaluation object circuit (62a) and the evaluation object circuit (62a). It is a figure which shows the repair process which determines whether there exists an input terminal which does not affect an output signal using an inverter. It is a figure which shows the cell with the input terminal which does not influence an output signal. It is a figure which shows a pseudo logic circuit.

Explanation of symbols

10a: flip-flop (hereinafter referred to as FF)
10b: FF in which a test scan circuit (hereinafter referred to as a DFT circuit) is inserted
11b: selector for selecting between DATA and SCANIN 12: TAP controller 20: first FF
21: Second FF
22: first FF selector 23: second FF selector 24: TAP controller 25: I / O cell 26: external input pin 30: first FF
31: Second FF
32: First FF selector 33: Second FF selector 34: TAP controller 35: I / O cell 36: External input pin 37: Circuit connected to the I / O cell S40: Design and cell library Step S41 for selecting: Step S42 for generating a new cell library: Step S42 for executing logical equivalence verification Step S51: Selecting an unverified evaluation cell Step S52: Determining whether there is an input terminal that does not affect the output signal Step S53: Determining whether the signal is connected to an external input set to a fixed value Step S54: Black box step S55: Replacing with a pseudo logic circuit S56: Have all the evaluation target cells been verified? Step 60 for determining whether or not: Evaluation target cell 61: Inverter 62a: Evaluation pair Circuit 62b: Evaluation target circuit in which an inverter is added before one input terminal of the evaluation target cell 60 S70: Selecting the evaluation target cell S71: Instantiating the evaluation target cell S72: One input of the evaluation target cell Step S73 in which an inverter is added in front of the terminal for instance S73: Logical equivalence verification is performed to determine whether there is a logic mismatch Step S74: Step S75 for storing as an input terminal that does not affect the output signal Step S76 for determining whether there is an input terminal that does not affect the output signal Step 80: Circuit 81 having the input terminal PC8 that does not affect the output signal from X8: NAND circuit 82 : AND circuit 83: Tristate 90: For circuit 80 Circuit 91 with pseudo logic: Latch 92: Selector 93: the AND circuit 94: Inverter

Claims (4)

A logic equivalence verification method for verifying logic equivalence between two circuits,
A first step of determining an input terminal that does not affect the output;
A second step of determining the presence or absence of connection with an external input whose signal is set to a fixed value;
A third step of reading a description file having no user designation or function block into a black box when the target cell is not connected to the external input in the second step;
When there is a connection with the external input in the second step, the target cell is replaced with a pseudo logic circuit that becomes a verification point in the logical equivalence verification and affects the subsequent logic of the target cell. 4. A logical equivalence verification method comprising four steps. The logical equivalence verification method according to claim 1,
The logic in which the first step is a step of verifying logical equivalence between a circuit having a first input terminal and a circuit having an input terminal obtained by adding an inverter to the first input terminal. Equivalence verification method. The logical equivalence verification method according to claim 1,
The pseudo logic circuit includes a first circuit serving as a verification point of logic equivalence verification;
A first input signal of the pseudo logic circuit and an output signal of the first circuit are respectively input, and a logical product signal of the first input signal and the output signal of the first circuit is obtained as the first signal. A second circuit for outputting to the first circuit;
A third circuit that receives a second input signal of the pseudo-logic circuit and outputs a signal of an inverse logic of the second input signal;
A second circuit that receives the second input signal and the inverse logic signal and outputs the second input signal or the inverse logic signal in accordance with the logical product signal; A logical equivalence verification method comprising: A first circuit serving as a verification point of logical equivalence verification;
A first input signal of the pseudo logic circuit and an output signal of the first circuit are respectively input, and a logical product signal of the first input signal and the output signal of the first circuit is obtained as the first signal. A second circuit that outputs to the circuit of
A third circuit that receives a second input signal of the pseudo-logic circuit and outputs a signal of an inverse logic of the second input signal;
A second circuit that receives the second input signal and the inverse logic signal and outputs the second input signal or the inverse logic signal in accordance with the logical product signal; A pseudo-logic circuit comprising:

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