CN113760820B - Data configuration and read-back method of super-large-scale FPGA chip - Google Patents
Data configuration and read-back method of super-large-scale FPGA chip Download PDFInfo
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Abstract
The invention relates to a data configuration and readback method of a super-large-scale FPGA chip, belonging to the technical field of electronic information. The method is divided into a configuration stage and a read-back stage, and the rapid data transfer between the CRAM bit units by the configuration controller is realized by the buffer area according to different read-write directions. The invention does not adopt the conventional mode of directly butting the configuration controller and the CRAM, an intermediate module is erected between the configuration controller and the CRAM, and the data interaction between the configuration controller and the CRAM is buffered through the intermediate module. The method takes the frame as a unit, and configures and reads back data frame by frame, thereby supporting partial frame reconfiguration and discontinuous reconfiguration and being more efficient than the conventional full reading configuration.
Description
Technical Field
The invention relates to a data configuration and readback method of a super-large-scale FPGA chip, belonging to the technical field of electronic information.
Background
An SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) has programmability, rich internal resources including rich interface types, logic resources of hundreds of millions of gates, and diversity advantage of computing capability, and occupies the role of a hardware accelerator in the Field of data centers, and becomes a key core device of the data centers.
The conventional Configuration flow consists of 4 main steps, which are clear Configuration Memory (Initialization), Initialization (Initialization), Loading Configuration Data (Loading Configuration Data), and chip start (Device start), respectively. (1) After the FPGA chip is powered on, the configuration controller firstly blocks the IO of the whole chip, then freezes the core, and then clears the CRAM in the chip line by line. The purpose of clearing the CRAM is to initialize the CRAM to a certain value in case its uncertain output value causes an undesired short circuit or other problem, eliminating the uncertainty in the circuit. (2) In the initialization phase, the FPGA samples the configuration mode selection in preparation for loading data. (3) Loading configuration data in this step, a state machine in the configuration controller skips according to the input code stream, decodes the configuration codes from the code stream and sends them to the corresponding configurable logic unit. (4) After the configuration controller completes all configurations, the core is unfrozen, the DONE is pulled high, and the user circuit starts to operate.
The conventional read-back procedure pulls the DONE signal low for the user and feeds a read-back command during the low level of DONE. Each time a read-back command is sent in, the device reads out the corresponding CRAM code at one time. And after the read-back is finished, releasing the DONE to be high level by the user, and automatically executing subsequent unfreezing operation by the device.
And as the logic resource scale of the FPGA chip is larger and larger, the configuration data amount is huge, and as the configuration controller directly controls the CRAM module, a bottleneck of configuration data transmission exists between the CRAM module and the CRAM module, the configuration time cost is high, and the overall performance of configuration and readback of the FPGA chip is reduced.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: along with the increasing scale of logic resources of the FPGA chip, more and more configuration data are provided, so that the problems of overlong time of configuration and readback stages and reduced chip performance are caused.
In order to solve the technical problems, the technical scheme provided by the invention is as follows: a data configuration and read-back method of a super-large-scale FPGA chip comprises the following steps:
A. in the configuration phase, the configuration phase is carried out,
step 2, when the pre-fetching data updating module receives and finishes a frame of configuration data, a write enabling signal is sent to the configuration data storage module, and a frame of pre-fetching data is output to the configuration data storage in a clock period;
step 3, writing the write direction of the configuration data storage module into position information and a frame of pre-fetching configuration data sent by the configuration controller; the configuration data storage module reads the direction and outputs the configuration data of the current frame required by the configuration processing module;
step 4, the configuration processing module receives the current frame configuration data from the configuration data storage module, receives the position information of the current frame from the configuration controller, sends write enable control to the corresponding CRAM and sends the arranged configuration data to each CRAM bit cell;
B. in the read-back phase,
step 2, when the pre-fetching data updating module receives and finishes a frame of read-back data, a write enabling signal is sent to the configuration data storage module, and a frame of pre-fetching data is output to the configuration data storage in a clock period;
step 3, writing the write direction of the configuration data storage module into position information and a frame of pre-fetching configuration data sent by the configuration controller; the read direction of the configuration data storage module outputs read-back data of the current frame required by the configuration controller module;
and 4, receiving the current frame read-back data from the configuration data storage module by the configuration controller module.
The invention has the beneficial effects that: and a conventional mode of directly butting the configuration controller with the CRAM is not adopted, an intermediate module is erected between the configuration controller and the CRAM, and data interaction between the configuration controller and the CRAM is buffered through the intermediate module. The method takes the frame as a unit, and configures and reads back data frame by frame, thereby supporting partial frame reconfiguration and discontinuous reconfiguration and being more efficient than the conventional full reading configuration.
Drawings
Fig. 1 is a schematic flowchart of a data configuration and read-back method of a very large FPGA chip according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a device used in a data configuration and read-back method of a very large-scale FPGA chip according to an embodiment of the present invention.
Fig. 3 is a block diagram of a prefetch data update structure in a data configuration and read-back method of a very large FPGA chip according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of configuration data storage in a data configuration and read-back method of a very large FPGA chip according to an embodiment of the present invention.
Detailed Description
Example one
A data configuration and read-back method of a very large-scale FPGA chip is disclosed, as shown in figure 1,
A. in the configuration phase, the configuration phase is carried out,
step 2, when the pre-fetching data updating module receives and finishes a frame of configuration data, a write enabling signal is sent to the configuration data storage module, and a frame of pre-fetching data is output to the configuration data storage in a clock period;
step 3, writing the write direction of the configuration data storage module into position information and a frame of pre-fetching configuration data sent by the configuration controller; the configuration data storage module reads the direction and outputs the configuration data of the current frame required by the configuration processing module;
step 4, the configuration processing module receives the current frame configuration data from the configuration data storage module, receives the position information of the current frame from the configuration controller, sends write enable control to the corresponding CRAM and sends the arranged configuration data to each CRAM bit cell;
B. in the read-back phase,
step 2, when the pre-fetching data updating module receives and finishes a frame of read-back data, a write enabling signal is sent to the configuration data storage module, and a frame of pre-fetching data is output to the configuration data storage in a clock period;
step 3, writing the write direction of the configuration data storage module into position information and a frame of pre-fetching configuration data sent by the configuration controller; the read direction of the configuration data storage module outputs read-back data of the current frame required by the configuration controller module;
and 4, receiving the current frame read-back data from the configuration data storage module by the configuration controller module.
In this embodiment, each module is integrated in the buffer device, and includes an original FPGA chip configuration controller and a CRAM bit unit, and a prefetch data updating module, a configuration data storage and configuration processing module are provided between the FPGA chip configuration controller and the CRAM bit unit, so as to provide a buffer space for the FPGA chip configuration controller and the CRAM bit unit in the matching and read-back processes. As shown in fig. 2, the apparatus includes a configuration controller, a prefetch data update module, a configuration data store, a configuration processing module, and a CRAM bit cell. The configuration controller module is not only used for configuration control of a full FPGA chip, but also used for controlling the whole high-efficiency configuration read-back buffer device, meanwhile, corresponding pre-fetching data is provided for the pre-fetching data updating module in the configuration stage, and the read-back data is sent back to the configuration controller from the pre-fetching data updating module in the read-back stage; the prefetch data updating module is used for receiving prefetch configuration data according to the system information provided by the configuration controller; the configuration data store is used for configuring the configuration data required by the processing module; the configuration processing module is used for controlling the transmission of the configuration data to the CRAM bit cell; the CRAM bit cell is used to store valid configuration bitstream coding information.
The block diagram of the structure of the prefetch data update of this embodiment is shown in fig. 3. The values of m and n depend on the structure of a frame of chip configuration data. Configuration direction data enter from the left side of m pe units on the leftmost column at the same time, readback direction data enter from the upper side of m pe units on the left column at the same time, and data of one frame are output through pulse propagation of n periods.
Fig. 4 shows a schematic diagram of configuration data storage according to an embodiment of the present disclosure. The configuration data storage module is used for storing a current frame and a pre-fetching data frame, and can store a plurality of frames of pre-fetching data under the condition of permission of a storage space, so that the full efficiency in the whole configuration read-back process is ensured.
The present invention is not limited to the specific technical solutions described in the above embodiments, and other embodiments may be made in the present invention in addition to the above embodiments. It will be understood by those skilled in the art that various changes, substitutions of equivalents, and alterations can be made without departing from the spirit and scope of the invention.
Claims (1)
1. A data configuration and read-back method of a super-large-scale FPGA chip is characterized in that:
A. in the configuration phase, the configuration phase is carried out,
step 1, a pre-fetching data updating module receives direction information and position information sent by a configuration controller and starts to count and pre-fetch configuration data of a frame;
step 2, when the pre-fetching data updating module receives and finishes a frame of configuration data, a write enabling signal is sent to the configuration data storage module, and a frame of pre-fetching data is output to the configuration data storage in a clock period;
step 3, writing the write direction of the configuration data storage module into position information and a frame of pre-fetching configuration data sent by the configuration controller; the configuration data storage module reads the direction and outputs the configuration data of the current frame required by the configuration processing module;
step 4, the configuration processing module receives the current frame configuration data from the configuration data storage module, receives the position information of the current frame from the configuration controller, sends write enable control to the corresponding CRAM and sends the arranged configuration data to each CRAM bit cell;
B. in the read-back phase,
step 1, a configuration processing module receives direction information and position information sent by a configuration controller, reads read-back data from a read enable of a corresponding CRAM bit unit, and arranges the read-back data to output the read-back data to a pre-fetch data updating module according to a frame format;
step 2, when the pre-fetching data updating module receives and finishes a frame of read-back data, a write enabling signal is sent to the configuration data storage module, and a frame of pre-fetching data is output to the configuration data storage in a clock period;
step 3, writing the write direction of the configuration data storage module into position information and a frame of pre-fetching configuration data sent by the configuration controller; the read direction of the configuration data storage module outputs read-back data of the current frame required by the configuration controller module;
step 4, the configuration controller module receives the current frame read-back data from the configuration data storage module;
the configuration controller module is not only used for controlling the configuration of the FPGA chip, but also used for controlling the whole buffer device, meanwhile, corresponding pre-fetching data is provided for the pre-fetching data updating module in the configuration stage, and the read-back data is sent back to the configuration controller from the pre-fetching data updating module in the read-back stage;
the prefetch data updating module is used for receiving prefetch configuration data according to system information provided by the configuration controller; the configuration data storage module is used for configuring the configuration data required by the processing module; the configuration processing module is used for controlling the transmission of the configuration data to the CRAM bit cell; the CRAM bit cell is used for storing effective configuration bitstream code information;
the buffer device comprises a configuration controller, a pre-fetching data updating module, a configuration data storage module, a configuration processing module and a CRAM bit unit.
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