CN106547483B - A kind of the SDR sdram controller and its working method of Universal efficient - Google Patents

A kind of the SDR sdram controller and its working method of Universal efficient Download PDF

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Publication number
CN106547483B
CN106547483B CN201610909322.7A CN201610909322A CN106547483B CN 106547483 B CN106547483 B CN 106547483B CN 201610909322 A CN201610909322 A CN 201610909322A CN 106547483 B CN106547483 B CN 106547483B
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read
control module
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CN106547483A (en
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葛庆国
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Guangdong High Cloud Semiconductor Technologies Ltd Co
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0613—Improving I/O performance in relation to throughput
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0634—Configuration or reconfiguration of storage systems by changing the state or mode of one or more devices

Abstract

The present invention relates to the SDR sdram controllers and its working method of a kind of Universal efficient, including PLL, Subscriber Interface Module SIM, automatic refresh module and command control module；Subscriber Interface Module SIM includes write buffer processing module, Read-write Catrol state machine module, inter-bank read-write processing module；Command control module includes automatic refresh process module, state initialization module, working sequence control module, order data transceiver module；The present invention is 1 by choosing read-write burst-length, the characteristics of using being operated continuously between write order between SDR SDRAM read command, on the basis of traditional controller by user interface optimization, user data buffering, data enter a new line segmentation, the realization burst-length such as reading and writing data timing controlled from 1 to page length within the scope of flexible read-write, user can read and write the needs of length according to itself specific procedure dynamically to control each read-write length, each read-write is completed in maximum efficiency, improves interface data handling capacity.

Description

A kind of the SDR sdram controller and its working method of Universal efficient
Technical field
The present invention relates to the SDR sdram controllers and its working method of a kind of Universal efficient, belong to FPGA IP kernel technology Field.
Background technique
IP kernel full name IP core (Intellectual Property Core), the form for referring to that one party provides are The reusable module of logic unit, chip design.Designer can carry out specific integrated circuit or scene based on IP kernel The logical design of programmable gate array, to reduce the design cycle.
SDR SDRAM memory has good cost performance, is used widely in many fields, but SDR SDRAM There are the timing requirements that comparison is stringent, logic control is more complicated, need a special controller to realize data read-write control, Verilog HDL or VHDL language can be used to realize in the controller.Controller characteristic specifically includes that
● burst-length supports 1,2,4,8 and whole page；
● CAS delay can be 2 or 3 clock cycle；
● automatic refresh function, self-refresh function, low-power consumption mode；
● including NOP, READ, WRITE, AUTO_REFRESH, PRECHARGE, ACTIVATE, URST_STO and LOAD_ The SDRAM control command such as MR；
● support 4,8,16,32 bit data widths.
FPGA has the characteristics that restructural, logical resource is abundant, I/O interface flexible, the SDR SDRAM control based on FPGA Device design can largely simplify design method, shorten the product designer development cycle.The read-write of SDR SDRAM memory Burst-length can choose 1,2,4,8 or whole page.When 1,2,4,8 burst-lengths of selection are written and read, all brought due to reading and writing every time Control overhead, so total read-write efficiency is not high；If choosing whole page operations mode, when write-in or the data length read are much small A large amount of memory space and interface access time are slatterned in page length degree Shi Zehui, overall efficiency is also intended to big heavy discount.
Summary of the invention
In view of the deficiencies of the prior art, the present invention provides a kind of SDR sdram controllers of Universal efficient.
The present invention also provides the working methods of above-mentioned SDR sdram controller；
In order to realize that SDR SDRAM can support 1 to read and write to the random length burst within the scope of page length, the present invention passes through choosing Reading and writing burst-length is 1, the characteristics of using that can operate continuously between write order between SDR SDRAM read command, by SDR Sdram controller continuously provides read write command to SDRAM from the raw Address count of movable property.
The present invention is buffered on the basis of traditional controller by user interface optimization, user data, data line feed is divided, Reading and writing data timing controlled etc. realize burst-length from 1 to page length within the scope of flexible read-write, user can be according to itself specific journey Sequence reads and writes the needs of length dynamically to control each read-write length, completes each read-write in maximum efficiency, improves interface Data throughout.
Term is explained
PLL (Phase Locked Loop): for phase-locked loop or phaselocked loop；
The technical solution of the present invention is as follows:
A kind of SDR sdram controller of Universal efficient, including PLL, Subscriber Interface Module SIM, automatic refresh module and order Control module；The Subscriber Interface Module SIM includes write buffer processing module, Read-write Catrol state machine module, inter-bank read-write processing mould Block；The command control module includes automatic refresh process module, state initialization module, working sequence control module, order Data transmit-receive module；
The PLL is separately connected the Subscriber Interface Module SIM, the automatic refresh module and the command control module；Institute State Subscriber Interface Module SIM, the automatic refresh module is all connected with the command control module；The Subscriber Interface Module SIM connection is used Family, the command control module connect SDR SDRAM memory.
Preferred according to the present invention, the Subscriber Interface Module SIM passes through address wire, write data line, read data line, control line Connect user side interface；The command control module connects SDR SDRAM memory side by address wire, control line, data line Interface；The Subscriber Interface Module SIM connects the command control module by control line, data line.
Subscriber Interface Module SIM is located among user logic and command processing module, realizes data length analysis, inter-bank read-write Handle, write data buffer storage processing, idle instruction processing etc.；Signal between Subscriber Interface Module SIM and user side include read-write data, Read/write address, read-write is enabled, read-write length, idle instruction, read-write response, reads effectively instruction, clock etc.；User logic is according to sky Spare time indicates to decide whether to carry out reading and writing data.After Subscriber Interface Module SIM receives read write command, it can be believed according to length, address etc. Breath judges whether to be divided into read-write operation twice, and the read-write of start command processing module.
The automatic refresh module generates automatic refresh according to the refresh parameter timing of different SDR SDRAM memories and asks It asks, realizes that the data of SDR SDRAM memory are kept.
The function that command control module is completed includes initialization process, automatic refresh process, controller timing control, order With data transmitting-receiving process etc..It include enabled read-write, read/write address, read-write data, free time with Subscriber Interface Module SIM interface signal Indicate, read effectively instruction, double read-writes instruction etc., it include automatic refresh requests, automatically brush with automatic refresh module interface signal New response, includes address, data, control etc. with memory side interface interface signal；After powering on, command processing module can be first Initialization waiting is carried out, is then initialized, enters idle state after the completion, according to automatic refresh requests or read-write requests point It carry out not respective handling.
It is preferred according to the present invention, using FPGA internal resource, PLL generate suitable sdram controller work clock and SDRAM clock signal；The write buffer processing module is for temporarily storing user data；Due to needed when SDRAM write operation through Cross intermodule processing, SDRAM activation, activation wait and wait links, so needing what temporary storage user sent to write data.It is pending Another when write command and submitting is sent to write data.The Read-write Catrol state machine module is for the Subscriber Interface Module SIM and the life Enable the data read-write control between control module；The inter-bank read-write processing module is for analyzing processing read-write data address and length Degree carries out inter-bank dividing processing if read/write address exceeds bailwick；The automatic refresh process module is used for SDR The refresh control of SDRAM memory；Guarantee the validity of data storage.The working sequence control module is for generating SDR The initialization of sdram controller, refreshing, read-write operation working sequence；The order data transceiver module is for generating transmission Various controls and read write command to SDR SDRAM memory；The state initialization module is used to carry out initialization waiting, and Initialize SDR sdram controller.
The working method of above-mentioned SDR sdram controller, specific steps include:
(1) the state initialization module carries out initialization waiting and enters step (2) after the default waiting time to be achieved；
(2) the state initialization module initialization SDR sdram controller；
(3) judge to initialize whether SDR sdram controller is completed, if completed, enter step (4), otherwise, return to step Suddenly (2)；
(4) SDR sdram controller is placed in idle state；
(5) command control module judges whether the automatic refresh module issues automatic refresh requests, if so, institute It states command control module to start to execute automatic refreshing, return step (4) after the completion of refreshing；Otherwise, (6) are entered step；
(6) Subscriber Interface Module SIM judges whether user side interface has Read-write Catrol request, if so, at the inter-bank read-write Module analysis processing read-write data address and length are managed, inter-bank dividing processing is carried out, is sent after having handled to command control module Read-write requests enter step (7)；Subscriber Interface Module SIM is to be sent data deposit write buffer area etc. is write simultaneously, enters step (9)；If not provided, return step (4)；
(7) Subscriber Interface Module SIM judges whether read-write operation terminates, if so, return step (4)；Otherwise, it enters step (8)；
(8) command control module sends activation, reading to SDR SDRAM memory according to the read-write requests of Subscriber Interface Module SIM Write command enters step (9)；
(9) command control module is written and read according to the data length that Subscriber Interface Module SIM is sent；
(10) command control module judges whether read-write terminates, if so, entering step (11)；Otherwise, return step (9)；
(11) command control module carries out preliminary filling electric treatment to SDR SDRAM memory, enters step (7) after the completion.
The invention has the benefit that
1, the present invention is 1 by choosing read-write burst-length, using can between write order between SDR SDRAM read command The characteristics of to operate continuously, passes through user interface optimization, user data buffering, data line feed point on the basis of traditional controller It cuts, the flexible read-write within the scope of reading and writing data timing controlled etc. realizes burst-length from 1 to page length, user can be specific according to itself Program reads and writes the needs of length dynamically to control each read-write length, completes each read-write in maximum efficiency, improves and connect Mouth data throughout；
2, the present invention uses FPGA platform, and resourceful, circuit is realized and flexibly transplanted well with code；
3, the present invention realizes controller to the automatic refreshing function of memory by rationally reading and writing and refreshing co-ordination mechanism Energy.
Detailed description of the invention
Fig. 1 is the structural block diagram of SDR sdram controller of the present invention；
Fig. 2 is the flow chart of work methods of SDR sdram controller of the present invention.
Specific embodiment
The present invention is further qualified with embodiment with reference to the accompanying drawings of the specification, but not limited to this.
Embodiment 1
A kind of SDR sdram controller of Universal efficient, as shown in Figure 1, including PLL, Subscriber Interface Module SIM, automatic refreshing Module and command control module；Subscriber Interface Module SIM includes write buffer processing module, Read-write Catrol state machine module, inter-bank read-write Processing module；Command control module includes automatic refresh process module, state initialization module, working sequence control module, life Enable data transmit-receive module；
PLL is separately connected Subscriber Interface Module SIM, automatic refresh module and command control module；It is Subscriber Interface Module SIM, automatic Refresh module is all connected with command control module；Subscriber Interface Module SIM connects user, and command control module connects SDR SDRAM storage Device.
Subscriber Interface Module SIM connects user side interface by address wire, write data line, read data line, control line；Order control Molding block connects SDR SDRAM memory side interface by address wire, control line, data line；Subscriber Interface Module SIM passes through control Line, data line connect the command control module.
Subscriber Interface Module SIM is located among user logic and command processing module, realizes data length analysis, inter-bank read-write Handle, write data buffer storage processing, idle instruction processing etc.；Signal between Subscriber Interface Module SIM and user side include read-write data, Read/write address, read-write is enabled, read-write length, idle instruction, read-write response, reads effectively instruction, clock etc.；User logic is according to sky Spare time indicates to decide whether to carry out reading and writing data.After Subscriber Interface Module SIM receives read write command, it can be believed according to length, address etc. Breath judges whether to be divided into read-write operation twice, and the read-write of start command processing module.
Automatic refresh module generates automatic refresh requests according to the refresh parameter timing of different SDR SDRAM memories, real The data of existing SDR SDRAM memory are kept.
The function that command control module is completed includes initialization process, automatic refresh process, controller timing control, order With data transmitting-receiving process etc..It include enabled read-write, read/write address, read-write data, free time with Subscriber Interface Module SIM interface signal Indicate, read effectively instruction, double read-writes instruction etc., it include automatic refresh requests, automatically brush with automatic refresh module interface signal New response, includes address, data, control etc. with memory side interface interface signal；After powering on, command processing module can be first Initialization waiting is carried out, is then initialized, enters idle state after the completion, according to automatic refresh requests or read-write requests point It carry out not respective handling.
Using FPGA internal resource, PLL generates suitable sdram controller work clock and SDRAM clock signal；It is described Write buffer processing module is for temporarily storing user data；Due to being needed when SDRAM write operation by intermodule processing, SDRAM Activation, activation wait and wait links, so needing what temporary storage user sent to write data.It is sent together again when write command to be sent Data are write out.The Read-write Catrol state machine module is for the number between the Subscriber Interface Module SIM and the command control module According to Read-write Catrol；The inter-bank read-write processing module is for analyzing processing read-write data address and length, if read/write address exceeds Bailwick then carries out inter-bank dividing processing；The automatic refresh process module is used for the refreshing control of SDR SDRAM memory System；Guarantee the validity of data storage.The working sequence control module be used for generate SDR sdram controller initialization, Refresh, the working sequence of read-write operation；The order data transceiver module is sent to each of SDR SDRAM memory for generating Kind control and read write command；The state initialization module initializes SDR SDRAM control for carrying out initialization waiting Device.
Embodiment 2
The working method of the SDR sdram controller of a kind of Universal efficient described in embodiment 1, as shown in Fig. 2, specific step Suddenly include:
(1) the state initialization module carries out initialization and waits 100us, after the default waiting time to be achieved, into step Suddenly (2)；
(2) the state initialization module initialization SDR sdram controller；
(3) judge to initialize whether SDR sdram controller is completed, if completed, enter step (4), otherwise, return to step Suddenly (2)；
(4) SDR sdram controller is placed in idle state；
(5) command control module judges whether the automatic refresh module issues automatic refresh requests, if so, institute It states command control module to start to execute automatic refreshing, return step (4) after the completion of refreshing；Otherwise, (6) are entered step；
(6) Subscriber Interface Module SIM judges whether user side interface has Read-write Catrol request, if so, at the inter-bank read-write Module analysis processing read-write data address and length are managed, inter-bank dividing processing is carried out, is sent after having handled to command control module Read-write requests enter step (7)；Subscriber Interface Module SIM is to be sent data deposit write buffer area etc. is write simultaneously, enters step (9)；If not provided, return step (4)；
(7) Subscriber Interface Module SIM judges whether read-write operation terminates, if so, return step (4)；Otherwise, it enters step (8)；
(8) command control module sends activation, reading to SDR SDRAM memory according to the read-write requests of Subscriber Interface Module SIM Write command enters step (9)；
(9) command control module is written and read according to the data length that Subscriber Interface Module SIM is sent；
(10) command control module judges whether read-write terminates, if so, entering step (11)；Otherwise, return step (9)；
(11) command control module carries out preliminary filling electric treatment to SDR SDRAM memory, enters step (7) after the completion.

Claims (3)

1. a kind of SDR sdram controller of Universal efficient, which is characterized in that including PLL, Subscriber Interface Module SIM, automatic refreshing Module and command control module；The Subscriber Interface Module SIM includes write buffer processing module, Read-write Catrol state machine module, inter-bank Read and write processing module；The command control module includes automatic refresh process module, state initialization module, working sequence control Module, order data transceiver module；
The PLL is separately connected the Subscriber Interface Module SIM, the automatic refresh module and the command control module；The use Family interface module, the automatic refresh module are all connected with the command control module；The Subscriber Interface Module SIM connects user, institute State command control module connection SDR SDRAM memory；
Using FPGA internal resource, PLL generates suitable sdram controller work clock and SDRAM clock signal；It is described write it is slow Processing module is deposited for interim storage user data；The Read-write Catrol state machine module is used for the Subscriber Interface Module SIM and institute State the data read-write control between command control module；The inter-bank read-write processing module is for analyzing processing read-write data address And length carries out inter-bank dividing processing if read/write address exceeds bailwick；The automatic refresh process module is used for SDR The refresh control of SDRAM memory；The working sequence control module is used to generate the initialization of SDR sdram controller, brush Newly, the working sequence of read-write operation；The order data transceiver module is sent to the various of SDR SDRAM memory for generating Control and read write command；The state initialization module initializes SDR sdram controller for carrying out initialization waiting.
2. a kind of SDR sdram controller of Universal efficient according to claim 1, which is characterized in that the user connects Mouth mold block connects user side interface by address wire, write data line, read data line, control line；The command control module passes through Address wire, control line, data line connect SDR SDRAM memory side interface；The Subscriber Interface Module SIM passes through control line, data Line connects the command control module.
3. a kind of working method of the SDR sdram controller of Universal efficient of any of claims 1 or 2, which is characterized in that tool Body step includes:
(1) the state initialization module carries out initialization waiting and enters step (2) after the default waiting time to be achieved；
(2) the state initialization module initialization SDR sdram controller；
(3) judge to initialize whether SDR sdram controller is completed, if completed, enter step (4), otherwise, return step (2)；
(4) SDR sdram controller is placed in idle state；
(5) command control module judges whether the automatic refresh module issues automatic refresh requests, if so, the life Control module is enabled to start to execute automatic refreshing, return step (4) after the completion of refreshing；Otherwise, (6) are entered step；
(6) Subscriber Interface Module SIM judges whether user side interface has Read-write Catrol request, if so, inter-bank read-write processing mould Block analysis processing read-write data address and length, carry out inter-bank dividing processing, send and read and write to command control module after having handled Request, enters step (7)；Subscriber Interface Module SIM is to be sent data deposit write buffer area etc. is write simultaneously, enters step (9)；Such as Fruit does not have, return step (4)；
(7) Subscriber Interface Module SIM judges whether read-write operation terminates, if so, return step (4)；Otherwise, (8) are entered step；
(8) command control module is according to the read-write requests of Subscriber Interface Module SIM to SDR SDRAM memory sends activation, read-write refers to It enables, enters step (9)；
(9) command control module is written and read according to the data length that Subscriber Interface Module SIM is sent；
(10) command control module judges whether read-write terminates, if so, entering step (11)；Otherwise, return step (9)；
(11) command control module carries out preliminary filling electric treatment to SDR SDRAM memory, enters step (7) after the completion.
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CN107864361B (en) * 2017-11-29 2024-02-27 上海先基半导体科技有限公司 Laser range finder and laser range finding display control system thereof
CN111240582B (en) * 2018-11-29 2022-01-28 长鑫存储技术有限公司 Data reading and writing method, reading and writing device and dynamic random access memory
CN109766285A (en) * 2019-01-10 2019-05-17 中国科学院长春光学精密机械与物理研究所 A kind of the SDRAM access control system and control method of burst mode
CN110046113B (en) * 2019-05-06 2024-02-09 华峰测控技术(天津)有限责任公司 SDRAM control system and SDRAM control method based on FPGA
CN116010310B (en) * 2023-03-21 2023-07-04 广东华芯微特集成电路有限公司 SDR-SDRAM controller and control method thereof

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PC01 Cancellation of the registration of the contract for pledge of patent right
PC01 Cancellation of the registration of the contract for pledge of patent right

Date of cancellation: 20210412

Granted publication date: 20190611

Pledgee: Science City (Guangzhou) Finance Leasing Co.,Ltd.

Pledgor: Gowin Semiconductor Corp.,Ltd.

Registration number: Y2019990000800