CN110046113A - A kind of SDRAM control system and control method based on FPGA - Google Patents
A kind of SDRAM control system and control method based on FPGA Download PDFInfo
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- CN110046113A CN110046113A CN201910372574.4A CN201910372574A CN110046113A CN 110046113 A CN110046113 A CN 110046113A CN 201910372574 A CN201910372574 A CN 201910372574A CN 110046113 A CN110046113 A CN 110046113A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1684—Details of memory controller using multiple buses
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1689—Synchronisation and timing concerns
Abstract
The SDRAM control system based on FPGA that the present invention provides a kind of, if including FPGA unit and dry plate SDRAM connected to it；The FPGA unit includes Instruction decoding module, state machine module, read through model, writing module, data/address bus and control bus.The present invention carries out gating Read-write Catrol to multi-disc SDRAM by using a state machine module based on three-stage design theory, control is write in reading simultaneously simultaneously, and meet requirement of the every SDRAM to refresh time, and it not will cause loss of data, wider array of application scenarios can be applicable in, read-write requests are checked in Flushing status simultaneously, it can be avoided state machine module and cannot respond to read-write requests in Flushing status, therefore the design of the state machine module can have preferable stability, it is higher with overall efficiency, the many advantages such as the maintenance and upgrade convenient for the project later period, also there is optimization layout simultaneously and save the advantage of resource.
Description
Technical field
It is the present invention relates to sdram controller design field in digital IC testing system, in particular to a kind of based on FPGA's
SDRAM control system and control method.
Background technique
Currently, needing in digital IC testing system by a large amount of graphics data saving in external memory, in chip
Graph data is read from external memory when test and digital chip functions are tested.SDRAM(Synchronous
Dynamic Random Access Memory, SDRAM) it is a high speed, high capacity dynamic memory, compared with SRAM, no
Only capacity is much bigger, and price is also relatively cheap, thus answers extensively in digital IC testing system and the acquisition of other industrial circles
With.Although there is some general sdram controllers currently on the market, exist setting is complicated, the readable poor, module of code compared with
It is more, can be directed to specific system, play the advantage of SDRAM.Also, sdram controller in the market is mostly for one
Piece SDRAM is designed, to same time control on FPGA (Field Programmable Gate Array, FPGA) chip
Multi-disc SDRAM processed then needs repeatedly example, and such design causes very big difficulty to the maintenance and upgrade of later period code.
For example, the patent document " the SDRAM control system based on FPGA " of Publication No. CN106649157A, passes through one
Interface modular converter is realized the different sdram controller IP interface conversions of different FPGA manufacturers into a kind of general RAM
(Random Access Memory, random access memory) interface, so that realizing can make in the FPGA of different vendor
With SDRAM memory, but this design scheme based on Xilinx sdram controller IP does not adapt to test in digital IC and is
To the complicated use demand of SDRAM in system.
Burst access is write to the arbitrary address random length of SDRAM due in digital IC testing system, needing to realize,
And its control bus needs and upper one layer of module is compatible with；In read access SDRAM, need to realize that arbitrary address is arbitrarily long
The reading burst access of degree, and to be read data from SDRAM according to different rates；In addition to this, it is tested in digital IC and is
It generally requires to use muti-piece SDRAM in system, therefore controller is required to control muti-piece SDRAM simultaneously, and to meet difference
The refreshing requirement of every piece of SDRAM in the case of access.And this use in digital IC testing system to SDRAM multiplicity and complexity
Demand is that general SDRAM control program institute is irrealizable, it is therefore desirable to the SDRAM control system that one kind specially designs.
Summary of the invention
In view of this, the main purpose of the present invention is to provide a kind of SDRAM control system based on FPGA, by using
One carries out gating Read-write Catrol to multi-disc SDRAM based on the state machine module control module of three-stage design theory while reading
Or control is write simultaneously, and meets requirement of the every SDRAM to refresh time, and not will cause loss of data, it can be applicable in wider
Application scenarios, while read-write requests are checked in Flushing status, can be avoided state machine module Flushing status can not
Read-write requests are responded, therefore the design of the state machine module there can be preferable stability, with overall efficiency is higher, is convenient for
The many advantages such as the maintenance and upgrade in project later period, meanwhile, module sharing method is used to multi-disc SDRAM, also there is optimization cloth
Office and the advantage for saving resource.
A kind of SDRAM control system based on FPGA provided by the invention, including FPGA unit and connected to it several
Piece SDRAM；
The FPGA unit includes Instruction decoding module, state machine module, read through model, writing module, data/address bus and control
Bus；
Described instruction decoding module is for decoding the instruction from external bus；
When decoding out reading instruction, described instruction decoding module configures the address of the address SDRAM and read through model inner buffer RAM
Range, the state machine module are corresponding according to the SDRAM address strobe monolithic or multi-disc for receiving the reading instruction
SDRAM, control read through model read the inner buffer of data deposit read through model from corresponding SDRAM, and according to read through model feedback
Buffer status controls the data readback of its caching to external bus or high speed data lines；
The read through model is described from corresponding SDRAM reading data and according to the read through model inner buffer for executing
The address range of RAM is stored in its inner buffer, executes the feedback to the buffer status, executes the data readback of the caching extremely
External bus or high speed data lines；
When decoding out write command, described instruction decoding module configures the address of the address SDRAM and writing module inner buffer RAM
Range, the state machine module are used for according to the SDRAM address strobe monolithic or the corresponding SDRAM of multi-disc, and according to writing mould
Corresponding SDRAM is written in the data that the buffer status of block feedback controls its caching；
The writing module is for receiving the write command, in the future according to the address range of the writing module inner buffer RAM
It is stored in its inner buffer from the data of external bus, executes the feedback to the buffer status, the data for executing the caching are write
Enter corresponding SDRAM；
If the control bus connects the state machine module and dry plate SDRAM, pass through it for the state machine module
If carrying out the gating control to the dry plate SDRAM or multi-disc controlling simultaneously；
If the data/address bus connects the read through model, writing module and dry plate SDRAM.
By upper, the present invention by using one based on the state machine module control module of three-stage design theory to multi-disc
SDRAM carries out gating Read-write Catrol while reading or writing control simultaneously, and meets requirement of the every SDRAM to refresh time, and not
It will cause loss of data, wider array of application scenarios can be applicable in, while checking read-write requests in Flushing status, can kept away
Exempt from state machine module and cannot respond to read-write requests in Flushing status, therefore the design of the state machine module can have preferably surely
It is qualitative, there are many advantages such as the higher, maintenance and upgrade convenient for the project later period of overall efficiency, meanwhile, multi-disc SDRAM is used
Module sharing method also has optimization layout and saves the advantage of resource.
Wherein, the state machine module uses three-stage state machine, and the first segment of state machine module is to utilize global system
Status register logic is described in clock, and the second segment of state machine module is to be retouched using combinational logic to state transfer
It states, the third section of state machine module is that output logic is described under the driving of global system clock.
By upper, although the describing mode coding of three-stage state machine is not very convenient, need to write in different positions defeated
Logic and state shift logic out, but since it is segmentation description, there is synthesizer to understand that accurate, overall efficiency is higher excellent
Gesture, while also eliminating using unstability existing for Combinational logic output.
Wherein, the inner buffer of the writing module includes the two panels caching RAM for constituting ping-pong buffer mechanism.
By upper, writing module caches RAM by internal two panels, can rattle and receive the data of external bus, and rattles and write
Enter SDRAM, transmission rate is higher and transmission is stablized.
Wherein, the inner buffer of the read through model includes the caching RAM of twice SDRAM quantity.
By upper, if also including that dry plate caches RAM, and the continuous read buffer data of high speed and low speed is supported to read inside read through model
Data cached two kinds of functions are responsible for table tennis by two panels caching RAM and receive a piece of SDRAM transmission under high speed read buffer mode
Data, and rattle and give to high speed data lines；Under low speed read buffer mode, it is responsible for receiving a piece of SDRAM biography by a piece of caching RAM
Defeated data, and give to external bus.
Wherein, the control bus includes the CMD_BUS control bus connecting with the state machine module and REF_BUS control
Bus processed, if the CMD_BUS control bus and REF_BUS control bus pass through Port Multiplier selection switch and the dry plate SDRAM
Pin connection；
The CMD_BUS control bus is described using three-stage state machine, if for controlling a piece of or dry plate SDRAM
Read-write and refresh access；
The REF_BUS control bus carries out a self-refresh bus for controlling SDRAM, i.e., total in CMD_BUS control
If line read and write access is a piece of or dry plate SDRAM, refresh function of the REF_BUS control bus to control other pieces SDRAM.
By upper, it can be achieved that realize gating read-write capability to multi-disc SDRAM while gating read-write capability.
Wherein, the data/address bus includes two-way three-state data/address bus, and data input pin connects the writing module, number
The read through model is connected according to output end, if the end IO connects the dry plate SDRAM.
By upper, if read through model and writing module are connect by two-way three-state data/address bus with dry plate SDRAM, wherein data are defeated
Enter end and connect the writing module, data output end connects the read through model, and the end IO can both carry out data write-in or carry out
Data output, to realize the read-write of SDRAM under the control of read through model and writing module.
The present invention also provides the reading data control method of SDRAM based on FPGA a kind of, using above-mentioned control system,
Include the following steps:
A1, Instruction decoding module decode the instruction from external bus, and configure the address SDRAM and be sent to shape
The address range of state machine module and configuration read through model inner buffer RAM are sent to read through model；
A2, it when decoding out reading instruction, executes and following reads step:
State machine module receives the reading instruction, according to the SDRAM address strobe monolithic or the corresponding SDRAM of multi-disc,
State machine module controls the inner buffer that read through model reads data deposit read through model from corresponding SDRAM,
State machine module controls the data readback of its caching to external bus or height according to the buffer status that read through model is fed back
Fast data line.
By upper, this method makes multi-disc SDRAM share a set of control module by using three-stage state machine design, from
And it realizes and the reading data of multi-disc SDRAM is controlled, there is optimization layout and save the advantage of resource.
Wherein, reading step described in step A2 includes:
The state machine module receives reading instruction and enters reading beginning state, under the driving of global system clock, according to institute
It states the corresponding SDRAM of SDRAM address strobe and successively sends activation, non-operation instruction and corresponding address；
The state machine module enters reading intermediate state, sends reading instruction and read address to corresponding SDRAM, gives read through model
It is enabled to send writing for its caching of write-in RAM；The read through model reads the data of corresponding SDRAM accordingly and is stored in inner buffer
RAM, when caching is write it is full when, send and cache full rising edge to state machine module；
When the read buffer that the state machine module receives read through model expires rising edge signal, the data of control read through model caching
Readback is to external bus or high speed data lines, after the completion of data readback, sends read buffer sky rising edge to state machine module.
By upper, this step can be activated according to the corresponding SDRAM of SDRAM address strobe, be refreshed, and by read address and reading
Instruction is sent to corresponding SDRAM, and writing for its caching RAM will be written and enable to be sent to read through model, control read through model in SDRAM
Data and be read out, and feed back buffer status to state machine module, state machine module can be realized according to buffer status to reading
The control of module, data are transferred out.
Wherein, step is read described in step A2 further include:
When the read through model is in low speed read buffer mode, corresponding SDRAM is stored using its internal a piece of caching RAM
Data send when a piece of caching RAM is filled with and cache full rising edge to state machine module, the state machine module enters
End state is read, under external bus clock driving, data are sent to external bus by read through model, are waited under the external bus
Reading instruction；
It is corresponding using its internal two panels caching RAM Pingpang Memory when the read through model is in high speed read buffer mode
The data of SDRAM, and readback is to high speed data lines send when data readback is completed and cache empty rising edge to state machine module,
The state machine module, which is again introduced into, reads beginning state, carries out reading data process next time.
By upper, read through model supports two kinds of reading data transmission modes, and due to the difference of data reading mode, state machine
There is also two ways, i.e. external bus starting or hardware self-starting for the Starting mode of read states.
The present invention also provides the data write-in control method of SDRAM based on FPGA a kind of, using above-mentioned control system,
Include the following steps:
B1, Instruction decoding module decode the instruction from external bus, and configure the address SDRAM and be sent to shape
The address range of state machine module and configurable write inside modules caching RAM are sent to writing module；
B2, when decoding out write command, execution writes step as follows:
Writing module receives the write command, the data from external bus is stored in its inner buffer, and buffer status is anti-
It is fed to state machine module:
State machine module is according to the SDRAM address strobe monolithic or the corresponding SDRAM of multi-disc, according to the caching of writing module
Corresponding SDRAM is written in the data that state controls its caching.
By upper, this method makes multi-disc SDRAM share a set of control module by using three-stage state machine design, from
And it realizes and controls or be written simultaneously control to the data strobe write-in of multi-disc SDRAM, there is optimization layout and save the excellent of resource
Gesture.
Wherein, writing step described in step B2 includes:
The writing module receives and caches the data from external bus by caching RAM table tennis, when caching is full, sends
Full rising edge is cached to state machine module；
The state machine module receives the full rising edge signal of the caching, and starting state machine module, which enters, writes beginning shape
State, under the driving of global system clock, according to the corresponding SDRAM of SDRAM address choice and successively send activate, non-operation instruction
With corresponding address；
The state machine module, which enters, writes intermediate state, sends write command and write address to corresponding SDRAM, gives writing module
The reading for sending its caching of reading RAM is enabled, and the data that control caches writing module are written in corresponding SDRAM；
When all corresponding SDRAM is written in the data that the writing module stores inner buffer RAM, send on caching sky
Edge is risen to state machine module, the state machine module, which enters, writes end state.
By upper, the write state of the inner buffer sky rising edge closed state machine module by writing module is realized, is completed pair
The data of SDRAM are written.
To sum up, the present invention has the advantage that compared with the prior art
Be compatible with the external bus control port on upper layer by Instruction decoding module, and by the control instruction of external bus into
Row decoding generates corresponding control signal and gives state machine module, read through model and writing module；Meanwhile the module also need to
The caching RAM of SDRAM and read through model and writing module provides corresponding access address；
The concentration and unified control to multi-disc SDRAM and to other modules, this design are realized by state machine module
Method keeps control logic relatively clear, convenient for verifying work such as the board tests of code；By using three-stage to state machine
Describing mode, so that code readable, compiler with higher can be comprehensive；By two different flushing policies, realize
There is controller wider array of SDRAM to drive reference clock frequency；
The ping-pong mechanism cached by two pieces of writing module can be realized external bus continuously to the write access of SDRAM, improve
Data transmission efficiency；
RAM is cached by muti-piece inside read through model, the parallel of data is read with synchronous in Lai Shixian multi-disc SDRAM, and energy
It is enough to be sent out with different frequencies；
By state machine module, the collaborative work of read through model, writing module, control bus, gating read and write access can be realized
Monolithic SDRAM reads while write access multi-disc SDRAM；
Detailed description of the invention
Fig. 1 is that the present invention is based on the schematic illustrations of the SDRAM control system of FPGA；
Fig. 2 is that the state of state machine module of the present invention shifts schematic diagram；
Fig. 3 is the design flow diagram of state machine module of the present invention；
Fig. 4 is state transition schematic diagram when present invention control SDRAM is written and read；
Fig. 5 is that the present invention is based on the flow charts of the reading data control method of the SDRAM of FPGA；
Fig. 6 is that the present invention is based on the flow charts of the data write-in control method of the SDRAM of FPGA.
Specific embodiment
In fpga logic design, finite state machine module FSM (Finite State Machine, FSM) be used to retouch
The timing behavior for stating various complexity is to carry out Digital Logic using HDL (Hardware Description Language, HDL)
One of the most important method of design.Finite state machine module can be divided into three types according to the difference of description method: one section
Formula state machine module, two-part state machine module and three-stage state machine.Due to one-part form state machine module describing mode not
Meet the code spice that timing and combinational logic is described separately, and code is tediously long, unintelligible, is unfavorable for additional constraint, no
Optimization conducive to synthesizer and placement-and-routing's device to design, so the describing mode is upper in the presence of limitation in application.Two-part state
The describing mode of machine module has the overall efficiency advantages such as preferably compared to one-part form state machine module, but there is also limitations, i.e., its
Output is to be described using combinational logic, and combinational logic presence is also easy to produce the unstable characteristics such as burr, and in FPGA/
Excessive combinational logic will affect in the logical devices such as CPLD (Complex Programmable Logic Device, CPLD)
The rate of realization.Although the describing mode coding of three-stage state machine is not very convenient, need to write output in different positions
Logic and state shift logic, but since it is segmentation description, there is synthesizer to understand accurate, the higher advantage of overall efficiency,
It also eliminates simultaneously using unstability existing for Combinational logic output.
Based on this, the SDRAM control system based on FPGA that the present invention provides a kind of, by using three-stage state machine control
Mode processed, and identical state machine module, read through model, writing module, Instruction decoding module are shared to multi-disc SDRAM.Using one
State machine module based on three-stage design theory carries out gating Read-write Catrol to multi-disc SDRAM chip while reading or writing simultaneously
There is synthesizer to understand many advantages such as accurate, the higher, maintenance and upgrade convenient for the project later period of overall efficiency for control；To more
Piece SDRAM uses module common way, can optimize layout and save resource.In the flushing policy selection of SDRAM, using being
1024 data lengths of every carry out within continuous read and write access after execute six self-refresh, every counting if without read write command
To execute after a certain period of time it is primary automatic refresh, such strategy not only can maximumlly realize the transmission of high-speed data communicate,
It is also able to satisfy requirement of the SDRAM to refresh time, and can reduce the power consumption of overall plan.The design is same using global clock
Step design, each module are driven using global system clock.There are two pieces of caching RAM, can rattle reception inside writing module
External bus data, and successively starting state machine moves in data in SDRAM.There is inside read through model multi-disc to cache RAM, every two
Piece RAM table tennis receives the data of a piece of SDRAM transmission, and continuous high speed output data, and can support different read buffers
Rate.
Referring to following attached drawing, the working principle of the invention is described in detail.
As shown in Figure 1, An embodiment provides a kind of SDRAM control system based on FPGA, including
FPGA unit, five SDRAM of the FPGA unit external connection, and control is written and read to it；
It wherein, include Instruction decoding module 100, state machine module 200, read through model 300, writing module inside FPGA unit
400, three-state data bus 500 and control bus 600；
Described instruction decoding module 100 is for decoding the instruction from external bus；
When decoding out reading instruction, described instruction decoding module 100 configures the address SDRAM and 300 inner buffer RAM of read through model
Address range, the state machine module 200 is for receiving the reading instruction, according to the SDRAM address strobe monolithic or more
The corresponding SDRAM of piece, control read through model 300 read the inner buffer of data deposit read through model 300, and root from corresponding SDRAM
The data readback of its caching is controlled to external bus or high speed data lines according to the buffer status that read through model 300 is fed back；
The read through model 300 is described from corresponding SDRAM reading data and according to slow inside the read through model for executing
Deposit the data readback that the address range of RAM is stored in its inner buffer, executes the feedback to the buffer status, executes the caching
To external bus or high speed data lines；
When decoding out write command, described instruction decoding module 100 configures the address SDRAM and 400 inner buffer RAM of writing module
Address range, the state machine module 200 be used for according to the SDRAM address strobe monolithic or the corresponding SDRAM of multi-disc, and
Corresponding SDRAM is written according to the data that the buffer status that writing module 400 is fed back controls its caching；
The writing module 400, will according to the address range of the writing module inner buffer RAM for receiving the write command
Data from external bus are stored in its inner buffer, execute the feedback to the buffer status, execute the data of the caching
Corresponding SDRAM is written；
The control bus 600 connects the state machine module 200 and five SDRAM, is used for the state machine module 200
The gating is carried out to five SDRAM by it to control, and specifically includes CMD_BUS control bus and REF_BUS control is total
Line, wherein CMD_BUS is described using three-stage state machine, if to control a piece of or dry plate SDRAM read-write and brush
New access；REF_BUS is that control SDRAM carries out a self-refresh bus, i.e., a piece of in state machine module controller read and write access
Or when multi-disc SDRAM, refresh function of the REF_BUS to control other pieces SDRAM, CMD_BUS and REF_BUS are being output to
It is to make can control by Port Multiplier selection switch before SDRAM pin, to realize gating read-write capabilities, simultaneously to five SDRAM
Read or write simultaneously function；
The three-state data bus 500 connects the read through model 300, writing module 400 and five SDRAM, for being read
Data transmission between module 300 or writing module 400 and five SDRAM, wherein the read through model 300 is by Instruction decoding module
Cache initialization address range of 100 its inside of control configuration, then under the control of state machine module 200, by a piece of SDRAM
In the inner buffer RAM of the data deposit read through model 300 of transmission, which supports continuous read buffer data of high speed and low
The data cached two kinds of functions of fast reading, under high speed read buffer mode, internal includes ten caching RAM, wherein every two panels caches
RAM is responsible for table tennis and receives the data of a piece of SDRAM transmission, and rattles and see off；Under low speed read buffer mode, inside include
Five caching RAM are responsible for receiving the data of a piece of SDRAM transmission by a piece of caching RAM, and by external bus under low speed rate
By data cached readback to outside；There is two panels to cache RAM inside the writing module 400, the reception that can rattle is from external bus
Data, and successively starting state machine module 200 moves in data in SDRAM, writing module only exports a circuit-switched data FIVE_BUS, should
Circuit-switched data FIVE_BUS is connected to the data output of five SDRAM, when carrying out data write-in, it is only necessary to by control bus
CMD_BUS and REF_BUS gating is sent on SDRAM control pin, and the gating read-write to five SDRAM can be realized and while selecting
Logical read-write capability.
As shown in Fig. 2, the design concept of above-mentioned state machine module 200 uses three-stage describing mode, the state machine module
200 first segment is that status register logic is described using global system clock, and second segment is using combinational logic pair
State transfer is described, and the third section of state machine module is to retouch under the driving of global system clock to output logic
It states.Its working condition can be subdivided into seven states, be reset state (RST), power-up state (init), 1 Flushing status respectively
(Ref_1), 6 Flushing status (Ref_6), wait state (idle), read states (RD), write state (WR)；
As shown in figure 3, the reset state (RST) of above-mentioned state machine module 200 is to revert to FPGA unit internal processes
The state of initialization；Enter power-up state after reset, that is, completes the power-on initialization operation to SDRAM；In power-up state
After, into a Flushing status, a self-refresh is carried out to all SDRAM in this state；If in a Flushing status
In when detecting read-write requests, can wait it is to be refreshed after jump directly to corresponding read states or write state；Once refreshing
After state, into wait state, read-write requests are waited；In the wait state, if without read-write requests and timing is to a timing
Between after, execute a self refresh operation into Flushing status, return to waiting for state later.When having read request or write request
When, into corresponding read states or write state；After to read or write, into six Flushing status, to read or write
Corresponding SDRAM executes six self-refresh；After to six self-refresh, state is returned to waiting for；
As shown in figure 4, write state (WR) is subdivided into and is write out in write state (WR) design of above-mentioned state machine module 200
Beginning state (WR_S) writes intermediate state (WR_M), writes end state (WR_E).External bus, which is responsible for for external data being stored in, writes mould
400 inner buffer of block, caching play the role of data transmission cross clock domain, then start shape by the rising edge of caching full scale will
The write state (WR) of state machine module 200, and enter and write beginning state (WR_S)；In the case where writing beginning state (WR_S), state machine mould
Block 200 global system clock (sys_clk) driving under, to SDRAM sequence issue activation (ACT), do-nothing operation (NOP) instruction and
Then corresponding address is jumped to by state writing (WR_S) and writes intermediate state (WR_M)；In the case where writing intermediate state (WR_M),
State machine module issues write command and write address, the data of above-mentioned 400 inner buffer of writing module are deposited according to write command and write address
Enter in corresponding SDRAM, when 400 inner buffer of writing module reads empty, write state terminated by the rising edge of the empty mark of caching, i.e., by
It writes intermediate state (WR_M) entrance and writes end state (WR_E)；End state (WR_E) state is being write, state machine module 200 is successively
Precharge (Precharge), do-nothing instruction (NOP) are issued, current line is closed and generates and write end mark；
As shown in figure 4, read states (RD) are subdivided into reading and are opened in read states (RD) design of above-mentioned state machine module 200
Beginning state (RD_S) reads intermediate state (RD_M), reads end state (RD_E).State machine module 200 is responsible for the number in SDRAM
According to deposit 300 inner buffer of read through model, caching plays the role of cross clock domain.Beginning state (RD_S) is being read, state machine module
200 under global system clock (sys_clk) driving, issues activation (ACT), do-nothing operation (NOP) instruction and phase to SDRAM sequence
The address answered, then state (RD_S) jumps to and reads intermediate state (RD_M) by reading；Read intermediate state (RD_M) state,
State machine module 200 issues reading instruction (RD) and read address, selectes the corresponding SDRAM of read address by control bus 600, will
Data in SDRAM are stored in 300 inner buffer of read through model, when the rising edge for caching full scale will arrives, by caching full scale will
Rising edge terminates read states, i.e., is entered by reading intermediate state (RD_M) and read end state (RD_E), is reading end state (RD_E)
State, state machine module 200 successively issue do-nothing instruction (NOP), do-nothing instruction (NOP), precharge (Precharge), do-nothing instruction
(NOP), and reading end mark is generated；
Two kinds of starting read states (RD) modes: external bus are supported in read states (RD) design of above-mentioned state machine module 200
Control starting read states and state machine module start read states automatically；
First way: it is to be issued to read enabled starting read states by external bus, that is, enters and read beginning state (RD_S)；So
State (RD_S) enters reading intermediate state (RD_M) by reading afterwards, and internal a piece of caching RAM is utilized to read the number in SDRAM
According to；When the rising edge that caching writes full scale will arrives, read states are exited, i.e., is entered by reading intermediate state (RD_M) and reads end state
(RD_E), the reading instruction next time from external bus is waited；
The second way: which will rely on first way, i.e. the read states of first time starting state machine module are
Made to can be carried out starting by the reading of external bus, it, will be in SDRAM under the control of external bus into beginning state (RD_S) is read
Data high-speed be stored in read through model 300 two panels inner buffer RAM, when caching is write it is full when, by caching full scale will rising edge control
Read states are exited, i.e., is entered by reading intermediate state (RD_M) and reads end state (RD_E)；Second and later starting state machine mould
The read states of block are to start read states after data cached reading is empty by the rising edge of the empty mark of caching, that is, enter and read beginning state
(RD_S)；Equally, and by the rising edge control of caching full scale will read states are exited, that is, enters and reads end state (RD_E).
The Design of Read-Write of above-mentioned state machine module, so that the SDRAM control system has biggish driving clock ranges, and
Meet requirement of the every SDRAM to refresh time, and not will cause loss of data, wider array of application scenarios can be applicable in, simultaneously
Read-write requests are checked in Flushing status, can be avoided state machine module in Flushing status cannot respond to read-write requests, because
The design of this state machine module can have preferable stability.
As shown in figure 5, being based on above-mentioned SDRAM control system, another embodiment of the present invention provides a kind of based on FPGA
SDRAM reading data control method, include the following steps:
S101: Instruction decoding module is decoded to the reading instruction received from external bus and is sent to state machine module,
And it configures the address SDRAM and is sent to state machine module and read through model；
This step includes following sub-step:
The reading instruction that external bus issues is sent to state machine module after decoding, and configures the transmission of the address SDRAM
Address range to state machine module and configuration read through model inner buffer RAM is sent to read through model；
State machine module enters beginning state of reading according to reading instruction, and under the driving of global system clock, gives reading address
Corresponding SDRAM issues activation, non-operation instruction and corresponding address.
In this step, after state machine module receives reading instruction and the address SDRAM from Instruction decoding module, opened into reading
Beginning state, and according to the address SDRAM control CMD_BUS control bus select the address SDRAM it is corresponding one or more pieces
SDRAM, and successively send activation, non-operation instruction and corresponding address, control of remaining SDRAM in CMD_REF control bus
System is lower to carry out self-refresh, still in wait state, does not send the instruction such as activation.
S102: the state machine module receives the reading instruction and enters read states, and read through model is according to the inner buffer RAM
Address range read SDRAM data deposit read through model inner buffer RAM and feed back buffer status to state machine module；
This step includes following sub-step:
The state machine module receives external bus instruction and enters reading beginning state, under the driving of global system clock,
According to SDRAM address choice SDRAM and successively send activation, non-operation instruction and corresponding address；
The state machine module enters reading intermediate state, sends reading instruction and read address to corresponding SDRAM, gives read through model
It is enabled to send writing for its caching of write-in RAM；
Writing for the read through model user equipment module transmission is enabled, the data of SDRAM is stored by caching RAM, when slow
It deposits when writing full, sends and cache full rising edge to state machine module；
When the read buffer that the state machine module receives read through model expires rising edge signal, into reading end state.
In this step, read through model supports high speed two kinds of functions of continuous read buffer data and low speed read buffer data, in high speed
Under read buffer mode, the data that table tennis receives SDRAM transmission are responsible for by two panels caching RAM, and rattle and send to high speed data lines, with
Data are handled for other modules inside FPGA unit；Under low speed read buffer mode, it is responsible for connecing by a piece of caching RAM
Receive SDRAM transmission data, and by external bus under low speed rate by data cached readback to the end PC.
S103: the state machine module controls read through model for the data readback of inner buffer to external bus or high-speed data
Line；
This step includes:
When the read through model is in low speed read buffer mode, corresponding SDRAM is stored using its internal a piece of caching RAM
Data send when a piece of caching RAM is filled with and cache full rising edge to state machine module, the state machine module enters
End state is read, under external bus clock driving, data are sent to external bus by read through model, are waited under the external bus
Reading instruction；
It is corresponding using its internal two panels caching RAM Pingpang Memory when the read through model is in high speed read buffer mode
The data of SDRAM, and readback is to high speed data lines send when data readback is completed and cache empty rising edge to state machine module,
The state machine module, which is again introduced into, reads beginning state, carries out reading data process next time.
In this step, read through model will cache full data readback to external bus or high speed data lines, when data readback is complete
At the inner buffer of read through model is in the empty mark of caching, if the reading of SDRAM whole resolution chart data is completed at this time, i.e.,
Controllable state machine module, which enters, reads end state, carries out six self-refresh to SDRAM；If not completing SDRAM whole test chart
The reading of graphic data, state machine module reenters beginning state of reading according to empty rising edge is cached at this time, and repeats above-mentioned step
Suddenly, until completing the reading of all resolution chart data.
This method is supported simultaneously to read the data of multi-disc SDRAM simultaneously, is cached by the way that multi-disc is arranged in read through model
RAM, and make can control by control bus CMD_BUS progress Port Multiplier selection and switch, it is corresponding that simultaneous selection reads address
SDRAM such as is refreshed, is activated at the movement, makes its response data read requests simultaneously.
As shown in fig. 6, being based on above-mentioned SDRAM control system, another embodiment of the present invention provides a kind of based on FPGA
SDRAM data write-in control method, include the following steps:
S201: Instruction decoding module carries out decoding to the write command received from external bus and is sent to writing module, and configures
The address SDRAM is sent to state machine module and the address range of configurable write inside modules caching RAM is sent to writing module；
In this step, after Instruction decoding module decodes the write command from external bus, it is sent to writing module,
And configure the address SDRAM be sent to state machine module and configurable write inside modules caching RAM address range be sent to writing module.
S202: the data from external bus are stored in inner buffer according to write command by writing module, and by caching on full
It rises and enters write state along starting state machine module；
This step includes following sub-step:
The writing module receives and caches the data from external bus by caching RAM table tennis, when caching is full, sends
Full rising edge is cached to state machine module；
The state machine module receives the full rising edge signal of the caching, and starting state machine module, which enters, writes beginning shape
State, under the driving of global system clock, according to the corresponding SDRAM of SDRAM address choice and successively send activate, non-operation instruction
With corresponding address.
In this step, writing module caches RAM table tennis by internal two panels and receives the data from external bus, works as caching
Man Shi sends and caches full rising edge to state machine module, and the caching that state machine module receives writing module expires rising edge, into writing out
Beginning state, and under the driving of global system clock, CMD_BUS control bus is controlled according to writing address and selects the writing address pair
The SDRAM answered successively sends activation, non-operation instruction and corresponding address, remaining SDRAM is in CMD_REF control bus
Control is lower to carry out self-refresh, still in wait state, does not send the instruction such as activation.
S203: the state machine module controls writing module, and corresponding SDRAM is written in the data of caching；
This step includes following sub-step:
The state machine module, which enters, writes intermediate state, sends write command and write address to corresponding SDRAM, gives writing module
The reading for sending its caching of reading RAM is enabled, and the data that control caches writing module are written in corresponding SDRAM；
When all corresponding SDRAM is written in the data that the writing module stores inner buffer RAM, send on caching sky
Rise along to state machine module, the state machine module enters end state of writing, wait external bus send next time data to writing
Then module expires the state entrance of rising edge state of a control machine module is write next time by the caching of writing module.
In this step, state machine module, which enters, writes intermediate state, sends write command and write address to corresponding SDRAM, gives
Reading that writing module sends its caching of reading RAM is enabled, and control writing module will cache full data, and table tennis is sent to selection
In SDRAM, when data are sent completely, writing module generates the empty mark of caching, sends the empty rising edge of caching to state machine module, shape
State machine module, which enters, writes end state, successively sends precharge (Precharge), do-nothing instruction (NOP), closes current line and generates
Write end mark.
To sum up, the present invention realizes the gating Read-write Catrol to multi-disc SDRAM while reading or writing simultaneously control, meets every
Requirement of the piece SDRAM to refresh time, and not will cause loss of data, while checking read-write requests in Flushing status,
It can be avoided state machine module and cannot respond to read-write requests in Flushing status, have overall efficiency higher, convenient for the project later period
The many advantages such as maintenance and upgrade, meanwhile, module sharing method is used to multi-disc SDRAM, also there is optimization layout and save money
The advantage in source.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in essence of the invention
Within mind and principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (11)
1. a kind of SDRAM control system based on FPGA, which is characterized in that if including FPGA unit and dry plate connected to it
SDRAM；
The FPGA unit includes Instruction decoding module, state machine module, read through model, writing module, data/address bus and control bus；
Described instruction decoding module is for decoding the instruction from external bus；
When decoding out reading instruction, described instruction decoding module configures the address model of the address SDRAM and read through model inner buffer RAM
It encloses, the state machine module is corresponding according to the SDRAM address strobe monolithic or multi-disc for receiving the reading instruction
SDRAM, control read through model read the inner buffer of data deposit read through model from corresponding SDRAM, and according to read through model feedback
Buffer status controls the data readback of its caching to external bus or high speed data lines；
The read through model is described from corresponding SDRAM reading data and according to the read through model inner buffer RAM's for executing
Address range is stored in its inner buffer, executes to the feedback of the buffer status, executes the data readback of the caching to outside
Bus or high speed data lines；
When decoding out write command, described instruction decoding module configures the address model of the address SDRAM and writing module inner buffer RAM
It encloses, the state machine module is used for according to the SDRAM address strobe monolithic or the corresponding SDRAM of multi-disc, and according to writing module
Corresponding SDRAM is written in the data that the buffer status of feedback controls its caching；
The writing module, will be from outer according to the address range of the writing module inner buffer RAM for receiving the write command
The data of portion's bus are stored in its inner buffer, execute the feedback to the buffer status, execute the data write-in pair of the caching
The SDRAM answered；
If the control bus connects the state machine module and dry plate SDRAM, for the state machine module by it to institute
If stating dry plate SDRAM to carry out the gating control or multi-disc while controlling；
If the data/address bus connects the read through model, writing module and dry plate SDRAM.
2. control system according to claim 1, which is characterized in that the state machine module uses three-stage state machine,
The first segment of state machine module is that status register logic is described using global system clock, the second of state machine module
Section is that state transfer is described using combinational logic, and the third section of state machine module is under the driving of global system clock
Output logic is described.
3. control system according to claim 1, which is characterized in that the inner buffer of the writing module includes constituting table tennis
The two panels of caching mechanism caches RAM.
4. control system according to claim 1, which is characterized in that the inner buffer of the read through model includes twice institute
State the caching RAM of SDRAM quantity.
5. control system according to claim 2, which is characterized in that the control bus includes and the state machine module
The CMD_BUS control bus and REF_BUS control bus of connection, the CMD_BUS control bus and REF_BUS control bus pass through
If Port Multiplier selection switch is connect with the pin of the dry plate SDRAM；
The CMD_BUS control bus is described using three-stage state machine, if for controlling a piece of or dry plate SDRAM reading
Write and refresh access；
The REF_BUS control bus carries out a self-refresh bus for controlling SDRAM, i.e., reads in CMD_BUS control bus
If write access is a piece of or dry plate SDRAM, refresh function of the REF_BUS control bus to control other pieces SDRAM.
6. control system according to claim 1, which is characterized in that the data/address bus includes that two-way three-state data are total
Line, data input pin connect the writing module, and data output end connects the read through model, if the end IO connects the dry plate
SDRAM。
7. a kind of reading data control method of the SDRAM based on FPGA, which is characterized in that use any institute of claim 1 to 6
The control system stated, includes the following steps:
A1, Instruction decoding module decode the instruction from external bus, and configure the address SDRAM and be sent to state machine
The address range of module and configuration read through model inner buffer RAM are sent to read through model；
A2, it when decoding out reading instruction, executes and following reads step:
State machine module receives the reading instruction, according to the SDRAM address strobe monolithic or the corresponding SDRAM of multi-disc,
State machine module controls the inner buffer that read through model reads data deposit read through model from corresponding SDRAM,
State machine module controls the data readback of its caching to external bus or high speed number according to the buffer status that read through model is fed back
According to line.
8. control method according to claim 7, which is characterized in that reading step described in step A2 includes:
The state machine module receives reading instruction and enters reading beginning state, under the driving of global system clock, according to described
The corresponding SDRAM of SDRAM address strobe simultaneously successively sends activation, non-operation instruction and corresponding address；
The state machine module enters reading intermediate state, sends reading instruction and read address to corresponding SDRAM, sends to read through model
It is enabled that writing for its caching RAM is written；The read through model reads the data of corresponding SDRAM accordingly and is stored in inner buffer RAM, when
When caching writes full, sends and cache full rising edge to state machine module；
When the read buffer that the state machine module receives read through model expires rising edge signal, the data readback of control read through model caching
To external bus or high speed data lines, after the completion of data readback, read buffer sky rising edge is sent to state machine module.
9. control method according to claim 8, which is characterized in that read step described in step A2 further include:
When the read through model is in low speed read buffer mode, the number of corresponding SDRAM is stored using its internal a piece of caching RAM
According to when a piece of caching RAM is filled with, transmission caches full rising edge to state machine module, and the state machine module enters reading knot
Pencil state, under external bus clock driving, data are sent to external bus by read through model, wait the external bus next time
Reading instruction；
When the read through model is in high speed read buffer mode, its internal corresponding SDRAM of two panels caching RAM Pingpang Memory is utilized
Data, and readback is to high speed data lines, when data readback is completed, sends and caches empty rising edge to state machine module, described
State machine module, which is again introduced into, reads beginning state, carries out reading data process next time.
10. a kind of data write-in control method of the SDRAM based on FPGA, which is characterized in that any using claim 1 to 6
The control system, includes the following steps:
B1, Instruction decoding module decode the instruction from external bus, and configure the address SDRAM and be sent to state machine
The address range of module and configurable write inside modules caching RAM are sent to writing module；
B2, when decoding out write command, execution writes step as follows:
Writing module receives the write command, the data from external bus is stored in its inner buffer, and buffer status is fed back to
State machine module:
State machine module is according to the SDRAM address strobe monolithic or the corresponding SDRAM of multi-disc, according to the buffer status of writing module
Corresponding SDRAM is written in the data for controlling its caching.
11. control method according to claim 10, which is characterized in that writing step described in step B2 includes:
The writing module receives and caches the data from external bus by caching RAM table tennis, when caching is full, sends caching
Expire rising edge to state machine module；
The state machine module receives the full rising edge signal of the caching, and starting state machine module, which enters, writes beginning state,
Under the driving of global system clock, according to the corresponding SDRAM of SDRAM address choice and successively send activate, non-operation instruction and phase
The address answered；
The state machine module, which enters, writes intermediate state, sends write command and write address to corresponding SDRAM, sends to writing module
It is enabled to read its reading for caching RAM, the data that control caches writing module are written in corresponding SDRAM；
When all corresponding SDRAM is written in the data that the writing module stores inner buffer RAM, sends and cache empty rising edge
To state machine module, the state machine module, which enters, writes end state.
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