CN210573757U - Hardware device for realizing SDRAM control system based on FPGA - Google Patents

Abstract

The utility model provides a hardware device for realizing SDRAM control system based on FPGA, which comprises an FPGA unit and a plurality of SDRAM connected with the FPGA unit; the FPGA unit comprises an instruction decoding module, a state machine module, a reading module, a writing module, a data bus and a control bus. The utility model discloses an adopt a state machine module based on syllogic design theory to gate read-write control to multi-disc SDRAM, read simultaneously or write control simultaneously, and satisfy every SDRAM to the requirement of refresh time, and can not cause data loss, can be suitable for wider application scene, the state is refreshing and is being examined the read-write request simultaneously, can avoid the state machine module to be in the unable response read-write request of state of refreshing, consequently, the design of this state machine module can have better stability, it is higher to have comprehensive efficiency, be convenient for a great deal of advantages such as maintenance and the upgrading in project later stage, still have the advantage of optimizing the overall arrangement and saving resources simultaneously.

Description

Hardware device for realizing SDRAM control system based on FPGA

Technical Field

The invention relates to the field of SDRAM controller design in a digital IC test system, in particular to a hardware device for realizing an SDRAM control system based on an FPGA.

Background

At present, in a digital IC test system, it is necessary to store a large amount of graphic data in an external memory, read the graphic data from the external memory at the time of chip test, and test the functions of a digital chip. SDRAM (synchronous dynamic Random Access Memory) is a high-speed, high-capacity dynamic Memory, and has a much larger capacity and a relatively lower price than SRAM, so that it is widely used in digital IC test systems and other industrial fields. Although some general SDRAM controllers exist in the market at present, the advantages of complex arrangement, poor code readability, more modules, incapability of aiming at specific systems and incapability of exerting the advantages of SDRAM exist. Furthermore, most of the SDRAM controllers in the market are designed for one SDRAM, and if a plurality of SDRAMs are to be controlled simultaneously on an FPGA (Field Programmable Gate Array) chip, multiple instantiations are required, which causes great difficulty in maintaining and upgrading the late codes.

For example, in patent document CN106649157A, "SDRAM control system based on FPGA", an interface conversion module is used to convert different SDRAM controller IP interfaces of different FPGA manufacturers into a general RAM (Random Access Memory) interface, so that SDRAM memories can be used in FPGAs of different manufacturers, but the design scheme based on Xilinx SDRAM controller IP cannot meet the complex use requirement of SDRAM in a digital IC test system.

In a digital IC test system, the write burst access of any address of SDRAM with any length needs to be realized, and a control bus of the test system needs to be compatible with a module on the upper layer; when reading and accessing the SDRAM, the read burst access with any address and any length needs to be realized, and data is read from the SDRAM according to different rates; in addition, in a digital IC test system, a plurality of SDRAMs are often required, so that the controller needs to be able to control a plurality of SDRAMs simultaneously and satisfy the refresh requirements of each SDRAM under different access conditions. The requirement for various and complicated SDRAM uses in the digital IC test system is not realized by the general SDRAM control scheme, so a specially designed SDRAM control system is needed.

Disclosure of Invention

In view of the above, a main object of the present invention is to provide a hardware device for implementing an SDRAM control system based on an FPGA, in which a state machine module control module based on a three-stage design theory is used to perform gating read-write control, simultaneous read or simultaneous write control on multiple SDRAMs, and meet the requirement of each SDRAM on refresh time, without data loss, and thus being applicable to a wider application scenario, and meanwhile, the read-write request is checked in a refresh state, and it is able to avoid that the state machine module cannot respond to the read-write request in the refresh state, so the design of the state machine module has better stability, and has many advantages such as higher comprehensive efficiency, convenience for later maintenance and upgrade of a project, and meanwhile, the module sharing mode is used for multiple SDRAMs, and further has advantages of layout optimization and resource saving.

The invention provides a hardware device for realizing an SDRAM control system based on an FPGA, which comprises an FPGA unit and a plurality of SDRAMs connected with the FPGA unit;

the FPGA unit comprises an instruction decoding module, a state machine module, a reading module, a writing module, a data bus and a control bus;

the instruction decoding module is used for decoding an instruction from an external bus;

when a reading instruction is decoded, the instruction decoding module configures an SDRAM address and an address range of a cache RAM inside the reading module, the state machine module is used for receiving the reading instruction, strobes a single chip or multiple chips of corresponding SDRAM according to the SDRAM address, controls the reading module to read data from the corresponding SDRAM and store the data into an internal cache of the reading module, and controls the cached data to be read back to an external bus or a high-speed data line according to a cache state fed back by the reading module;

the reading module is used for executing the data read from the corresponding SDRAM and storing the data into an internal cache according to the address range of an internal cache RAM of the reading module, executing feedback of the cache state and executing data read back of the cache to an external bus or a high-speed data line;

when a write command is decoded, the command decoding module configures an SDRAM address and an address range of a cache RAM inside the write module, and the state machine module is used for gating one or more corresponding SDRAMs according to the SDRAM address and controlling the cached data to be written into the corresponding SDRAMs according to the cache state fed back by the write module;

the writing module is used for receiving the writing instruction, storing data from an external bus into an internal cache according to the address range of an internal cache RAM of the writing module, executing feedback of the cache state, and executing the writing of the cached data into a corresponding SDRAM;

the control bus is connected with the state machine module and the plurality of SDRAM and is used for the state machine module to carry out gating control or multi-chip simultaneous control on the plurality of SDRAM through the control bus;

the data bus is connected with the reading module, the writing module and the plurality of SDRAM.

Therefore, the invention adopts the state machine module control module based on the three-section design theory to carry out gating read-write control, simultaneous read or simultaneous write control on a plurality of SDRAM, meets the requirement of each SDRAM on the refresh time, does not cause data loss, can be suitable for wider application scenes, and simultaneously inspects the read-write request in the refresh state, and can avoid the state machine module from failing to respond to the read-write request in the refresh state, so the design of the state machine module can have better stability, has the advantages of higher comprehensive efficiency, convenience for later maintenance and upgrading of projects and the like, and simultaneously adopts a module sharing mode for a plurality of SDRAM, and also has the advantages of optimizing layout and saving resources.

The state machine module adopts a three-section state machine, the first section of the state machine module describes the logic of the state register by using a global system clock, the second section of the state machine module describes the state transition by using combinational logic, and the third section of the state machine module describes the output logic under the driving of the global system clock.

Therefore, although the three-section state machine is not very convenient to encode and needs to write output logic and state transition logic at different positions, the three-section state machine has the advantages of accurate comprehension and high synthesis efficiency of a synthesizer due to the fact that the three-section state machine is described in a section mode, and meanwhile instability existing in output by adopting combinational logic is eliminated.

The internal cache of the writing module comprises two cache RAMs forming a ping-pong cache mechanism.

Therefore, the writing module can receive data of an external bus in a ping-pong manner through the two internal cache RAMs and write the data into the SDRAM in a ping-pong manner, and the transmission rate is high and the transmission is stable.

Wherein the internal cache of the read module comprises twice the number of cache RAMs as the number of SDRAM.

In the read mode, the two cache RAMs are responsible for ping-pong receiving of data transmitted by one SDRAM and ping-pong sending to a high-speed data line; in the low-speed reading cache mode, one cache RAM is responsible for receiving data transmitted by one SDRAM and sending the data to an external bus.

The control BUS comprises a CMD _ BUS control BUS and a REF _ BUS control BUS which are connected with the state machine module, and the CMD _ BUS control BUS and the REF _ BUS control BUS are connected with pins of the plurality of SDRAMs through a multiplexer selection switch;

the CMD _ BUS control BUS is described by a three-section state machine and is used for controlling the read-write and refresh access of one or a plurality of SDRAM (synchronous dynamic random access memories);

the REF _ BUS control BUS is used for controlling the SDRAM to carry out a self-refresh BUS, namely when the CMD _ BUS control BUS accesses one or a plurality of SDRAM, the REF _ BUS control BUS is used for controlling the refresh function of other SDRAM.

Therefore, the gating read-write function and the simultaneous gating read-write function of the plurality of SDRAM can be realized.

The data bus comprises a bidirectional three-state data bus, the data input end of the bidirectional three-state data bus is connected with the writing module, the data output end of the bidirectional three-state data bus is connected with the reading module, and the IO end of the bidirectional three-state data bus is connected with the plurality of SDRAM.

The read module and the write module are connected with a plurality of SDRAM through bidirectional three-state data buses, wherein a data input end is connected with the write module, a data output end is connected with the read module, and an IO end can write data and output data, so that the read and write of the SDRAM are realized under the control of the read module and the write module.

The invention also provides a data reading control method of SDRAM based on FPGA, which adopts the control system, and comprises the following steps:

a1, the instruction decoding module decodes the instruction from the external bus, configures SDRAM address and sends the SDRAM address to the state machine module and configures the address range of the cache RAM in the reading module and sends the address range to the reading module;

a2, when the reading instruction is decoded, executing the following reading steps:

the state machine module receives the reading instruction, strobes a single chip or a plurality of corresponding SDRAM according to the SDRAM address,

the state machine module controls the reading module to read data from the corresponding SDRAM and store the data into the internal cache of the reading module,

the state machine module controls the cached data to be read back to an external bus or a high-speed data line according to the cache state fed back by the reading module.

Therefore, the method adopts the design of the three-section state machine, and the plurality of SDRAM shares one set of control module, thereby realizing the data reading control of the plurality of SDRAM and having the advantages of optimizing the layout and saving resources.

Wherein, the reading step in step A2 includes:

the state machine module receives a read instruction and enters a read starting state, and under the drive of a global system clock, corresponding SDRAM is gated according to the SDRAM address and activation and no-load operation instructions and corresponding addresses are sequentially sent;

the state machine module enters a read intermediate state, sends a read instruction and a read address to the corresponding SDRAM, and sends a write enable written into the cache RAM of the read module; the reading module reads the corresponding SDRAM data and stores the data into an internal cache RAM, and when the cache is full, a cache full rising edge is sent to the state machine module;

and the state machine module controls the data cached by the reading module to be read back to an external bus or a high-speed data line when receiving a reading cache full rising edge signal of the reading module, and sends a reading cache empty rising edge to the state machine module after the data is read back.

Therefore, the step can be used for activating and refreshing the corresponding SDRAM according to the SDRAM address gating, sending the read address and the read command to the corresponding SDRAM, sending the write enable written in the cache RAM to the read module, controlling the read module to read the data in the SDRAM and feeding the cache state back to the state machine module, and the state machine module can realize the control of the read module according to the cache state and transmit the data.

Wherein, the reading step in step a2 further includes:

when the read module is in a low-speed read cache mode, a piece of cache RAM in the read module is used for storing corresponding SDRAM data, when the piece of cache RAM is full, a cache full rising edge is sent to the state machine module, the state machine module enters a read ending state, and under the drive of an external bus clock, the read module sends the data to an external bus to wait for a next read instruction of the external bus;

when the reading module is in a high-speed reading cache mode, ping-pong storage of corresponding SDRAM data is carried out by utilizing two internal cache RAMs, the data is read back to a high-speed data line, when the data read back is completed, a cache empty rising edge is sent to the state machine module, and the state machine module enters a reading starting state again to carry out the next data reading process.

In the above, the read module supports two data reading transmission modes, and because of the difference in the data reading modes, there are also two modes for starting the state machine reading state, namely, external bus starting or hardware self-starting.

The invention also provides a data writing control method of SDRAM based on FPGA, which adopts the control system, and comprises the following steps:

b1, the instruction decoding module decodes the instruction from the external bus, configures SDRAM address and sends the SDRAM address to the state machine module and configures the address range of the cache RAM in the writing module and sends the address range to the writing module;

b2, when the writing instruction is decoded, the following writing steps are executed:

the writing module receives the writing instruction, stores data from an external bus into an internal cache thereof, and feeds back the cache state to the state machine module:

and the state machine module strobes a single chip or a plurality of corresponding SDRAM (synchronous dynamic random access memory) according to the SDRAM address, and controls the cached data to be written into the corresponding SDRAM according to the cache state of the writing module.

Therefore, the method adopts the design of the three-section state machine, and leads a plurality of SDRAM to share one set of control module, thereby realizing the data strobe write-in control or simultaneous write-in control of the plurality of SDRAM, and having the advantages of optimizing the layout and saving resources.

Wherein the writing step of step B2 includes:

the writing module receives and caches data from an external bus through a cache RAM ping-pong, and sends a cache full rising edge to the state machine module when the cache is full;

the state machine module receives the cache full rising edge signal, starts the state machine module to enter a write starting state, selects a corresponding SDRAM according to the SDRAM address and sequentially sends an activation instruction and a no-operation instruction and corresponding addresses under the drive of a global system clock;

the state machine module enters a write intermediate state, sends a write command and a write address to the corresponding SDRAM, sends a read enable for reading the cache RAM of the write module to the write module, and controls to write the data cached by the write module into the corresponding SDRAM;

and when the writing module writes all the data stored in the internal cache RAM into the corresponding SDRAM, sending a cache empty rising edge to the state machine module, and enabling the state machine module to enter a writing ending state.

Therefore, the writing state of the state machine module is closed through the internal cache empty rising edge of the writing module, and the data writing of the SDRAM is completed.

In conclusion, compared with the prior art, the invention has the following advantages:

the command decoding module is compatible with an upper external bus control port, decodes the control command of the external bus, generates a corresponding control signal and sends the control signal to the state machine module, the reading module and the writing module; meanwhile, the module also needs to provide corresponding access addresses for the SDRAM and cache RAMs of the reading module and the writing module;

the centralized and unified control of a plurality of SDRAM modules and other modules is realized through the state machine module, the design method ensures that the control logic is clearer, and the verification work such as board test of codes is facilitated; by adopting a three-section description mode for the state machine, the code has higher readability and the compiler can be integrated; the controller has a wider SDRAM driving clock frequency range through two different refreshing strategies;

through a ping-pong mechanism of two caches of the writing module, the continuous writing access of an external bus to the SDRAM can be realized, and the data transmission efficiency is improved;

the data in the multiple SDRAM are read in parallel and synchronously by the multiple cache RAMs in the reading module, and can be sent out along with different frequencies;

through the cooperative work of the state machine module, the reading module, the writing module and the control bus, the gating reading and writing access to a single SDRAM or the simultaneous reading and writing access to a plurality of SDRAMs can be realized;

drawings

FIG. 1 is a schematic diagram of an SDRAM control system based on an FPGA according to the present invention;

FIG. 2 is a state transition diagram of the state machine module of the present invention;

FIG. 3 is a flow chart of the design of the state machine module of the present invention;

FIG. 4 is a diagram illustrating state jumps when controlling SDRAM to perform read/write operations according to the present invention;

FIG. 5 is a flow chart of the SDRAM data read control method based on FPGA of the present invention;

FIG. 6 is a flow chart of the SDRAM data write control method based on FPGA according to the present invention.

Detailed Description

In FPGA logic design, a Finite State Machine module FSM (FSM) is used to describe various complex timing behaviors, and is one of the most important methods for digital logic design using HDL (Hardware Description Language). Finite state machine modules can be classified into three types according to different description methods: a one-stage state machine module, a two-stage state machine module, and a three-stage state machine. The description mode of the one-section state machine module does not conform to the code style of separately describing time sequence and combinational logic, is long and unclear in code, is not beneficial to additional constraint, and is not beneficial to design optimization of a synthesizer and a layout router, so that the description mode has limitations in application. Compared with a one-segment state machine module, the description mode of the two-segment state machine module has the advantages of better comprehensive efficiency and the like, but has limitations that the output of the two-segment state machine module is described by adopting combinational Logic, unstable characteristics such as easiness in generating burrs and the like exist in the combinational Logic, and the realization rate is influenced by excessive combinational Logic in Logic devices such as an FPGA (field Programmable gate array)/CPLD (Complex Programmable Logic Device, CPLD). Although the three-section state machine is not very convenient to encode and needs to write output logic and state transition logic at different positions, the three-section state machine has the advantages of accurate comprehension and high synthesis efficiency of a synthesizer due to the fact that the three-section state machine is described in a section mode, and meanwhile instability existing in output by adopting combinational logic is eliminated.

Based on the control method, the SDRAM control system based on the FPGA shares the same state machine module, the read module, the write module and the instruction decoding module for a plurality of SDRAM by adopting a three-section state machine control mode. The state machine module based on the three-section design theory is adopted to carry out gating read-write control, simultaneous read control or simultaneous write control on a plurality of SDRAM chips, and the method has the advantages of accurate comprehension of a synthesizer, higher comprehensive efficiency, convenience for later maintenance and upgrading of projects and the like; and a module common mode is adopted for a plurality of SDRAM, so that the layout can be optimized and the resources can be saved. In the aspect of the refresh strategy selection of the SDRAM, six times of self-refresh is executed after continuous read-write access within 1024 data lengths is carried out, and if no read-write command exists, automatic refresh is executed once after a certain time is counted. The design adopts a global clock synchronization design, and all modules are driven by a global system clock. The writing module is internally provided with two cache RAMs which can receive external bus data in a ping-pong manner and sequentially start a state machine to move the data into the SDRAM. The reading module is internally provided with a plurality of cache RAMs, each two RAM ping-pong receives data transmitted by one SDRAM, continuously outputs the data at high speed, and can support different reading and caching rates.

The operation of the present invention will be described in detail with reference to the following drawings.

As shown in fig. 1, an embodiment of the present invention provides an SDRAM control system based on an FPGA, which includes an FPGA unit, and the FPGA unit is externally connected to five SDRAMs and performs read-write control on the SDRAMs;

the FPGA unit internally comprises an instruction decoding module 100, a state machine module 200, a reading module 300, a writing module 400, a three-state data bus 500 and a control bus 600;

the instruction decoding module 100 is configured to decode an instruction from an external bus;

when a read instruction is decoded, the instruction decoding module 100 configures an SDRAM address and an address range of a cache RAM inside the read module 300, and the state machine module 200 is configured to receive the read instruction, gate a single chip or multiple chips of corresponding SDRAMs according to the SDRAM address, control the read module 300 to read data from the corresponding SDRAMs and store the data in an internal cache of the read module 300, and control the cached data to read back to an external bus or a high-speed data line according to a cache state fed back by the read module 300;

the read module 300 is configured to execute the reading of data from the corresponding SDRAM and store the data in its internal cache according to an address range of an internal cache RAM of the read module, execute feedback of the cache state, and execute the read-back of the cached data to an external bus or a high-speed data line;

when a write command is decoded, the command decoding module 100 configures an SDRAM address and an address range of a cache RAM inside the write module 400, and the state machine module 200 is configured to gate a single chip or multiple chips of corresponding SDRAMs according to the SDRAM address and control cached data to be written into the corresponding SDRAMs according to a cache state fed back by the write module 400;

the write module 400 is configured to receive the write instruction, store data from an external bus into an internal cache thereof according to an address range of an internal cache RAM of the write module, perform feedback on a cache state, and write the cached data into a corresponding SDRAM;

the control BUS 600 is connected with the state machine module 200 and five SDRAMs, and is used for the state machine module 200 to perform the gating control on the five SDRAMs through the control BUS, and specifically comprises a CMD _ BUS control BUS and a REF _ BUS control BUS, wherein the CMD _ BUS is described by using a three-stage state machine and is used for controlling the read-write and refresh access of one or more SDRAMs; the REF _ BUS is used for controlling the SDRAM to carry out a self-refreshing BUS, namely when the state machine module controller reads and writes one or more SDRAM (synchronous random access memories), the REF _ BUS is used for controlling the refreshing function of other SDRAM (synchronous random access memories), and the CMD _ BUS and the REF _ BUS are enabled and controlled by the multiplexer selector switch before being output to the SDRAM pin, so that the gating reading and writing function, the simultaneous reading or simultaneous writing function are realized on five SDRAM (synchronous random access memories);

the tri-state data bus 500 is connected to the read module 300, the write module 400 and five SDRAMs, and is used for data transmission between the read module 300 or the write module 400 and the five SDRAMs, wherein the read module 300 is controlled by the command decoding module 100 to configure an internal cache initialization address range, and then under the control of the state machine module 200, data transmitted by one SDRAM is stored in an internal cache RAM of the read module 300, the read module 300 supports two functions of high-speed continuous read cache data and low-speed read cache data, and under a high-speed read cache mode, the read module contains ten cache RAMs, wherein each two cache RAMs are responsible for ping-pong receiving data transmitted by one SDRAM and sending out; under the low-speed reading cache mode, the internal part of the low-speed reading cache mode comprises five cache RAMs, one cache RAM is responsible for receiving data transmitted by one SDRAM, and an external bus reads the cache data back to the outside at a low speed rate; the internal part of the writing module 400 is provided with two pieces of cache RAMs which can receive data from an external BUS in a ping-pong manner, the state machine module 200 is sequentially started to move the data into the SDRAM, the writing module only outputs one path of data FIVE _ BUS which is connected to the data output ports of the FIVE SDRAM, and when data writing is carried out, only the control buses CMD _ BUS and REF _ BUS need to be gated and transmitted to the SDRAM control pin, so that the gating read-write and simultaneous gating read-write functions of the FIVE SDRAM can be realized.

As shown in fig. 2, the design concept of the state machine module 200 is described in a three-stage manner, a first stage of the state machine module 200 describes the logic of the state register by using a global system clock, a second stage describes the state transition by using combinational logic, and a third stage of the state machine module describes the output logic under the driving of the global system clock. The working state of the device can be subdivided into seven states, namely a Reset State (RST), a power-on state (init), a 1-time refreshing state (Ref _1), a 6-time refreshing state (Ref _6), a waiting state (idle), a reading state (RD) and a writing state (WR);

as shown in fig. 3, the Reset State (RST) of the state machine module 200 is a state that causes the internal program of the FPGA unit to return to initialization; entering a power-on state after the resetting is finished, namely completing the power-on initialization operation of the SDRAM; after the power-on state is finished, entering a one-time refreshing state, and performing one-time self-refreshing on all the SDRAM in the state; if a read-write request is detected in a one-time refreshing state, directly jumping to a corresponding read state or write state after the refreshing is finished; after the refreshing state is finished, entering a waiting state and waiting for a read-write request; in the waiting state, if there is no read-write request and the timing reaches a certain time, entering a refresh state to execute a self-refresh operation, and then returning to the waiting state. When a read request or a write request exists, entering a corresponding read state or write state; after the read or write operation is finished, entering a six-time refreshing state, and executing six times of self-refreshing on the SDRAM corresponding to the read or write operation; after the six self-refreshing operations are finished, returning to a waiting state;

as shown in fig. 4, in the write state (WR) design of the state machine module 200, the write state (WR) is subdivided into a write start state (WR _ S), a write middle state (WR _ M), and a write end state (WR _ E). The external bus is responsible for storing external data into the internal cache of the writing module 400, the cache plays a role of data transmission clock domain crossing, then the rising edge of the cache full flag starts the writing state (WR) of the state machine module 200, and enters the writing starting state (WR _ S); in a write start state (WR _ S), the state machine module 200 sequentially issues an Active (ACT), a No Operation (NOP) command and a corresponding address to the SDRAM under the drive of a global system clock (sys _ clk), and then jumps to a write middle state (WR _ M) from the write start state (WR _ S); in the write intermediate state (WR _ M), the state machine module sends out a write command and a write address, the data cached in the write module 400 is stored in the corresponding SDRAM according to the write command and the write address, and when the cache in the write module 400 is empty, the write state is ended by the rising edge of the cache empty flag, that is, the write intermediate state (WR _ M) enters the write end state (WR _ E); in the write end state (WR _ E), the state machine module 200 sequentially issues a Precharge (Precharge) and a null command (NOP), closes the current row and generates a write end flag;

as shown in fig. 4, in the design of the read state (RD) of the state machine module 200, the read state (RD) is subdivided into a read start state (RD _ S), a read middle state (RD _ M), and a read end state (RD _ E). The state machine module 200 is responsible for storing the data in the SDRAM into the internal cache of the read module 300, and the cache plays a role of crossing clock domains. In the read start state (RD _ S), the state machine module 200 sequentially issues an Active (ACT), a No Operation (NOP) command and corresponding addresses to the SDRAM under the drive of the global system clock (sys _ clk), and then jumps to the read intermediate state (RD _ M) from the read start state (RD _ S); in the read intermediate state (RD _ M), the state machine module 200 sends a read command (RD) and a read address, selects the SDRAM corresponding to the read address through the control bus 600, stores the data in the SDRAM into the internal cache of the read module 300, when the rising edge of the cache full flag comes, the read state is ended by the rising edge of the cache full flag, that is, the read intermediate state (RD _ M) enters the read end state (RD _ E), and in the read end state (RD _ E), the state machine module 200 sequentially sends out an empty command (NOP), a Precharge (Precharge), and an empty command (NOP) and generates a read end flag;

the read state (RD) design of the state machine module 200 supports two ways of starting the read state (RD): the external bus controls the starting of the reading state and the state machine module automatically starts the reading state;

the first mode is as follows: the external bus sends out a read enable starting read state, namely, a read start state (RD _ S) is entered; then, the read starting state (RD _ S) enters a read intermediate state (RD _ M), and an internal piece of cache RAM is used for reading data in the SDRAM; when the rising edge of the cache full-writing mark comes, exiting the reading state, namely entering a reading ending state (RD _ E) from a reading intermediate state (RD _ M) and waiting for the next reading instruction from the external bus;

the second mode is as follows: the method is based on a first mode, namely, the read state of a first startup state machine module is started by the read enable of an external bus, a read start state (RD _ S) is entered, data in SDRAM is stored into two internal cache RAMs of a read module 300 at a high speed under the control of the external bus, when the cache is full, the read state is exited by the control of the rising edge of a cache full mark, namely, a read intermediate state (RD _ M) enters a read end state (RD _ E); the reading state of the second and later starting state machine module is that after the cache data is read empty, the reading state is started by the rising edge of the cache empty mark, namely, the reading starting state (RD _ S) is entered; likewise, the rising edge of the cache full flag controls the exit of the read state, i.e., the entry into the read complete state (RD _ E).

The read-write design of the state machine module enables the SDRAM control system to have a large driving clock range, meets the requirement of each piece of SDRAM on the refresh time, does not cause data loss, can be suitable for a wider application scene, and meanwhile checks the read-write request in the refresh state, so that the situation that the state machine module cannot respond to the read-write request in the refresh state can be avoided, and the design of the state machine module can have good stability.

As shown in fig. 5, based on the SDRAM control system, another embodiment of the present invention provides a data reading control method for an SDRAM based on an FPGA, including the following steps:

s101: the instruction decoding module decodes the read instruction received from the external bus and sends the read instruction to the state machine module, and configures an SDRAM (synchronous dynamic random access memory) address to send to the state machine module and the read module;

the method comprises the following substeps:

after being decoded, a read instruction sent by an external bus is sent to a state machine module, and an SDRAM (synchronous dynamic random access memory) address is configured to be sent to the state machine module and an address range of a cache RAM (random access memory) in the read module is configured to be sent to the read module;

and the state machine module enters a read starting state according to the read instruction and sends an activation and idle operation instruction and a corresponding address to the SDRAM corresponding to the read address under the drive of the global system clock.

In this step, after receiving the read command and the SDRAM address from the command decoding module, the state machine module enters a read start state, controls the CMD _ BUS control BUS to select one or more SDRAMs corresponding to the SDRAM address according to the SDRAM address, and sequentially sends an activate and idle command and corresponding addresses, and the remaining SDRAMs are self-refreshed under the control of the CMD _ REF control BUS, still in a wait state, and do not send commands such as activate.

S102: the state machine module receives the reading instruction and enters a reading state, and the reading module reads the data of the SDRAM according to the address range of the internal cache RAM, stores the data into the internal cache RAM of the reading module and feeds the cache state back to the state machine module;

the method comprises the following substeps:

the state machine module receives an external bus instruction to enter a read starting state, selects an SDRAM (synchronous dynamic random access memory) according to an SDRAM address and sequentially sends an activation instruction, a no-operation instruction and a corresponding address under the drive of a global system clock;

the state machine module enters a read intermediate state, sends a read instruction and a read address to the corresponding SDRAM, and sends a write enable written into the cache RAM of the read module;

the read module receives the write enable sent by the state machine module, stores data of the SDRAM through the cache RAM, and sends a cache full rising edge to the state machine module when the cache is full;

and the state machine module enters a reading ending state when receiving a reading cache full rising edge signal of the reading module.

In the step, the reading module supports two functions of high-speed continuous reading of cache data and low-speed reading of cache data, and in a high-speed cache reading mode, two cache RAMs are responsible for ping-pong receiving of data transmitted by an SDRAM (synchronous dynamic random access memory) and ping-pong sending of the data to a high-speed data line so as to enable other modules in the FPGA unit to process the data; in the low-speed reading cache mode, one cache RAM is responsible for receiving data transmitted by the SDRAM, and the cache data is read back to the PC end by an external bus at a low speed.

S103: the state machine module controls the reading module to read back the data cached in the internal cache to an external bus or a high-speed data line;

the method comprises the following steps:

when the read module is in a low-speed read cache mode, a piece of cache RAM in the read module is used for storing corresponding SDRAM data, when the piece of cache RAM is full, a cache full rising edge is sent to the state machine module, the state machine module enters a read ending state, and under the drive of an external bus clock, the read module sends the data to an external bus to wait for a next read instruction of the external bus;

when the reading module is in a high-speed reading cache mode, ping-pong storage of corresponding SDRAM data is carried out by utilizing two internal cache RAMs, the data is read back to a high-speed data line, when the data read back is completed, a cache empty rising edge is sent to the state machine module, and the state machine module enters a reading starting state again to carry out the next data reading process.

In the step, the reading module reads back the data which is fully cached to an external bus or a high-speed data line, when the data read back is completed, the internal cache of the reading module is in a cache empty mark, and at the moment, if the reading of all the test pattern data of the SDRAM is completed, the state machine module can be controlled to enter a reading ending state, and the SDRAM is self-refreshed for six times; if the reading of all the test pattern data of the SDRAM is not finished, the state machine module enters the reading starting state again according to the cache empty rising edge at the moment, and the steps are repeated until the reading of all the test pattern data is finished.

The method supports simultaneous reading of data of a plurality of SDRAM, and can simultaneously respond to a data reading request by arranging a plurality of cache RAMs in a reading module, performing multiplexer selection and switch enabling control by a control BUS CMD _ BUS, and simultaneously selecting the SDRAM corresponding to a reading address to perform actions such as refreshing, activating and the like.

As shown in fig. 6, based on the SDRAM control system, another embodiment of the present invention provides a data writing control method for an SDRAM based on an FPGA, including the following steps:

s201: the command decoding module decodes the write command received from the external bus and sends the write command to the write module, configures an SDRAM (synchronous dynamic random access memory) address and sends the SDRAM address to the state machine module, and configures an address range of a cache RAM in the write module and sends the address range to the write module;

in this step, the command decoding module decodes the write command from the external bus, and sends the decoded write command to the write module, configures the SDRAM address to send to the state machine module, and configures the address range of the cache RAM inside the write module to send to the write module.

S202: the writing module stores data from an external bus into an internal cache according to a writing instruction, and starts the state machine module to enter a writing state through a full rising edge of the cache;

the method comprises the following substeps:

the writing module receives and caches data from an external bus through a cache RAM ping-pong, and sends a cache full rising edge to the state machine module when the cache is full;

and the state machine module receives the cache full rising edge signal, starts the state machine module to enter a write starting state, selects corresponding SDRAM according to the SDRAM address and sequentially sends an activation instruction and a null operation instruction and corresponding addresses under the drive of a global system clock.

In the step, a writing module receives data from an external BUS through two internal cache RAMs in a ping-pong manner, when the cache is full, a cache full rising edge is sent to a state machine module, the state machine module receives the cache full rising edge of the writing module, enters a writing starting state, under the drive of a global system clock, a CMD _ BUS control BUS is controlled according to a writing address to select an SDRAM corresponding to the writing address, and sequentially sends activating and idle operation commands and corresponding addresses, and the rest of the SDRAM performs self-refreshing under the control of the CMD _ REF control BUS, is still in a waiting state, and does not send commands such as activating and the like.

S203: the state machine module controls the writing module to write the cached data into the corresponding SDRAM;

the method comprises the following substeps:

the state machine module enters a write intermediate state, sends a write command and a write address to the corresponding SDRAM, sends a read enable for reading the cache RAM of the write module to the write module, and controls to write the data cached by the write module into the corresponding SDRAM;

when the write module writes all data stored in the internal cache RAM into the corresponding SDRAM, sending a cache empty rising edge to the state machine module, enabling the state machine module to enter a write ending state, waiting for an external bus to send next data to the write module, and then controlling the state machine module to enter a next write starting state through a cache full rising edge of the write module.

In the step, the state machine module enters a write intermediate state, sends a write command and a write address to a corresponding SDRAM (synchronous dynamic random access memory), sends a read enable for reading a cache RAM of the write module, controls the write module to send full cache data to the selected SDRAM in ping-pong mode, when the data sending is completed, the write module generates a cache empty mark, sends a rising edge of the cache empty to the state machine module, the state machine module enters a write end state, sequentially sends a Precharge (Precharge) and an empty command (NOP), closes a current row and generates a write end mark.

In conclusion, the invention realizes the gating read-write control, the simultaneous read control or the simultaneous write control of a plurality of SDRAM, meets the requirement of each SDRAM on the refresh time, does not cause data loss, simultaneously checks the read-write request in the refresh state, can avoid the condition that a state machine module can not respond to the read-write request in the refresh state, has the advantages of higher comprehensive efficiency, convenience for later maintenance and upgrading of projects and the like, and simultaneously adopts a module sharing mode for the plurality of SDRAM, and also has the advantages of optimized layout and resource saving.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (3)

1. A hardware device for realizing SDRAM control system based on FPGA is characterized in that the hardware device comprises an FPGA unit and a plurality of SDRAM connected with the FPGA unit;

the FPGA unit comprises an instruction decoding module, a state machine module, a reading module, a writing module, a data bus and a control bus;

the instruction decoding module is used for decoding an instruction from an external bus;

when a reading instruction is decoded, the instruction decoding module configures an SDRAM address and an address range of a cache RAM inside the reading module, the state machine module is used for receiving the reading instruction, strobes a single chip or multiple chips of corresponding SDRAM according to the SDRAM address, controls the reading module to read data from the corresponding SDRAM and store the data into an internal cache of the reading module, and controls the cached data to be read back to an external bus or a high-speed data line according to a cache state fed back by the reading module;

the read module is used for executing the data read from the corresponding SDRAM and storing the data into an internal cache according to the address range of an internal cache RAM of the read module, executing feedback on the cache state and executing data read back of the cache to an external bus or a high-speed data line;

when a write command is decoded, the command decoding module configures an SDRAM address and an address range of a cache RAM inside the write module, and the state machine module is used for gating one or more corresponding SDRAMs according to the SDRAM address and controlling the cached data to be written into the corresponding SDRAMs according to the cache state fed back by the write module;

the writing module is used for receiving the writing instruction, storing data from an external bus into an internal cache according to the address range of an internal cache RAM of the writing module, executing feedback of the cache state, and executing the writing of the cached data into a corresponding SDRAM;

the control BUS comprises a CMD _ BUS control BUS and a REF _ BUS control BUS which are connected with the state machine module, and the CMD _ BUS control BUS and the REF _ BUS control BUS are connected with pins of the plurality of SDRAMs through a multiplexer selection switch; the CMD _ BUS control BUS is used for controlling the read-write and refresh access of one or a plurality of SDRAM; the REF _ BUS control BUS is used for controlling the SDRAM to perform one-time self-refresh, namely when the CMD _ BUS control BUS accesses one or a plurality of SDRAMs in a read-write mode, the REF _ BUS control BUS is used for controlling the refresh function of other SDRAMs;

the data bus comprises a bidirectional three-state data bus, the data input end of the bidirectional three-state data bus is connected with the writing module, the data output end of the bidirectional three-state data bus is connected with the reading module, and the IO end of the bidirectional three-state data bus is connected with the plurality of SDRAM.

2. The hardware apparatus of claim 1, wherein the internal cache of the write module comprises a two-slice cache RAM constituting a ping-pong cache mechanism.

3. The hardware apparatus according to claim 1, wherein the internal cache of the read module comprises twice the amount of cache RAM as the SDRAM.

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