CN109815583A - The wiring method and test method of the interconnection resource of FPGA - Google Patents
The wiring method and test method of the interconnection resource of FPGA Download PDFInfo
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- CN109815583A CN109815583A CN201910054439.5A CN201910054439A CN109815583A CN 109815583 A CN109815583 A CN 109815583A CN 201910054439 A CN201910054439 A CN 201910054439A CN 109815583 A CN109815583 A CN 109815583A
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Abstract
This application involves integrated circuit testings, disclose the wiring method and test method of the interconnection resource of FPGA a kind of.The wiring method is specially according to selected direction, respectively since each row of starting routing cell or each column, the in turn wiring process of executable unit's step-length, to being routed to each row for terminating routing cell or be respectively classified as only, and according to the contrary direction selected with this, respectively since each row of the starting routing cell or each column, each wiring process for executing the primary one step；The test method being tested by profile section to cloth on the basis of the wiring method.Balanced existing fpga logic resource can be utilized in the application embodiment, the test wire drawing lines as much as possible in a test pat, test pat quantity needed for reducing the test of FPGA interconnection resource, reduces the FPGA testing time, reduces the time of test pat exploitation.
Description
Technical field
This application involves integrated circuit testing field, in particular to the wiring technique of a kind of interconnection resource of FPGA and test
Technology.
Background technique
Interconnection resource is connected to all units inside FPGA, and the length of line and technique decide signal on line
Driving capability and transmission speed.There is interconnection resource abundant inside fpga chip, designer does not need directly to select in practice
Interconnection resource is selected, placement-and-routing's device can be automatically according to the topological structure and constraint condition selective interconnection resource of input logic netlist
It is connected to modules unit, interconnection resource is the important component of FPGA, the direct shadow of the connectivity of the interconnection resource of FPGA
The concrete function for ringing the FPGA, then the test of the interconnection resource of FPGA is particularly important.
The shortcomings that existing FPGA interconnection resource test method be it is unbalanced to the resource utilization of FPGA, in this way to wiring
Test pat quantity required for resource testing is relatively more, and the FPGA interconnection resource testing time is also just long.
Summary of the invention
The wiring method and test method of a kind of interconnection resource for being designed to provide FPGA of the application, being capable of balanced benefit
With existing fpga logic resource, test wire drawing lines, reduction FPGA interconnection resource are surveyed as much as possible in a test pat
Test pat quantity needed for examination, reduces the FPGA testing time, reduces the time of test pat exploitation.
To solve the above-mentioned problems, this application discloses the interconnection resource wiring methods of FPGA a kind of, comprising:
According to selected direction, respectively since each row of starting routing cell or each column, in turn executable unit's step-length
Wiring process, until being routed to each row for terminating routing cell or being respectively classified as only, and according to the contrary side selected with this
To, respectively since each row of the starting routing cell or each column, each wiring process for executing the primary one step.
In a preferred embodiment, the wiring process of the one step further comprises: selection is by the type of profile section and root
Select one step according to the type by profile section, according to the selected direction from the one step across starting PLB to end
Only PLB is carried out by the wiring of profile section, and this is distributed into the input terminal of the LUT into termination PLB by profile section, and with the termination
The starting PLB of next adjacent one step wiring process on direction PLB selected as this, wherein starting wiring
Unit terminates routing cell across the one step with this.
In a preferred embodiment, this includes X1, X2 ... XL by the type of profile section, and L is natural number, wherein
X1 indicates that across 1 PLB step-length, wherein the one step of the X1 is 1 PLB step-length by profile section；
X2 indicates that across 2 PLB step-lengths, wherein the one step of the X2 is 2 PLB step-lengths by profile section；
…
XL indicates that across L PLB step-length, wherein the one step of the XL is L PLB step-length by profile section.
In a preferred embodiment, which further comprises:
When selecting the type by profile section as X1, when which is east or south, respectively since the 1st row or column,
Execute the wiring process by profile section of 1 PLB step-length with being repeated in, until being routed to Nth row or column terminates, and respectively from the
1 row or column, westwards or north direction, execute the wiring process by profile section of 1 PLB step-length；
When selecting the type by profile section as X2, when which is east or south, respectively from the 1st row or column and the 2nd
Row or column starts, and executes the wiring process by profile section of 2 PLB step-lengths with being repeated in, until be routed to respectively N-1 row or
Column and N row or column terminate, and respectively since the 1st row or column and the 2nd row or column, westwards or the direction in north, execute 2 PLB
The wiring process by profile section of step-length；
……
When selecting the type by profile section as XL, when which is east or south, respectively from the 1st row or column, the 2nd row
Or arrange ... ... and L row or column starts, and executes the wiring process by profile section of L PLB step-length with being repeated in, until respectively
Be routed to N-L+1 row or column ... ..., N row or column terminates, and respectively from the 1st row or column, the 2nd row or column ... ... and L row or
Column start, westwards or north direction, execute L PLB step-length the wiring process by profile section；
Wherein, the 1st row or column, the 2nd row or column ... ... and the L row or column are located at the different quilts of same column or row
On profile section, L natural number and 1≤L≤N, N are the number of the PLB of the same row or column of the FPGA, N > 0.
Disclosed herein as well is the interconnection resource test methods of FPGA a kind of, comprising:
Step 1: the step in method is described above；
Step 2: by connecting each I/O module by profile section to each starting PLB input logic by profile section
Value, the logical value be input to after this is by profile section this by profile section terminate PLB in LUT input terminal and in the LUT
Specific logical operation is carried out, and the result of all logical operations is input to and each d type flip flop corresponding to the respectively LUT
In, which shifts all operation results and exports；
Step 3: the connection by profile section of the corresponding respectively LUT connection is judged according to the operation result that the displacement exports
Property.
In a preferred embodiment, which is XOR operation.
In a preferred embodiment, which further comprises: giving the logical value inputted by profile section by I/O module
When changing, specific logical operation can be all carried out in the respectively LUT, operation result is input to corresponding to the respectively LUT
In each d type flip flop, then all operation results are shifted and are exported by each d type flip flop.
In a preferred embodiment, which further comprises: if the operation result of displacement output is not equal to correspondence
The respectively LUT each input value exclusive or as a result, the signal for then inputting the respectively LUT passed through by profile section exist open circuit or it is short
Road, otherwise input the respectively LUT signal passed through it is normal by profile section connectivity.
In a preferred embodiment, during which executes, be at best able to carry out simultaneously K seed type by survey line
Section wiring process, and the different input terminals of the K seed type being distributed into respectively by profile section to the LUT and in the LUT respectively
Logical operation is carried out, wherein 1≤K≤M, M are all LUT input terminal sums in each PLB.
In a preferred embodiment, which further comprises to step 3:
Reset all corresponding d type flip flops of each LUT for test；
Traversal is combined by all inputs of profile section, and executes following steps at least once, until having traversed all
Input combination:
Input combination by the I/O module is input to this by after profile section, into operation is compared in each LUT, by this
The result of comparison operation is output in the corresponding d type flip flop of each LUT, by all operation results in the corresponding d type flip flop
Displacement output；
Judged according to the operation result that the displacement exports by the connectivity of profile section.
This application discloses a kind of computer readable storage medium, computer is stored in the computer readable storage medium
Executable instruction, the computer executable instructions realize the step in method as previously described when being executed by processor.
In the application embodiment, following advantages is included at least:
In executing direction (such as E) wiring process, so that the LUT for originating routing cell is fully utilized, cloth will be terminated
The switch-back of line unit is put into the next and wiring process of the party in the opposite direction, and one step of start unit execution is opposite
The wiring in direction (such as W), it is reaching the utility model has the advantages that
By rationally arranging, optimal setting turning guide marking keeps the LUT utilization rate of each routing cell balanced consistent；
Moreover, interconnection resource can cloth it is logical in the case where, the wiring result on the same direction can be than existing wiring
Scheme at most can one times of more cloth drawing lines；
Further, the quantity for reducing the test pat needed for profile section test, shortens FPGA testing time and test
The development time of pat.
A large amount of technical characteristic is described in the description of the present application, is distributed in each technical solution, if to enumerate
Out if the combination (i.e. technical solution) of all possible technical characteristic of the application, specification can be made excessively tediously long.In order to keep away
Exempt from this problem, each technical characteristic disclosed in the application foregoing invention content, below in each embodiment and example
Each technical characteristic disclosed in disclosed each technical characteristic and attached drawing, can freely be combined with each other, to constitute each
The new technical solution (these technical solutions have been recorded because being considered as in the present specification) of kind, unless the group of this technical characteristic
Conjunction is technically infeasible.For example, disclosing feature A+B+C in one example, spy is disclosed in another example
A+B+D+E is levied, and feature C and D are the equivalent technologies means for playing phase same-action, it, can not as long as technically selecting a use
Can use simultaneously, feature E can be technically combined with feature C, then, and the scheme of A+B+C+D because technology is infeasible should not
It is considered as having recorded, and the scheme of A+B+C+E should be considered as being described.
Detailed description of the invention
Fig. 1 is the wiring method flow diagram according to the interconnection resource of the FPGA of the application first embodiment
Fig. 2 is the test method flow diagram according to the interconnection resource of the FPGA of the application second embodiment
Fig. 3 is the wiring method schematic diagram by profile section that type is X2 in a kind of FPGA interconnection resource
Fig. 4 is the wiring side by profile section that type is X2 in the FPGA interconnection resource according to the application first embodiment
Method schematic diagram
Fig. 5 is the total arrangement schematic diagram according to the application FPGA based on PLB
Fig. 6 is according to the interconnection structure schematic diagram between each PLB of the application FPGA
Fig. 7 is the structural schematic diagram according to PLB in the application FPGA
Fig. 8 is the structural schematic diagram according to SLICE in the application PLB
Fig. 9 is the planning schematic diagram according to the routing cell of the first implementation method of the application
Figure 10 is according to a specific embodiment flow chart of the step two in second embodiment to step 3
Specific embodiment
In the following description, in order to make the reader understand this application better, many technical details are proposed.But this
The those of ordinary skill in field is appreciated that even if without these technical details and many variations based on the following respective embodiments
And modification, the application technical solution claimed also may be implemented.
The explanation of part concept:
1.FPGA:Field Programmable Gate Array, Field Programmable Logic Array.It is as dedicated
One of integrated circuit fields semi-custom circuit and occur, not only solved the deficiency of full custom circuit, but also overcome original
The limited disadvantage of programmable logic device gate circuit number.
2.PLB:Programmable Logic Block, programmed logical module.It is the basic unit of FPGA, such as Fig. 7
Shown, it includes an a Routing Switch array RSB and logic unit PFB.
3.RSB:Routing Switch Box.It is the Routing Switch array of FPGA, many wirings are interconnected from this herein
In issue, also terminate from here, next PLB or PIB and oneself PLB intraconnection be connected to by this logical block.
4.PFB:Programmable Function Block, programmable function blocks.
It include two LUT and two corresponding d type flip flops in one SLICE of logic chip in 5.SLICE:FPGA.
6.LUT:Lookup Table, look-up table.In computer science, look-up table is replaced with simple inquiry operation
Data structure as the array or Associate array calculated when operation.
7.Register, register.It is the wherein component part in central processing unit, register is limited storage capacity
High speed depositing element, they can be used to temporary instruction, data and address.
8.BRAM:Block Random Access Memory, block random access memory.It is mainly used in construction data
Cache memory, deep FIFO and buffer etc..
9.IO module, Input and Output block, input/output module.Each I/O module and each PLB connect in FPGA
It connects.
10. test PAT: be a kind of route segments for testing the specific logical design of FPGA resource, such as by profile section:
It is test subject by profile section, existing LUT and d type flip flop and other connection unit constitute the signal by profile section in FPGA
Input main body and calculate main body, it is final this by profile section, the LUT as arithmetic unit, the d type flip flop as shift register, three
Person just constitutes a kind of special measurement circuit, is known as a test pat of FPGA.Test pat is LUT in test FPGA
And the measurement circuit specially designed, referred to as test the PAT of LUT.In general, a test pat can only test the one of FPGA
A part of kind resource.FPGA is made of multiple resources, so the test PAT of FPGA has very much.
11. routing cell: it is selected by profile section the unit number across PLB, the span is according to selected by profile section
Type determine.For example, if the selected type by profile section is X2, then the institute of this type of wiring is across 2 PLB.
12. originating routing cell and terminating routing cell: the i.e. stop bits of the initial position of interconnection wiring and interconnection wiring
Set: unidirectional wiring process is terminated by the initial position start and ending position of interconnection wiring.As shown in figure 3, if by
When the type of profile section is X2 and is routed eastwards, first group of first segment is started by profile section from position (0,0), arrives position (2,0)
Terminate.Then start from position (2,0), terminate to position (4,0).And so on until terminate.Second group of first segment is by survey line
Section starts from position (1,0), terminates to position (3,0).Then start from position (3,0), terminate to position (5,0).
Implementation to keep the purposes, technical schemes and advantages of the application clearer, below in conjunction with attached drawing to the application
Mode is described in further detail.
The first embodiment of the application is related to a kind of wiring method of the interconnection resource of FPGA, process as shown in Figure 1,
The wiring method the following steps are included:
Start, executes step 101: according to selected direction, respectively since each row of starting routing cell or each column, according to
The wiring process of Ci Di executable unit step-length, until being routed to each row for terminating routing cell or being respectively classified as only；
Later, step 102 is executed: according to the contrary direction selected with this, respectively from the starting routing cell
Each row or each column start, each wiring process for executing the primary one step.
Optionally, the wiring process of the one step further comprises: selection is tested by the type of profile section and according to this
The type of line segment selectes one step, according to the selected direction from one step institute across starting PLB to terminating PLB progress
By the wiring of profile section, and this is distributed into the input terminal of the LUT into termination PLB by profile section, and using termination PLB as should
The starting PLB of next adjacent one step wiring process on selected direction, wherein the starting routing cell and the knot
Wiring in bundles unit is across the one step.
Optionally, this includes X1, X2 ... XL by the type of profile section, and L is natural number, wherein
X1 indicates that across 1 PLB step-length, wherein the one step of the X1 is 1 PLB step-length by profile section；
X2 indicates that across 2 PLB step-lengths, wherein the one step of the X2 is 2 PLB step-lengths by profile section；
…
XL indicates that across L PLB step-length, wherein the one step of the XL is L PLB step-length by profile section.
Optionally, according to the selected type by profile section, which further comprises:
1) it when selecting the type by profile section as X1, when which is east or south, is opened respectively from the 1st row or column
Begin, execute the wiring process by profile section of 1 PLB step-length with being repeated in, until being routed to Nth row or column terminates, and respectively
From the 1st row or column, westwards or north direction, execute the wiring process by profile section of 1 PLB step-length；
2) when selecting the type by profile section as X2, when which is east or south, respectively from the 1st row or column, and
2nd row or column starts, and executes the wiring process by profile section of 2 PLB step-lengths with being repeated in, until being routed to N-1 row respectively
Or column and N row or column terminate, and respectively since the 1st row or column and the 2nd row or column, westwards or the direction in north, execute 2
The wiring process by profile section of PLB step-length；
……
When selecting the type by profile section L) as XL, when which is east or south, respectively from the 1st row or column, the 2nd
Row or column ... ... and L row or column start, and execute the wiring process by profile section of L PLB step-length with being repeated in, until point
It is not routed to N-L+1 row or column ... ..., N row or column terminates, and respectively from the 1st row or column, the 2nd row or column ... ... and L row
Or column start, westwards or north direction, execute L PLB step-length the wiring process by profile section；Wherein, the 1st row or column,
2nd row or column ... ... and the L row or column are located at the different by profile section of same column or row, and L natural number and 1≤L≤
N, N are the number of the PLB of the same row or column of the FPGA, N > 0.
During the wiring method executes, the wiring by profile section of one or more types can be carried out simultaneously
Journey；Preferably, a type of wiring process by profile section is carried out during which executes simultaneously；Optionally,
The test method carries out a plurality of types of wiring process by profile section simultaneously during executing, specifically, carrying out K kind simultaneously
The wiring process by profile section of type, and the K seed type be distributed into respectively by profile section to the LUT different input terminals and
Logical operation is carried out in the LUT respectively, wherein 1≤K≤M, M are all LUT input terminal sums in each PLB.
It should be understood that, if completing the wiring by profile section of all interconnection resources, being needed more for same FPGA
The wiring process of the secondary wiring method for executing present embodiment is (including being all routed and being distinguished to every kind of type by profile section
Selected four direction is routed etc.), wherein under normal circumstances, execute the primary wiring method only in the same direction into
Row.
It should be understood that the implementation procedure of step 101 and step 102 is without sequencing, after can first carrying out step 101
Step 102 is executed, executes step 101 after step 102 can be first carried out, or may be performed simultaneously step 101 and step 102.
The second embodiment of the application is related to a kind of test method of the interconnection resource of FPGA, process as shown in Fig. 2,
The test method the following steps are included:
Start, executes a kind of step 201: the wiring method of the interconnection resource for FPGA that the application first embodiment is related to
The step of.
It should be noted that first embodiment is the identical method implementation of step 201 of present embodiment, first
Technical detail in embodiment can be applied to the step 201 of present embodiment.
Later, step 202 is executed: by connecting each I/O module by profile section to each starting by profile section
The end PLB input logic value, the logical value are input to the input for terminating LUT in PLB by profile section after this is by profile section
Hold and simultaneously carry out specific logical operation in the LUT, and by the result of all logical operations be input to corresponding to each LUT
In each d type flip flop, which shifts all operation results and exports.
What the specific logical operation can be changed by setting, optionally, which can be XOR operation；It can
Selection of land, the logical operation can be comparison operation；Etc..
Optionally, step 202 further comprises: giving this to be changed by the logical value that profile section inputs by I/O module
When, specific logical operation can be all carried out in the respectively LUT, operation result is input to each d type flip flop corresponding to the respectively LUT
In, then all operation results are shifted and are exported by each d type flip flop.
Finally, executing step 203: judging the corresponding LUT connection according to the operation result for shifting output in step 202
By the connectivity of profile section.
Optionally, step 203 further comprises: if the operation result of displacement output is not equal to the corresponding LUT's
Each input value exclusive or as a result, the signal for then inputting the respectively LUT passed through by profile section exist open circuit or short circuit, otherwise input
What respectively the signal of the LUT was passed through is normal by profile section connectivity.
During the test method of the application second embodiment executes, one or more types can be carried out simultaneously
By the wiring process of profile section；Preferably, it carries out simultaneously during which executes a type of by profile section
Wiring process；Optionally, a plurality of types of wiring process by profile section are carried out simultaneously during which executes, are had
Body, while carrying out the wiring process by profile section of K seed type, and the K seed type is distributed into respectively to the LUT by profile section
Different input terminals and carry out logical operation respectively in the LUT, wherein 1≤K≤M, M be each PLB in all LUT input terminals
Sum.
Optionally, the step two in present embodiment can further include following steps to step 3:
Start to execute A, resets all corresponding d type flip flops of each LUT for test；
B is executed later, and traversal is combined by all inputs of profile section, and executes B1 to B2 at least once, until having traversed
All input combinations:
B1 will input combination be input to by the I/O module it is described by after profile section, into being compared fortune in each LUT
It calculates, the result of the comparison operation is output in the corresponding d type flip flop of each LUT, it will be in the corresponding d type flip flop
All operation result displacement outputs；
B2 judges according to the operation result of the displacement output by the connectivity of profile section.
Figure 10 is according to a specific embodiment flow chart of the step two in second embodiment to step 3.
It should be noted that test method of the present embodiment can be executed by step 1 it is all types of
After the wiring process of profile section, the test process of step 2 and step 3 is executed, until testing all types of tested
Line segment；Be also possible to after selective one seed type of completion or a variety of wiring process by profile section, execute step 2 and
Then the test process of step 3 executes the other kinds of wiring process by profile section not being routed again, then holds again
The test process of row step 2 and step 3, until completing all types of by the wiring of profile section and test process.
In order to more fully understand the technical solution of the application, it is illustrated below with reference to a specific example,
The details enumerated in the example is primarily to be easy to understand, not as the limitation to the application protection scope.
The test of FPGA interconnection resource is to do logical comparison using LUT resource inside FPGA to judge.One in general
FPGA unit only has 8 logic units, it is possible to can be less.This example is that the FPGA of 20 × column of row 22 is laid out (in row-column layout's shape
At lattice all regard a PLB (basic unit) as), by by profile section be the direction X2 line E2 for:
Fig. 3 is the wiring method by profile section that type is X2 in a kind of FPGA interconnection resource.It can be seen from the chart, it should
The shortcomings that wiring method is: the 0th, 1 column are starting routing cells, and two column are without carrying out logical comparison, the benefit of the LUT of two column
It is relatively low with rate；21st, 22 column (most next two columns) be terminate routing cell, this two column need twice logic unit more directly to
Each by profile section with steering, the utilization rate of the LUT of two column is relatively high, twice other (except the 0th, 1 column and the 21st, 22 column)
LUT unit, cause LUT utilization rate unbalanced.
Fig. 4 is the wiring side by profile section that type is X2 in the FPGA interconnection resource according to the application first embodiment
Method.It can be seen from the chart, the key of this method is when the same direction (E) of test is by profile section, also in starting cloth
Two column of line unit carry out the test of primary measured line segment to opposite direction (W) respectively；It, should compared with the conventional method described in Fig. 3
The advantages of method, is: in the test process according to the wiring method of Fig. 4, originating LUT in each column (the 0th, 1 column) of routing cell
Also it can be fully utilized, so that LUT utilization rate be made in each column (PLB) of each routing cell to reach balanced consistent, and with this
Method interconnection resource can cloth it is logical in the case where, once can one times of cloth of drawing lines more than the method than Fig. 3；It needs to add explanation
It is: in the test process according to the wiring method of Fig. 4, although terminating LUT in each column (the 21st, 22 column) of routing cell does not have
It is utilized, but can be tested in the test of the opposite direction (west) of next time as when originating routing cell.
It should be noted that this application involves connection include be directly connected to and be of coupled connections.
Here is the supplementary explanation to part the relevant technologies involved in each embodiment of the application:
Fig. 5 is according to total arrangement schematic diagram of one FPGA of the application based on PLB.As shown in figure 5, middle section is (such as
(0,0)) be FPGA a programmable logic cells (PLB), it will be appreciated that at the basic unit of an array.Periphery is programmable
I/O module, that is all logical signals only pass through I/O module could be sent into FPGA PLB by profile section, also only IO
Module could send out the logical signal of FPGA.
Fig. 6 is according to the structural schematic diagram between one each PLB of FPGA of the application by being interconnected by profile section.Each
There is a programmable RSB (Routing Switch Box) in PLB, the connection between the PLB of FPGA is exactly to be realized by RSB
's.Signal is transmitted by horizontal channel and vertical channel between PLB, and PLB can directly drive horizontally or vertically channel, between channel
It is switched over by channel RSB (routing switch Box), the signal transmitted on channel enters PFB by part RSB.
Comprising various types of by profile section in RSB, with type X0, X1, X2, for X4, X6, in which: X0 indicates that PLB is arrived
Oneself this unit by profile section type；X1 indicate across PLB step-length by profile section type；X2 indicates to walk across two PLB
It is long by profile section type；X4 indicate across four PLB step-lengths by profile section type；X6 indicates tested across six PLB step-lengths
Line segment type.
The wiring direction of FPGA interconnection resource: usual FPGA's includes the side of the four corners of the world four by the wiring direction of profile section
To common E, W, S, N are indicated.Wherein, North and South direction by profile section is mutually linked as vertical channel, east-west direction by profile section
Be mutually linked as horizontal channel.
This application involves the direction of East, West, South, North be on figure after FPGA to be laid out in cellular construction shown in fig. 5
Direction.
Fig. 7 is the structural schematic diagram according to PLB (programmable logic block) in one FPGA of the application.As shown in fig. 7,
The logical signal connection for having RSB (Routing&Switch Box) to be responsible between PLB in PLB, PLB includes PFB (programmable functions
Block), PFB includes four SLICE；In SLICE include two LUT (lookup logic table) and therewith one-to-one two may be programmed
D type flip flop/latch.
Fig. 8 is the structural schematic diagram according to SLICE in the application PFB.As shown in figure 8, each LUT includes four inputs
End, the input terminal D that the output end of each LUT passes through Combinational logic output one-to-one d type flip flop therewith.The end Q of d type flip flop
It can be connected with other PLB by RSB.
The starting point (in starting PLB) by profile section of FPGA interconnection resource and clearing end (terminating PLB) common BEG with
END is indicated；For example, a behavior eight, is classified as six FPGA, by taking X2 type is by profile section as an example, as shown in figure 9, E2BEG0:
It represents to originate PLB (x, y) as starting point, eastwards across two PLB, terminates to PLB (x, y+2) is terminated；That is: (x's, y)
The E2END0 of E2BEG0 and (x, y+2) are that be connected together is exactly type for one of X2 by profile section.This X2 type is tested
The drawing lines of line segment is E2BEG0 ... E2BEG6, and that is X2 line eastwards has 0~6 drawing lines.
FPGA is programming device, it by standard cell array (including lookup logic unit, register, interconnection resource)
Composition.
In FPGA interconnection resource, each PLB ((x, y) basic unit of such as Fig. 9) of FPGA has identical by profile section
Resource will be verified before factory.For example, if FPGA has an X0, X1, X2, six kinds of spans of X4, X6 by profile section.Often
Kind is had in E (east) by profile section, W (west), N (south), the four kinds of directions S (north).Every kind has 7 drawing lines by profile section.It is then each basic
Unit has: 6*4*7=168 root is by profile section.The connectivity that entire FPGA has 6*8*168=8064 root to be detected it by profile section
Energy.
Ibid, the type by profile section of interconnection resource can be divided into X1 (can only be across a basic unit), and X2 (can only be across
Two basic units), X6 (can only be across six basic units), X0 (can only be in this basic unit line) ... etc., with X1,
The types such as X2, X6, X0 by for profile section, and be divided into four corners of the world four direction, naming rule is as follows:
E { G } BEG { H }, E { G } END { H } indicate X { G } eastwards by profile section G=0,1,2,6；
BEG indicates to originate, H=4, and 8 ...；
END expression terminates, H=4, and 8 ...；
W { G } BEG { H }, W { G } END { H } indicate X { G } westwards by profile section G=0,1,2,6；
BEG indicates to originate, H=4, and 8 ...；
END expression terminates, H=4, and 8 ...；
S { G } BEG { H }, S { G } END { H }, N { G } BEG { H }, N { G } END { H }.
Turning guide marking: being reformed into westwards by profile section turning that W is by profile section if it is E eastwards, and westwards W is turned by profile section
It is curved become eastwards E by profile section, S to the south reformed by profile section turning northwards N by profile section, northwards N by profile section
Turning becomes S to the south by profile section, and step size computation, which is turned, when turning oneself calculates a step.
The interconnection resource of FPGA detects, and seeks to check that in these of each unit by the disengaging connection of profile section be normal
, usually logic unit is entered by the termination PLB of profile section it is compared inspection each.One logic unit has 6~8
Logical operation table, each operation table can have 4 inputs, that is to say, that each operation table can at most check 4 by profile section.
The test cabling scheme of interconnection resource determines the coverage rate of FPGA test, resolution chart number and testing time in FPGA.
The test method of the interconnection resource of existing FPGA specifically includes the following steps:
Start to execute step 1: in each PLB by profile section according to certain interconnection rule cloth into the LUT of PFB；
It is executed later step 2: inputting from I/O module by logical signal by profile section.Guarantee each logic by profile section
Signal is consistent with input signal；
It is executed later step 3: use LUT as comparator, it will be by by input signal progress that profile section be the LUT inputted
Logic exclusive or is then mutually all 0, is not all 1；It is consistent by the signal of profile section and input, if LUT is 1, show to have individual tested
Line segment is short and inputs inconsistent, it is possible to open circuit or short circuit；If LUT is 0, illustrate four input terminals connection of this LUT
It is normal by profile section connectivity；
It is executed later step 4: the comparison result of LUT to be sent into the input terminal of d type flip flop；
It finally executes step 5: the d type flip flop of all storage LUT comparison results is linked to be shift register.Thus may be used
To export each comparison result by profile section from limited I/O module.
The test mode of the application second embodiment is after wiring result according to first embodiment to the existing survey
The optimization of examination.
The application embodiment also provides a kind of computer readable storage medium, wherein being stored with, computer is executable to be referred to
It enables, which realizes each method embodiment of the application when being executed by processor.Computer-readable storage
Medium includes that permanently can be accomplished by any method or technique information with non-permanent, removable and non-removable media and deposit
Storage.Information can be computer readable instructions, data structure, the module of program or other data.The storage medium of computer
Example includes but is not limited to phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory
(DRAM), other kinds of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory
(EEPROM), flash memory or other memory techniques, read-only disc read only memory (CD-ROM) (CD-ROM), digital versatile disc
(DVD) or other optical storage, magnetic cassettes, tape magnetic disk storage or other magnetic storage devices or any other non-biography
Defeated medium, can be used for storage can be accessed by a computing device information.As defined in this article, computer readable storage medium
It does not include temporary computer readable media (transitory media), such as data-signal and carrier wave of modulation.
It should be noted that relational terms such as first and second and the like are only in the application documents of this patent
For distinguishing one entity or operation from another entity or operation, without necessarily requiring or implying these entities
Or there are any actual relationship or orders between operation.Moreover, the terms "include", "comprise" or its any other
Variant is intended to non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only
It including those elements, but also including other elements that are not explicitly listed, or further include for this process, method, object
Product or the intrinsic element of equipment.In the absence of more restrictions, the element limited by sentence " including one ", not
There is also other identical elements in the process, method, article or apparatus that includes the element for exclusion.The application of this patent
In file, if it is mentioned that certain behavior is executed according to certain element, then refers to the meaning for executing the behavior according at least to the element, wherein
Include two kinds of situations: executing the behavior according only to the element and the behavior is executed according to the element and other elements.Multiple,
Repeatedly, the expression such as a variety of include 2,2 times, 2 kinds and 2 or more, 2 times or more, two or more.
It is included in disclosure of this application with being considered as globality in all documents that the application refers to, so as to
It can be used as the foundation of modification if necessary.In addition, it should also be understood that, the foregoing is merely the preferred embodiments of this specification, and
The non-protection scope for being used to limit this specification.It is all this specification one or more embodiment spirit and principle within, institute
Any modification, equivalent substitution, improvement and etc. of work, should be included in this specification one or more embodiment protection scope it
It is interior.
Claims (10)
1. the interconnection resource wiring method of FPGA a kind of characterized by comprising
According to selected direction, respectively since each row of starting routing cell or each column, the in turn cloth of executable unit's step-length
Line process, until be routed to terminate routing cell each row or be respectively classified as only, and according to the selected contrary direction,
Respectively since each row of the starting routing cell or each column, each wiring process for executing the primary one step.
2. wiring method according to claim 1, which is characterized in that the wiring process of the one step is further wrapped
Include: selection selectes one step by the type of profile section and according to the type by profile section, according to the selected direction
From the one step across starting PLB be distributed by profile section to institute by the wiring of profile section, and by this to PLB is terminated
State the input terminal for terminating LUT in PLB, and using termination PLB as the selected direction on next adjacent unit step
The starting PLB of long wiring process, wherein the starting routing cell and the end routing cell are across the one step.
3. wiring method according to claim 1, which is characterized in that described by the type of profile section includes X1, X2 ...
XL, L are natural number, wherein
X1 is indicated across 1 PLB step-length by profile section, wherein the one step of the X1 is 1 PLB step-length；
X2 is indicated across 2 PLB step-lengths by profile section, wherein the one step of the X2 is 2 PLB step-lengths；
…
XL is indicated across L PLB step-length by profile section, wherein the one step of the XL is L PLB step-length.
4. wiring method according to claim 3, which is characterized in that the wiring method further comprises:
When selecting the type by profile section as X1, when the selected direction is east or south, respectively since the 1st row or column, according to
The secondary wiring process by profile section that 1 PLB step-length is repeatedly carried out, until being routed to Nth row or column terminates, and respectively from the 1st
Row or column, westwards or north direction, execute the wiring process by profile section of 1 PLB step-length；
When selecting the type by profile section as X2, when the selected direction is east or south, respectively from the 1st row or column and the 2nd row
Or column start, and execute the wiring process by profile section of 2 PLB step-lengths with being repeated in, until it is routed to N-1 row or column respectively,
Terminate with N row or column, and respectively since the 1st row or column and the 2nd row or column, westwards or north direction, execute 2 PLB step-lengths
The wiring process by profile section；
……
When selecting the type by profile section as XL, when the selected direction is east or south, respectively from the 1st row or column, the 2nd row or
It arranges ... ... and L row or column starts, and executes the wiring process by profile section of L PLB step-length with being repeated in, until cloth respectively
Line is to N-L+1 row or column ... ..., and N row or column terminates, and respectively from the 1st row or column, the 2nd row or column ... ... and L row or column
Start, westwards or north direction, execute L PLB step-length the wiring process by profile section；
Wherein, the 1st row or column, the 2nd row or column ... ... and the L row or column are located at the difference of same column or row
By on profile section, L natural number and 1≤L≤N, N are the number of the PLB of the same row or column of the FPGA, N > 0.
5. the interconnection resource test method of FPGA a kind of characterized by comprising
Step 1: method according to any of claims 1-4 carries out the interconnection resource wiring of FPGA；
Step 2: it is patrolled by being inputted with each I/O module being connect by profile section to each starting PLB by profile section
Volume value, the logical value by it is described by profile section after be input to it is described by profile section terminate PLB in LUT input terminal and
Carry out specific logical operation in the LUT, and by the result of all logical operations be input to corresponding to each LUT
Each d type flip flop in, by operation results all in each d type flip flop shift export；
Step 3: the connectivity by profile section of the corresponding LUT connection is judged according to the operation result of the displacement output.
6. test method according to claim 5, which is characterized in that the specific logical operation is XOR operation.
The step 2 further comprises: when being changed by I/O module to the logical value inputted by profile section, all can
Specific logical operation is carried out in each LUT, operation result is input in each d type flip flop corresponding to each LUT,
Then operation results all in each d type flip flop are shifted and is exported.
7. test method according to claim 5, which is characterized in that the step 3 further comprises: if the shifting
Position output operation result not equal to corresponding each LUT each input value exclusive or as a result, being then input to each LUT's
There is open circuit or short circuit by profile section in what signal was passed through, otherwise input that the signal of each LUT passed through is connected by profile section
The general character is normal.
8. test method according to claim 7, which is characterized in that during the test method executes, most multipotency
The wiring process by profile section enough while that carry out K seed type, and the K seed type is distributed into respectively by profile section to described
The different input terminals of LUT simultaneously carry out logical operation respectively in the LUT, wherein 1≤K≤M, M are that all LUT are defeated in each PLB
Enter end sum.
9. according to test method described in claim 5-8 any one, which is characterized in that the step 2 to step 3, into
One step includes:
Reset all corresponding d type flip flops of each LUT for test；
Traversal is combined by all inputs of profile section, and executes following steps at least once, until having traversed all inputs
Combination:
Will input combination be input to by the I/O module it is described by after profile section, into operation is compared in each LUT, by institute
The result for stating comparison operation is output in the corresponding d type flip flop of each LUT, by all fortune in the corresponding d type flip flop
Calculate result displacement output；
Judged according to the operation result of the displacement output by the connectivity of profile section.
10. a kind of computer readable storage medium, which is characterized in that be stored with computer in the computer readable storage medium
Executable instruction is realized as described in any one of claim 5 to 9 when the computer executable instructions are executed by processor
Method in step.
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