CN101464494A - Interconnection line test circuit used in field programmable gate array device - Google Patents

Abstract

The invention relates to an interconnection line testing circuit used in a field programmable gate array device, which comprises even number of vector generation and respond analyzers. Each vector generation and respond analyzer in the even number of vector generation and respond analyzers comprises an n-input and n-output logic combined circuit and a group of n-bit registers, wherein, n is a natural number; and every two vector generation and respond analyzers are connected by interconnection lines with opposite direction and the bit width of n and are combined into a built-in self-testing circuit. The built-in self-testing circuit can achieve the simultaneous test of the two groups of interconnection lines with opposite direction and larger bit width on the condition that the number of the registers is not changed, shorten the testing time of a FPGA device, and reduce the testing cost of the FPGA device.

Description

The interconnection line test circuit that uses in a kind of FPGA

Technical field

The present invention relates to a kind of interconnection line measuring technology, especially, relate to the interconnection line circuit that uses in a kind of FPGA.

Background technology

Field programmable gate array (Field Programable Gate Array, that FPGA) adopt is logical cell array (Logic Cell Array, LCA) form, its inside comprises configurable logic blocks (Configurable Logic Block, CLB), output load module (InputOutput Block, IOB) and interconnector (Interconnect, IR) three parts; IOB can provide the connecting interface between FPGA internal logic and the package pins, and CLB can be used for realizing the logic and the sequential memory function of fpga chip, and IR then is used for realizing the signal and communication between fpga chip CLB, the IOB.

Have in two-dimentional CLB array that (Look Up Table LUT) and configurable logic and sequential resource such as register, realizes logical design and timing Design function such as look-up table; Corresponding switch matrix (Switch Matrix of each CLB in FPGA, SM), and between the point on four limits up and down of SM by many programmable interconnect point (ProgrammableInterconnect Point, PIP) link to each other, then (LineSegment LS) interconnects by some interconnect line segment between the SM.SM and LS have constituted the interconnect resource of FPGA jointly, by PIP is programmed (configuration), can realize different interconnect functions.

FPGA device of the prior art adopts the PIP structure of unidirectional drive usually, as shown in Figure 1, a SRAM dispensing unit and a transfer tube 101 add that buffering logical one 02 is in order to guarantee the driving force of interconnection line, be that existing unidirectional PIP has increased the buffering logical one 02 shown in Fig. 1 outside dispensing unit and transfer tube, just improved driving force.

Owing to exist by the opposite unidirectional drive PIP203 of interconnect line segment 202 closures among the SM201 of FPGA device, as shown in Figure 2, in the horizontal direction, both there had been unidirectional drive PIP203 from left to right among the SM201, also had the unidirectional drive PIP203 of right-to-left simultaneously.

Yet when the interconnect resource in the FPGA device was tested, (Wire Under Test WUT) covered all LS and PIP to need to make up some tested interconnection lines usually.In existing FPGA device interconnection resources method of testing, all need in test configurations, distinguish the level among the conducting SM, vertical, oblique switch, form the tested interconnection line of covering level, vertical, oblique interconnect resource, and then by adding test and excitation or utilizing the CLB in the FPGA device to make up built-in self-test (Built In Self-Test, BIST) circuit is tested tested interconnection line, to detect the fault in the interconnect resource.

What adopt in the above-mentioned test is the FPGA device of unidirectional drive PIP, and the problem of appearance is exactly to dispose to form two prescriptions to the interconnection line opposite, that bit wide is identical when manufacturing test FPGA device.As shown in Figure 3, being set in has three driving directions PIP from left to right and the PIP of three driving direction right-to-lefts respectively among the SM, the time will dispose in test so and form that one group of bit wide is three, is three with one group of bit wide from left to right, the tested interconnection line of right-to-left; On the other hand, for the FPGA device that has adopted unidirectional drive PIP, when utilizing this device to realize some design function, may form as shown in Figure 5 two prescriptions equally on the contrary, the interconnection line that bit wide is identical.

Development along with the FPGA measuring technology, the multidigit interconnection line that configuration formed when FPGA was tested, other two kinds of method of testings have appearred, a kind of is to adopt the method that directly loads test and excitation by the external terminal of FPGA device, if the shortcoming of this method is exactly the increase of FPGA device scale, and the growth of external terminal number does not catch up with increasing of interconnect resource number in the FPGA device far away; Therefore, employing directly adds the method for test and excitation and is not suitable for formed interconnection line to the interconnect resource test in the existing large-scale F PGA device time.

Another kind of method of testing then is to utilize the CLB that is positioned at tested interconnection line two ends in the FPGA device to make up the BIST circuit; This method improvement the problem of outside number of pins constraint in the said method.Concrete BIST circuit structure as shown in Figure 4, drive end at tested interconnection line need make up a test vector generator (Test Pattern Generator, TPG) circuit is used to generate test and excitation, (Output Response Analyzer, ORA) circuit is used for the observation test response and need make up a test response analyzer at the receiving end of tested interconnection line.Promptly can observe the value of the register in the FPGA device by the retaking of a year or grade function of utilizing the FPGA device, therefore, the ORA circuit can utilize the register identical with tested interconnection line figure place to make up.In order to generate bridging fault, the persistent fault that detects between the tested interconnection line, also need to utilize the register identical and some logical resources to make up the TPG circuit usually with tested interconnection line figure place.Therefore, suppose that the register among each CLB has only three, as shown in Figure 3, so just need twice test configurations, first test configurations will utilize the CLB of left to make up TPG, and utilize right-hand CLB to make up ORA, interconnection line is from left to right tested, another test configurations then utilizes right-hand CLB to make up TPG, and utilizes the CLB of left to make up ORA, and the interconnection line of right-to-left is tested.So just can finish the test of the interconnection line that two groups of bit wides are 3, direction is opposite shown in Fig. 3.

In a word, the technical matters that those skilled in the art need solve is exactly: under the register resources condition of limited, and the BIST circuit of test when how to realize the bigger two groups of bit wide interconnection lines such as opposite direction of bit wide.

Summary of the invention

The purpose of this invention is to provide a kind of when register quantity is constant, the new BIST circuit of testing when realizing the bigger two groups of bit wide interconnection lines such as opposite direction of bit wide, this BIST circuit can shorten the test duration at the FPGA device detection, and has reduced the testing cost of this device.

For achieving the above object, the invention discloses the interconnection line circuit that uses in a kind of FPGA device, comprise: the even number vector generates and the response analysis device, each vector in generation of described even number vector and the response analysis device generates and the response analysis device comprises that a n imports logic combination circuit and one group of n bit register of n output, wherein, n gets natural number;

Per two vectors generate and the response analysis device connects to form the built-in self-test circuit by the interconnection line that direction is opposite, bit wide is n, and described built-in self-test circuit is: the logic combination circuit C of primary vector generation and response analysis device ₁Input end connect that secondary vector generates and the interconnection line B of response analysis device ₂Output terminal, primary vector generates and the logic combination circuit C of response analysis device ₁Output terminal connect that primary vector generates and the register R of response analysis device ₁Input end, primary vector generates and the register R of response analysis device ₁Output terminal connect that primary vector generates and the interconnection line B of response analysis device ₁Input end, primary vector generates and the interconnection line B of response analysis device ₁Output terminal connect that secondary vector generates and the logic combination circuit C of response analysis device ₂Input end, secondary vector generates and the logic combination circuit C of response analysis device ₂Output terminal connect that secondary vector generates and the register R of response analysis device ₂Input end, secondary vector generates and the register R of response analysis device ₂Output terminal connect that secondary vector generates and the interconnection line B of response analysis device ₂Input end;

Wherein, described register R ₁The reset values of [t] is 0 entirely, R ₂The reset values of [t] is 1 entirely, and described logic combination circuit C ₁, C ₂Satisfy following logical relation:

For logic combination circuit C ₁, C ₂Shu Chu the 0th logical value respectively:

Logic combination circuit C ₁, C ₂Shu Chu the 0th logical value is separately by z logic combination circuit C respectively ₁, C ₂Input logic value XOR obtain, the proper polynomial that described z sets for the n bit register is $1+x^{m_1}+x^{m_2}+...+x^{m_k}$ Value,

${C_1}^o\left[0\right]={C_1}^i[m_1-1]\⊕{C_1}^i[m_2-1]\⊕...\⊕{C_1}^i[m_k-1]$

${C_2}^o\left[0\right]={C_2}^i[m_1-1]\⊕{C_2}^i[m_2-1]\⊕...\⊕{C_2}^i[m_k-1]$

For logic combination circuit C ₁The 1st position logical value to n-1 output:

Logic combination circuit C ₁The t position logical value of output is corresponding logic combination circuit C ₁The input logic value of last position, C ₁ ^o[t]=C ₁ ⁱ[t-1], 1≤t≤n-1;

For logic combination circuit C ₂N-1 position logical value is arrived in the 1st of output:

If C ₂ ⁱ[t] is complete 0 or C ₂ ⁱ[t] is complete 1 o'clock, then logic combination circuit C ₂The t position of output equals corresponding logic combination circuit C ₁The logical inverse of the input logic value of last position:

C ₂ ^o[t]=～C ₂ ⁱ[t-1], 1≤t≤n-1, wherein ,=～presentation logic is anti-;

Otherwise, logic combination circuit C then ₂The t position of output equals corresponding logic combination circuit C ₁The input logic value of last position: C ₂ ^o[t]=C ₂ ⁱ[t-1], 1≤t≤n-1;

m _kBe the index in the described proper polynomial, k is a natural number, 1≤k≤n-1,

Wherein, above-mentioned subscript o represents described logic combination circuit C ₁, C ₂Output terminal, subscript i represents described logic combination circuit C ₁, C ₂Input end,

The presentation logic XOR.

Compared with prior art, the present invention has the following advantages:

At first, the invention provides a kind of BIST circuit at bit wide interconnection lines such as two groups in the FPGA device are reverse, this circuit only uses n register just can finish two groups of bit wides respectively to be n, the test of the interconnection line that direction is opposite at the interconnection line two ends.The invention solves the limited shortcoming of register resources of configurable use when making up the BIST circuit, and test when realizing two groups of bit wide interconnection lines such as opposite direction of bigger bit wide; In addition, BIST circuit of the present invention can improve the interconnection line bit wide that can test in each test configurations, thereby the configuration of (this test comprises manufacturing test and system testing) has been shortened the test duration simultaneously, and has been reduced testing cost when reducing the FPGA device detection.(test duration of FPGA device is depended on the number of test configurations)

Secondly, the present invention is by providing a kind of BIST circuit, thereby realize utilizing limited register and logical resource among the CLB that the FPGA device comprises, finish FPGA device two prescriptions that possible configuration forms in manufacturing test on the contrary, test in the time of interconnection line that bit wide equates; If promptly the figure place of two groups of bit wide interconnection lines such as opposite direction is n, BIST circuit so of the present invention only need use n register at the two ends of interconnection line respectively, can finish the test of two groups of interconnection lines.

Moreover the present invention can be used for the FPGA device that adopts unidirectional drive PIP interconnection structure is carried out the interconnect resource test, because it reduces half with test configurations, therefore can shorten the test duration greatly, reduces testing cost.The present invention both had been applicable to the manufacturing test of FPGA device, also be applicable to the FPGA device in system testing, therefore can be used for improving the reliability of FPGA device and place electronic system thereof.

Description of drawings

Fig. 1 is a unidirectional drive PIP structure of the prior art;

Fig. 2 be in the switch matrix existing horizontal direction from left to right with the synoptic diagram of the unidirectional drive PIP of right-to-left;

Fig. 3 is the interconnection line example schematic diagram of two groups of bit wides such as opposite direction of the formation of possible configuration when FPGA carries out manufacturing test;

Fig. 4 is a BIST electrical block diagram of the prior art;

Fig. 5 is a BIST electrical block diagram provided by the present invention;

Fig. 6 is the vector generation of a kind of embodiment of the present invention and the structural representation of corresponding analysis device.

Embodiment

For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.

Advantages such as the FPGA device has the integrated level height, volume is little, can realize special application function by user program, and the cycle of designing and developing is short, reconfigurable, and then become the focus that electronic system develops.

CLB is the elementary cell that realizes user function in the FPGA basic structure, and a plurality of logic function blocks are lined up an array structure usually regularly, are distributed in whole fpga chip; IOB finishes the interface between fpga chip internal logic and the external terminal, is centered around around the logical cell array; IR comprises the line line segment and some switches that is connected able to programme of all lengths, and they couple together each CLB or IOB, constitutes the circuit of specific function.The user can determine the function of each unit and their interconnected relationship by programming, thereby realizes required logic function.When test, FPGA can be configured to and the different form of initial designs configuration.

Core idea of the present invention is, by in test configurations, utilize the CLB that is positioned at boundary in the FPGA device make up can be simultaneously as the test circuit of TPG (test vector generator) and ORA (test response analyzer), thereby test simultaneously by opposite unidirectional drive PIP of direction (programmable interconnect point) and the constructed two groups of WUT (tested interconnection line) of interconnect line segment.

The interconnection line test circuit that uses in a kind of FPGA of the present invention comprises: vector generates and response analysis device (TRG and ORA, TGAOA), described vector generates and the response analysis device can be even number, and per two vector generations are connected and form the built-in self-test circuit with the response analysis device by the interconnection line that direction is opposite, bit wide is n; Each vector in generation of described even number vector and the response analysis device generates and the response analysis device comprises that a n imports logic combination circuit and one group of n bit register of n output, and wherein, n gets natural number.

Two vectors of described built-in self-test circuit generate and the concrete annexation of response analysis device is:

The logic combination circuit C of primary vector generation and response analysis device ₁Input end connect that secondary vector generates and the interconnection line B of response analysis device ₂Output terminal,

The output terminal C of the logic combination circuit of primary vector generation and response analysis device ₁The register R that connects primary vector generation and response analysis device ₁Input end,

The register R of primary vector generation and response analysis device ₁Output terminal connect that primary vector generates and the interconnection line B of response analysis device ₁Input end,

The interconnection line B of primary vector generation and response analysis device ₁Output terminal connect that secondary vector generates and the logic combination circuit C of response analysis device ₂Input end,

The logic combination circuit C of secondary vector generation and response analysis device ₂Output terminal connect that secondary vector generates and the register R of response analysis device ₂Input end,

The register R of secondary vector generation and response analysis device ₂Output terminal connect that secondary vector generates and the interconnection line B of response analysis device ₂Input end;

Wherein, described register R ₁The reset values of [t] is 0 entirely, R ₂The reset values of [t] is 1 entirely;

And described logic combination circuit C ₁, C ₂Need to satisfy the formula (2) of following logical relation to formula (6).

With reference to Fig. 5 and shown in Figure 6, BIST circuit structure provided by the present invention is specially:

1: two can be simultaneously as the TGAOA of TPG and ORA ₁And TGAOA ₂, two prescriptions are the tested interconnection line B of n to opposite, bit wide (being number) ₁[t] and B ₂[t], (the t span is: 0≤t≤n-1);

2:TGAOA ₁Logic combination circuit C by n input n output ₁With one group of n bit register R ₁[t] forms;

Wherein, C ₁Input C ₁ ⁱBe B ₂The output terminal of [t], C ₁Output C ₁ ^oBe R ₁The input of [t], R ₁The output of [t] is B ₁The input end of [t];

3:TGAOA ₂Logic combination circuit C by n input n output ₂With one group of n bit register R ₂[t] forms;

Wherein, C ₂Input C ₂ ⁱBe B ₁The output terminal of [t], C ₂Output C ₂ ^oBe R ₂The input of [t], R ₂The output of [t] is B ₂The input end of [t];

Wherein, the proper polynomial as if n position LFSR (linear feedback shift register) is:

$1+x^{m_1}+x^{m_2}+...+x^{m_k}---\left(1\right)$

Then: C ₁The logic that realizes is:

${C_1}^o\left[0\right]={C_1}^i[m_1-1]\⊕{C_1}^i[m_2-1]\⊕...\⊕{C_1}^i[m_k-1]---\left(2\right)$

C ₁ ^o[t]＝C ₁ ⁱ[t-1]；(3)

C ₂The logic that realizes is:

${C_2}^o\left[0\right]={C_2}^i[m_1-1]\⊕{C_2}^i[m_2-1]\⊕...\⊕{C_2}^i[m_k-1]---\left(4\right)$

If C ₂ ⁱThe logical value of [t] is 0 entirely or is 1 entirely:

C ₂ ^o[t]＝～C ₂ ⁱ[t-1]；(5)

Otherwise:

C ₂ ^o[t]＝C ₂ ⁱ[t-1]； (6)

And n position LFSR (linear feedback shift register) R ₁The reset values of [t] is complete 0, R ₂The reset values of [t] is complete 1;

Wherein, m _kBe the index in the described proper polynomial, k is a natural number, 1≤k≤n-1, and the span of t is: 1≤t≤n-1;

Need to prove that the subscript o in the present specification represents described logic combination circuit C ₁, C ₂Output terminal, subscript i represents described logic combination circuit C ₁, C ₂Input end,

The presentation logic XOR ,=～presentation logic is anti-, described C ₁ ^o[0], C ₂ ^o[0] difference presentation logic combinational circuit C ₁, C ₂The logical value of the 0th output; C ₁ ⁱ[m _k-1], C ₂ ⁱ[m _k-1] difference presentation logic combinational circuit C ₁, C ₂M _kThe logical value of-1 input; C ₁ ^o[t], C ₂ ^o[t] be presentation logic combinational circuit C respectively ₁, C ₂The logical value of t position output; C ₁ ⁱ[t-1], C ₂ ⁱ[t-1] be presentation logic combinational circuit C respectively ₁, C ₂The logical value of t-1 position input.

That is to say that formula (2) is to the logic combination circuit C on the middle equal sign left side of formula (6) ₁, C ₂Subscript O presentation logic combinational circuit C ₁, C ₂N position output, the logic combination circuit C on equal sign the right ₁, C ₂Subscript i presentation logic combinational circuit C ₁, C ₂N position input, i.e. logic combination circuit C ₁, C ₂The 0th of output can be according to indicated m in the proper polynomial of corresponding n bit linear feedback shift register ₁, m ₂..., m _kCome m to input ₁, m ₂..., m _kThe position is carried out the logical operation XOR and is obtained;

M is the index in the proper polynomial (1), and k is a natural number, 1≤k≤n-1.

Above-mentioned for instance formula (1), if n=3, the proper polynomial that 3 LFSR are promptly arranged is 1+x ²+ x ³, m so ₁Just equal 2, m ₂Just equal 3, k just equals m ₂Subscript 2.Perhaps, during n=8, promptly the proper polynomial of 8 LFSR is 1+x ²+ x ³+ x ⁴+ x ⁸, m so ₁Just equal 2, m ₂Just equal 3, m ₃Just equal 4, m ₄Just equal 8, k just equals m ₄Subscript 4.

That formula (5) is represented is logic combination circuit C ₁, C ₂T position output valve equal logic combination circuit C ₁, C ₂The logical inverse of t-1 position input value, if logic combination circuit C ₁, C ₂The 0th be input as 0, the 1 and be input as 1, the 2 and be input as 1, logic combination circuit C so ₁, C ₂The 1st output just be 1, the 2 and be output as 0, the 3 and be output as 0.

When reality is tested, B ₁[t], R ₁[t], B ₂[t], R ₂[t], C ₁, C ₂Annexation is:

With reference to shown in Figure 6, in test configurations, utilize to be positioned at B ₁The drive end of [t] is B ₂Register resources among the SM corresponding C LB of the clearing end of [t] makes up TGAOA ₁In R ₁[t]; And utilize and be positioned at B ₂The drive end of [t] is B ₁Register resources among the SM corresponding C LB of the clearing end of [t] makes up TGAOA ₂In R ₂[t]; The drive end at this place is input end, and clearing end is output terminal.

In addition, in test configurations, utilize to be positioned at B ₁The drive end of [t] is B ₂The TGAOA that logical resource among the corresponding CLB of the SM of the clearing end of [t] makes up ₁In C ₁Be positioned at B and utilize ₁The drive end of [t] is B ₂The TGAOA that logical resource among the corresponding CLB of the SM of the clearing end of [t] makes up ₂In C ₂

Need to prove, need R in the test configurations ₁The reset values configuration of [t] is 0 entirely, R ₂The reset values configuration of [t] is 1 entirely; And in test configurations, the bit wide n of the interconnection line that each test configurations can be tested can not be greater than the number of the register among the CLB.

Concrete test process is as follows:

The first step: at first the register that vector is generated and responds carries out corresponding resetting, and is about to R ₁[t] resets is 0 entirely, R ₂[t] resets is 1 entirely;

Second step: repeat 2 ⁿ-1 following process:

Substep a) loads the clock signal of one-period;

Substep b) carries out a retaking of a year or grade, obtain this clock period R afterwards ₁[t] and R ₂The state of [t] if state and perfect condition are not inconsistent, promptly illustrates in the employed interconnect resource of interconnection line to have fault.

In actual applications, a) load the clock signal of one-period for substep, be described register all by a clock signal terminal, only in the effective edge of each clock signal, register just can be latched into the logical value on the data input pin in the register.Therefore, test the time need utilize be specifically designed to the clock signal wiring in the FPGA device interconnect resource with the BIST circuit in the clock signal of register be connected on the outside port, perhaps can perhaps can load clock signal by directly loading clock signal on the corresponding port by boundary-scan port scanning.

For substep b) carry out a retaking of a year or grade, the retaking of a year or grade operation at this place is to realize by load a series of control signal sequence on the special configuration control port of FPGA device, described control signal sequence will be deposited the value of the register in the FPGA device in the configuration sram cell, and then the logical value in the configuration sram cell is come out by scanning on the configured port.Like this, just can learn the logical value of the register in the FPGA device.

Need to prove, when the BIST test that the user carries out, for two groups of tested interconnection lines determining same bit-width, in test process, B ₁[t] and B ₂[t] goes up the test and excitation that loads and all fixes, (0≤t≤n-1);

For example when bit wide is 3, when resetting, B ₁[t] goes up the excitation that loads on the drive end is exactly R ₁The reset values 111 of [t], and B ₂[t] goes up the excitation that loads is exactly R ₂The reset values 000 of [t];

According to C ₂And C ₁Input (C ₂ ⁱAnd C ₁ ⁱ, i.e. B ₁[t] and B ₂[t]) output (C ₂ ^oAnd C ₁ ^o, i.e. R ₂[t] and R ₁[t]) logic corresponding relation, R at this moment ₂[t] and R ₁The logical value of the input end of [t] all is 011, then after the next clock period, and R ₂[t] and R ₁The desirable logical value of [t] all should be 011.

If B ₁[t] and B ₂The value of the clearing end of [t] is not 111 and 000, and show as and have fault on the interconnection line this moment, and according to C ₂And C ₁The logic function that is realized, R ₂[t] and R ₁The logical value of the input end of [t] can not be 011 just, so after the next clock period, and R ₂[t] and R ₁The logical value of [t] can not be 011 just.

Because BIST circuit design of the present invention has determined each cycle to go up at B ₁[t] and B ₂The activation sequence that is loaded on [t] is determined, and C ₂And C ₁The input and output logical relation that is realized is also determined, so R after each cycle ₂[t] and R ₁Desirable logical value in [t] is also determined.Therefore, if find R like this retaking of a year or grade the time ₂[t] and R ₁Logical value in [t] is not desirable logical value, just illustrates in the interconnection line and has made mistakes.

Below in conjunction with Fig. 5 and Fig. 6 the BIST circuit at bit wide interconnection lines such as two groups in the FPGA device are reverse provided by the present invention is described in detail.

In FPGA, there is a two-dimentional CLB array, in CLB, exists such as configurable logic and sequential resources such as LUT and registers, with the logic and the sequential function of design.All there is a SM corresponding to each CLB, links to each other by many PIP between the point on four limits up and down of described SM, then interconnect between the SM by some LS.SM and LS have constituted the interconnect resource of FPGA jointly, by PIP being programmed or disposing, can realize different interconnect functions.

As shown in Figure 5, the test circuit at interconnection line two ends no longer is to realize the TPG of test and excitation generation or the ORA that test response is observed, but both can realize that test and excitation generates, and also can realize the TGAOA that test response is observed.Wherein, TGAOA ₁And TGAOA ₂The vector that the structure explanation of introducing according to the front makes up generates and the response analysis device.

With the interconnection line that two groups of bit wides shown in Fig. 3 are 3, direction is opposite is example, corresponding TGAOA ₁And TGAOA ₂Structure as shown in Figure 6.

The proper polynomial of setting bit wide and be 3 LFSR is 1+x ²+ x ³

Then have, at C ₁In, ${C_1}^o\left[0\right]={C_1}^i\left[1\right]\⊕{C_1}^i\left[2\right]=B_2\left[1\right]\⊕B_2\left[2\right],$

And C ₁ ^o[1]=C ₁ ⁱ[0]=B ₂[0], C ₁ ^o[2]=C ₁ ⁱ[1]=B ₂[1];

At C ₂In, ${C_2}^o\left[0\right]={C_2}^i\left[1\right]\⊕{C_2}^i\left[2\right]=B_1\left[1\right]\⊕B_1\left[2\right],$

And C ₂ ^o[1] and C ₂ ^o[2] logical value then with B ₁[0], B ₁[1], B ₁[2] relevant;

Work as B ₁[0], B ₁[1], B ₁[2] be 0 entirely or be 1 o'clock entirely, C ₂ ^o[1] and C ₂ ^o[2] value just equals B respectively ₁[0] and B ₁[1] logical inverse, otherwise, just directly equal B ₁[0] and B ₁[1] logical value.

C ₁And C ₂Logical design make C ₁And C ₂Can be achieved as follows the logical relation of table one: C ₁And C ₂The input and output mapping relations; With table two: TGAOA ₁And TGAOA ₂Input and output logical mappings relation shown in the test and excitation sequence that is generated,

Wherein, the C in the table one ₁ ⁱ[0:2] represents in the logic combination circuit: C ₁ ⁱ[0], C ₁ ⁱ[1], C ₁ ⁱ[2];

C ₁ ^o[0:2] represents in the logic combination circuit: C ₁ ^o[0], C ₁ ^o[1], C ₁ ^o[2];

C ₂ ⁱ[0:2] represents in the logic combination circuit: C ₂ ⁱ[0], C ₂ ⁱ[1], C ₂ ⁱ[2];

C ₂ ^o[0:2] represents in the logic combination circuit: C ₂ ^o[0], C ₂ ^o[1], C ₂ ^o[2];

B in the table two ₂In the tested interconnection line of [0:2] representative: B ₂[0], B ₂[1], B ₂[2];

B ₁In the tested interconnection line of [0:2] representative: B ₁[0], B ₁[1], B ₁[2];

It should be noted that C ₁And C ₂The input and output logical mappings relation attribute below all satisfying: promptly for 2 ³Plant any of input combination, all have unique a kind of output combination corresponding with it.C ₁And C ₂This attribute of logic combination circuit makes that they can be with B ₂[0:2] and B ₁[0:2] changes into another logical value combination uniquely to the response results of any test and excitation.Therefore, if B ₂[0:2] and B ₁[0:2] wrong response occurs for certain test and excitation, then correspondingly, and R ₁[0:2] and R ₂Can occur wrong logical value combination in [0:2], thereby FPGA carried out the retaking of a year or grade operation and observing R ₁[0:2] and R ₂During logical value in [0:2], can detect fault.In addition, by with R ₁[0:2] and R ₂The reset values of [0:2] is made as complete 0 and complete 1, then comprises 2 of the reset cycle ³In-1=7 clock period, TGAOA ₁And TGAOA ₂Can be at B ₁[0:2] and B ₂Generate the as above activation sequence shown in the table one and table two on [0:2], this activation sequence combination can guarantee to detect B as can be seen ₁[0:2] and B ₂Bridging fault and persistent fault between [0:2] any two interconnection lines.

When using BIST circuit provided by the present invention to test, the bit wide n that interconnection line may occur surpasses the situation of the number m of available register, at this moment tested interconnection line can be divided into the interconnection line that a plurality of bit wides are two groups of bit wides such as opposite direction of m, repeatedly test in the test configurations then.Obviously, in this case,, adopt BIST circuit provided by the present invention to test needed configuration and want much less than traditional BIST circuit structure.(traditional B IST circuit needs

Individual configuration, and the present invention only needs

Individual configuration)

A kind of new FPGA interconnect resource method of testing that is applicable to unidirectional drive PIP interconnection structure that the present invention proposes mainly is at logic and register resources features of limited among unidirectional drive PIP interconnection structure that is adopted in the existing large-scale F PGA device and the CLB, by in test configurations, utilize the CLB that is positioned at boundary in the FPGA device make up can be simultaneously as the test circuit of TPG and ORA, thereby simultaneously to testing by direction opposite unidirectional drive PIP and two groups of constructed WUT of interconnect line segment.When this method is carried out the interconnect resource test to the FPGA device that adopts unidirectional drive PIP interconnection structure, can with the decreased number of test configurations half, thereby reduce testing cost greatly.Because this method adopts BIST (built-in self-test) scheme, can be applicable to the manufacturing test of interconnect resource in the FPGA device simultaneously and in system testing.

More than the interconnection line circuit that uses in a kind of FPGA in the embodiment of the invention is described in detail; For simple description, thus it all is expressed as the combination of unit, but those skilled in the art should know that the present invention is not subjected to the restriction of described structural unit position relation.In addition, those skilled in the art also should know, the embodiment described in the instructions all belongs to preferred embodiment, and related action and unit might not be that the present invention is necessary.

Each embodiment in this instructions all adopts the mode of going forward one by one to describe, and what each embodiment stressed all is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.More than the interconnection line circuit that uses in a kind of FPGA device provided by the present invention is described in detail, used specific case herein principle of the present invention and embodiment are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.

Claims (1)

1, the interconnection line test circuit that uses in a kind of FPGA is characterized in that, comprising:

The even number vector generates and the response analysis device, and each vector in vectorial generation of described even number and the response analysis device generates and the response analysis device comprises logic combination circuit and one group of n bit register that a n input n exports, and wherein, n gets natural number;

Per two vectors generate and the response analysis device connects to form the built-in self-test circuit by the interconnection line that direction is opposite, bit wide is n, and described built-in self-test circuit is: the logic combination circuit C of primary vector generation and response analysis device ₁Input end connect that secondary vector generates and the interconnection line B of response analysis device ₂Output terminal, primary vector generates and the logic combination circuit C of response analysis device ₁Output terminal connect that primary vector generates and the register R of response analysis device ₁Input end, primary vector generates and the register R of response analysis device ₁Output terminal connect that primary vector generates and the interconnection line B of response analysis device ₁Input end, primary vector generates and the interconnection line B of response analysis device ₁Output terminal connect that secondary vector generates and the logic combination circuit C of response analysis device ₂Input end, secondary vector generates and the logic combination circuit C of response analysis device ₂Output terminal connect that secondary vector generates and the register R of response analysis device ₂Input end, secondary vector generates and the register R of response analysis device ₂Output terminal connect that secondary vector generates and the interconnection line B of response analysis device ₂Input end;

Wherein, described register R ₁The reset values of [t] is 0 entirely, R ₂The reset values of [t] is 1 entirely, and described logic combination circuit C ₁, C ₂Satisfy following logical relation:

For logic combination circuit C ₁, C ₂Shu Chu the 0th logical value is respectively:

Logic combination circuit C ₁, C ₂Shu Chu the 0th logical value is separately by z logic combination circuit C respectively ₁, C ₂Input logic value XOR obtain, the proper polynomial that described z sets for the n bit register is $1+x^{m_1}+x^{m_2}+...+x^{m_k}$ Value,

${C_1}^o\left[0\right]={C_1}^i[m_1-1]\⊕{C_1}^i[m_2-1]\⊕...\⊕{C_1}^i[m_k-1]$

${C_2}^o\left[0\right]={C_2}^i[m_1-1]\⊕{C_2}^i[m_2-1]\⊕...\⊕{C_2}^i[m_k-1]$

For logic combination circuit C ₁N-1 position logical value is arrived in the 1st of output:

Logic combination circuit C ₁The t position logical value of output is corresponding logic combination circuit C ₁The input logic value of last position, C ₁ ^o[t]=C ₁ ⁱ[t-1], 1≤t≤n-1;

For logic combination circuit C ₂N-1 position logical value is arrived in the 1st of output:

If C ₂ ⁱ[t] is complete 0 or C ₂ ⁱ[t] is complete 1 o'clock, then logic combination circuit C ₂The t position of output equals corresponding logic combination circuit C ₁The logical inverse of the input logic value of last position:

C ₂ ^o[t]=～C ₂ ⁱ[t-1], 1≤t≤n-1, wherein ,=～presentation logic is anti-;

Otherwise, logic combination circuit C then ₂The t position of output equals corresponding logic combination circuit C ₁The input logic value of last position: C ₂ ^o[t]=C ₂ ⁱ[t-1], 1≤t≤n-1;

m _kBe the index in the described proper polynomial, k is a natural number, 1≤k≤n-1,

Wherein, above-mentioned subscript o represents described logic combination circuit C ₁, C ₂Output terminal, subscript i represents described logic combination circuit C ₁, C ₂Input end,

The presentation logic XOR.

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