CN102565682A - Method for positioning fault testing vectors on basis of bisection method - Google Patents

Method for positioning fault testing vectors on basis of bisection method Download PDF

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Publication number
CN102565682A
CN102565682A CN2010105871636A CN201010587163A CN102565682A CN 102565682 A CN102565682 A CN 102565682A CN 2010105871636 A CN2010105871636 A CN 2010105871636A CN 201010587163 A CN201010587163 A CN 201010587163A CN 102565682 A CN102565682 A CN 102565682A
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test
vector
testing
fault testing
subclass
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CN2010105871636A
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CN102565682B (en
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唐飞
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苏州工业园区谱芯科技有限公司
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Abstract

The invention discloses a method for positioning fault testing vectors on the basis of a bisection method, which comprises the following steps of: loading the testing vectors onto a circuit to be detected and outputting characteristic sequence values corresponding to the testing vectors; obtaining expected characteristic sequence values by responding to a compressor and comparing the expected characteristic sequence values with the actually measured characteristic sequence values; if the expected characteristic sequence values are inconsistent with the actually measured characteristic sequence values, obtaining a result that a certain fault points are possibly detected on the circuit to be detected, and then roughly and equally dividing a testing vector set into a first subset and a second subset; directly finding a first fault testing vector which causes the testing failure by using the first subset as a novel test object; and finishing the testing vectors which are not positioned and repeating the steps by using the testing vectors which are not positioned as a novel testing vector set until all the fault testing vectors are found. According to the positioning method disclosed by the invention, the testing vector set is divided and then the test is respectively carried out, so that the testing times are greatly reduced and the efficiency is high.

Description

A kind of localization method of the fault testing vector based on dichotomy

Technical field

The present invention relates to the technical field of hardware testing, relate in particular to integrated circuit board electrodes production test field.

Background technology

Along with dwindling day by day of integrated circuit technology size and improving constantly of circuit complexity; SOC(system on a chip) (System-on-Chip particularly; SoC) appearance and widespread use, the integrated level of VLSI (very large scale integrated circuits) have developed into can the above degree of integrated several ten million transistors on the chip.So exploring and use low cost, high efficiency measuring technology and test macro has become an important topic in the chip testing.

Utilizing logic built-in self-test technology (Logic Built-In Self-Test; When LBIST) carrying out the chip-scale fault test; The diagnosis capability that the fault coverage of test and localization of fault precision depend on test vector, the test duration is depended on the length of the number of times and the logic built-in self-test scan chain of logic built-in self-test.For specific circuit under test, the length of scan chain is fixed, thereby the test duration is depended on the number of times of test.In practical application, both required test vector to have the high fault diagnosis ability, again testing time there is higher requirement.

Test vector to breaking down positions, the general characteristic vector sequence value of gathering through the vectorial characteristic vector sequence value of gathering of comparison nominative testing and the test vector of actual test gained, thus judge whether there is fault testing vector in the set.Please join shown in Figure 1; Traditional linear orientation method need be done single test to each test vector of test vector collection the inside; Come to confirm at last all test vector that causes this test failure combinations, the method exists the problem that the test duration is long and testing time is many.

Summary of the invention

The object of the present invention is to provide a kind of localization method of the fault testing vector based on dichotomy, make that test is more efficient.

For realizing above goal of the invention, the present invention adopts following technical scheme: a kind of localization method of the fault testing vector based on dichotomy comprises the steps:

S1: circuit under test is connected to test board;

S2: configuration testing vector generator and the kind subsequence of response compressor reducer and the number of test vector, to generate some test vectors, all test vectors are formed the test vector set, in order to circuit under test is detected;

S3: test vector is loaded on the circuit under test, accomplishes up to all test vector tests;

S4: the characteristic sequence value of corresponding test vector among the output step S3;

S5: obtain the desired character sequential value through the response compressor reducer, and the actual characteristic sequence value that records among itself and the step S4 is made comparisons;

S6: if both results are consistent, the test of this circuit under test through current test vector set is described, can not detected any trouble spot;

S7:, then above-mentioned test vector set is divided into first subclass and second subclass if both results are inconsistent;

S8: as new tested object, repeating step S2 to S7 is up to finding first fault testing vector that causes test crash with first subclass;

S9: the test vector that arrangement is not positioned, as a brand-new test vector set, repeating step S2 to S8 is all found up to all fault testing vectors with it.

As further improvement of the present invention, among the step S3, load test vector through the logic bist instruction.

As further improvement of the present invention, among the step S4, the characteristic sequence value of test vector is exported through using the logic bist instruction once more.

As further improvement of the present invention, said response compressor reducer is provided with software simulator, and the characteristic sequence value of expecting among the step S5 draws through this software simulator.

As further improvement of the present invention, said test vector generator comprises one group of linear feedback shift register (LSFR).

As further improvement of the present invention; Among the step S8; If the first subclass test crash is tested with regard to further this first subclass being divided into littler subclass again, so go on; In subclass, only contain a test vector, this test vector is first fault testing vector.

As further improvement of the present invention, if sub a set when testing successfully, when another relative subclass would also only remain a test vector, just this test vector is regarded as fault testing vector automatically.

Compared to prior art, the localization method that the present invention is based on the fault testing vector of dichotomy is divided test vector set, then test respectively; Greatly reduced testing time; Shortened the test duration, thereby can locate fast and effectively a large amount of test vectors, efficient is high.

Description of drawings

Fig. 1 is logic built-in self-test ultimate principle figure.

The basic framework figure of the general built-in self-test of Fig. 2 institute of the present invention foundation.

Fig. 3 is the basic circuit structure figure of linear feedback shift register.

Embodiment

The present invention is based on the localization method of the fault testing vector of dichotomy; Mainly utilize the built-in self-test technology to carry out the test of chip-scale logic fault; Be about to circuit under test and be connected to test board; Generate the test vector set through test board, and this test vector set is loaded on the circuit under test, judge through the contrastive test result whether circuit under test passes through the test of test vector set.Said test board meets the basic framework of general built-in self-test.Please join shown in Figure 2ly, said test board is provided with test controller 1, and it comprises test vector generator 11 and response compressor reducer 12.Please join shown in Figure 3, said test vector generator 11 comprise one group of linear feedback shift register (Linear Feedback Shift Register, LSFR).Through configuration testing vector generator 11 and the kind subsequence of response compressor reducer 12 and the number of test vector, just can generate some test vectors.All test vectors are formed the test vector set, in order to circuit under test is detected.The number of test vector depends on the selection of tandom number generator seed and the circuit state quantity and the complexity of circuit under test thereof.But,, just can calculate the value of any initial seed of test vector and the cycle tests of any a plurality of test vectors subsequently thereof as long as the basic structure of test vector generator 11 confirms.

Test Application is according to logic built-in self-test flow process, through the logic bist instruction test vector is loaded on the circuit under test, accomplishes up to all test vector tests.Through the test of certain hour,, obtain one group of characteristic vector sequence to test vector and circuit under test by responding all test results of compressor reducer 12 collections and compressing.Utilize the software simulator of test vector generator and response compressor reducer, obtain the desired character sequential value.Through relatively expecting characteristic vector sequence value and the sequential value that actual test obtains, just can judge whether to exist some or a plurality of test vectors to detect some trouble spots.

The present invention is based on the localization method of the fault testing vector of dichotomy, comprise the steps:

S1: circuit under test is connected to test board through cable, guarantees to connect correctly, in order to avoid influence the correctness of test result;

S2: configuration testing vector generator and the kind subsequence of response compressor reducer and the number of test vector on test board, to generate some test vectors, all test vectors are formed the test vector set, in order to circuit under test is detected;

S3: according to logic built-in self-test flow process, test vector is loaded on the circuit under test, accomplishes up to all test vector tests through the logic bist instruction;

S4: the characteristic sequence value (in this embodiment, the characteristic sequence value of test vector is exported through using the logic bist instruction once more) of corresponding test vector among the output step S3;

S5: obtain the desired character sequential value through response compressor reducer 12; And the actual characteristic sequence value that records among itself and the step S4 made comparisons (in this embodiment; Response compressor reducer 12 is provided with software simulator, and this step desired characteristic sequence value draws through this software simulator);

S6: if both results are consistent, the test of this circuit under test through current test vector set is described, can not detected any trouble spot;

S7: if both results are inconsistent, explain that this circuit under test fails the test through the set of current test vector, possibly detect some trouble spot, and subsequently above-mentioned test vector set is divided into the first subclass V about equally 0With the second subclass V 1

S8: with the first subclass V 0As new tested object, repeating step S2 to S7 is up to finding first fault testing vector that causes test crash;

S9: the test vector that arrangement is not positioned, as a brand-new test vector set, repeating step S2 to S8 is all found up to all fault testing vectors with it.

The emphasis of localization method that the present invention is based on the fault testing vector of dichotomy is: when fault testing vector is specifically located; Test vector to be positioned is treated as a set; And this set is divided into two equal-sized subclass, the i.e. first subclass V as much as possible 0With the second subclass V 1Then, respectively to the first subclass V 0With the second subclass V 1Test, if the test of some subclass is passed through, fault testing vector is described not therein, all test vectors in this subclass will be excluded.

Otherwise, if test crash (step S7) then further is divided into two littler subclass V about equally with this subclass 00, V 01And V 10, V 11, so go on, in subclass, only contain a test vector, this test vector is first fault testing vector.In above-mentioned test process, when a sub-set is tested successfully, if the also only surplus test vector of another relative subclass, just then this test vector would be regarded as fault testing vector automatically, to reduce once test.

Compared to prior art, the present invention possesses following beneficial effect:

(1). testing time is few; To the combination of test vector arbitrarily, owing to only be the simple division to the test vector set, testing time all seldom thereby can be located a large amount of test vectors fast and effectively, and efficient is high.

(2). fault coverage is high; Because localization method location efficiency of the present invention is higher, thereby can improve fault coverage through the scale of effective increase test vector.

(3). test vector is realized simple; Get final product owing to only need circuit under test be connected to test board through cable, easy to operate.

In sum; More than be merely preferred embodiment of the present invention; Should not limit scope of the present invention with this, promptly every simple equivalent of being done according to claims of the present invention and description of the invention content changes and modifies, and all should still belong in the scope that patent of the present invention contains.

Claims (8)

1. the localization method based on the fault testing vector of dichotomy is characterized in that, comprises the steps:
S1: circuit under test is connected to test board;
S2: configuration testing vector generator and the kind subsequence of response compressor reducer and the number of test vector, to generate some test vectors, all test vectors are formed the test vector set, in order to circuit under test is detected;
S3: test vector is loaded on the circuit under test, accomplishes up to all test vector tests;
S4: the characteristic sequence value of corresponding test vector among the output step S3;
S5: obtain the desired character sequential value through the response compressor reducer, and the actual characteristic sequence value that records among itself and the step S4 is made comparisons;
S6: if both results are consistent, the test of this circuit under test through current test vector set is described, can not detected any trouble spot;
S7:, then above-mentioned test vector set is divided into first subclass and second subclass if both results are inconsistent;
S8: as new tested object, repeating step S2 to S7 is up to finding first fault testing vector that causes test crash with first subclass;
S9: the test vector that arrangement is not positioned, as a brand-new test vector set, repeating step S2 to S8 is all found up to all fault testing vectors with it.
2. the localization method of the fault testing vector based on dichotomy as claimed in claim 1 is characterized in that: among the step S3, load test vector through the logic bist instruction.
3. the localization method of the fault testing vector based on dichotomy as claimed in claim 1, it is characterized in that: among the step S4, the characteristic sequence value of test vector is exported through using the logic bist instruction once more.
4. the localization method of the fault testing vector based on dichotomy as claimed in claim 1, it is characterized in that: said response compressor reducer is provided with software simulator, and the desired character sequential value among the step S5 draws through this software simulator.
5. the localization method of the fault testing vector based on dichotomy as claimed in claim 1, it is characterized in that: said test vector generator comprises one group of linear feedback shift register (LSFR).
6. the localization method of the fault testing vector based on dichotomy as claimed in claim 1; It is characterized in that: among the step S8; If the first subclass test crash is tested with regard to further this first subclass being divided into two littler son set again, so go on; In subclass, only contain a test vector, this test vector is first fault testing vector.
7. the localization method of the fault testing vector based on dichotomy as claimed in claim 6; It is characterized in that: if a son set is tested successfully; When another relative subclass also only remained a test vector, this test vector was just regarded as fault testing vector automatically.
8. the localization method of the fault testing vector based on dichotomy as claimed in claim 1, it is characterized in that: the size of said first subclass and second subclass about equally.
CN201010587163.6A 2010-12-14 2010-12-14 Method for positioning fault testing vectors on basis of bisection method CN102565682B (en)

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