JPS6118785B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory circuit useful for testing and diagnosing logic devices.

Conventional memory circuits include a write address designation signal, a read address designation signal, write data, a read data output, and a clock signal that defines the write timing, and write data given to the address specified by the write address designation input. It is configured to write in synchronization with the supply of a clock signal, and to read out the stored contents at an address designated by a read address designation signal as read data. This storage circuit is used for the purpose of temporarily holding data to be processed within the logic device.

It is generally known that a functional test of a sequential logic circuit device composed of gate circuits and registers can be easily performed by converting the target sequential logic circuit into a pseudo combinational circuit at the time of testing. In other words, in this method, in addition to the original function of each register in the circuit under test, a configuration is adopted in which all registers function as shift registers based on control signals, and during testing, all registers are transferred via the shift register path. An arbitrary value is set in the register,
After normal operation of the circuit, the contents of all registers are read out again via the shift register path by the control signal.This allows all registers of the target sequential circuit to be treated equally as input terminals and output terminals of the circuit. .

However, in order to apply this test method to a conventional logic device containing the aforementioned memory circuit, it is necessary to incorporate all the bits of the memory circuit into the shift register path; It is difficult to add a circuit like this because the amount of addition is enormous and this additional circuit significantly degrades the original performance of the memory circuit. Therefore, during testing, as shown in Figure 1, A method is adopted in which a memory circuit 13 existing between a first logic circuit 11 (including gates and registers) and a second logic circuit 12 (including gates and registers) is quickly routed. In this system, it is necessary to operate the data switching circuit 15 by the state specifying means 14 to switch the data 16 from the storage circuit and the data from the switching circuit 17. In this method, when testing using a shift register path, the memory circuit is not tested, so a separate test must be performed, which complicates the test. The memory circuit 1 is transferred again via the second logic circuit 12 and the first logic circuit 11 without including a register circuit.
In the case of 3 inputs, a loop of logic signals occurs and the logic state may not be determined.

An object of the present invention is to provide a memory circuit that allows easy functional testing.

The memory circuit of the present invention includes a memory means for storing data, a state specifying means for specifying whether the memory means should be used in a normal state or a shifted state, and a shift state is specified by the state specifying means. An address counter that increments only when the
A write means writes write data to a storage location of the storage means determined by the output signal of the counter, and a write address determined by the read address signal given from the outside in the normal state and by the output signal of the address counter in the shift state. In the normal state, data given from the outside is read out by the reading means, and in the shift state, data shifted by 1 bit and data shifted by 1 bit from the outside are stored. and a write data supply means for supplying write data to the means.

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 shows an embodiment of the memory circuit of the present invention, including a state designation signal input 21, a clock signal input 22, an address counter 23, a write circuit 24, a read means 25, and a write data supply circuit 26. is configured. The address counter 23 is positive only at the leading edge of the clock signal 22 (when changing from a logic value "0" to a logic value "1") when the state designation signal 21 is in a shift state (logical value "1"). 1, and when the state designation signal 21 is in the normal state (logical value "0"),
The output state is maintained regardless of changes in the clock. Further, the reset signal 27 has the function of setting the address counter 23 to a predetermined initial state.

The write circuit 24 is a write address selection circuit 2
8, a write address storage circuit 29, a write address decoding circuit 30, and an AND circuit 31. The storage circuit referred to here is a circuit that outputs the input as is when the applied clock signal has a logical value of "0", and holds the output when the applied clock signal has a logical value of "1". When the state designation signal 21 has a logic value of "0" (normal state), the write address selection circuit 28 selects the external write address designation signal 32, and when the state designation signal 21 has a logic value of "1" (shift state), it selects the write address designation signal 32 of the address counter 23. This selects the output signal. The selected write address designation signal is input to the write address storage circuit 29, and the output of the write address storage circuit 29 is input to the write address decoding circuit 30. The decoding result of the write address decoding circuit 30 and the clock signal 22 are supplied to an AND circuit 31. As a decoding result from the write address decoding circuit 30, only one output signal has a logic value of "1" in accordance with the output of the write address storage circuit 29, and all others have a logic value of "0". Therefore, the output of the AND circuit 31 to which the output signal of the write address decoding circuit 30 is given the logical value "0" becomes a logical value "0" regardless of the state of the clock signal 22, and the output signal of the write address decoding circuit 30 becomes the logical value "0". The output of the AND circuit 31, which is given an output with the logical value "1", is:
Logical value “1” when the clock signal is logical value “1”
When the logic value is "0", the logic value becomes "0". AND
Each output signal of the circuit 31 and the output signal 33 of the write data supply circuit 21 are applied to a memory cell 34 at each intersection arranged in a matrix. This operation of changing the state of the memory cell 34 was selected by the write address decoding circuit 30 in the state of only logical value "1".
The output from the AND circuit 31 is set to a logic value "1" by the clock signal 22, and the data holding function of the memory cell 34 connected to this output is temporarily lost, resulting in a bit line (output of the write data supply circuit) state. This is executed by setting the corresponding state.

Next, in the readout circuit 25, the readout address selection circuit 35 selects a readout address designation signal 36 from the outside when the state designation signal 21 has a logic value of "0" (normal state) and a logic value of "1" (shift state). ), the output signal of the address counter 23 is selected. In the read operation, the output of the read selection circuit 35 is decoded by the read address decoding circuit 37, and the content of the memory cell at the activated address is transferred to the sense line 3 by the output having the only logic value "1".
8 and is read out by the output buffer circuit 39,
It is executed by being output to the data output terminal 40. Furthermore, the write data supply circuit 26
It consists of a write data selection circuit 41 and a write data storage circuit 42. The write data selection circuit 41 has a state designation signal 21 of logical value “0”.
When the logic value is "1" (shift state), the data from the output buffer circuit 39 is input as 1 bit.
Shifted data is selected. At this time, shift input data 44 from the outside is supplied to the missing bit positions due to the one-bit shift. The output of the write data selection circuit 41 is input to the write data storage circuit 42 and the clock signal 22
When the logic value is "0", the input is output as is, and when the logic value is "1", the output is held. Note that the data output (the rightmost 4
0) is treated as a shift output in the shift state. Now, the state designation signal 21 has a logic value of "0" (normal use state), and the clock signal 22 has a logic value of "0".
At this time, the write address selection circuit 28, the read address selection circuit 35, and the write data selection circuit 41 receive the write address designation signal 32 from the outside, respectively.
The read address designation signal 36 and the write data input 43 are selected, and the write address storage circuit 29
The write data storage circuit 42 is in a state where its input is output as is. At this time, since the clock signal 22 has a logical value of "0", the AND
All output signals of the circuit 31 have a logical value of "0", and all memory cells are not affected in any way. As the clock signal 22 changes from the logic value "0" to the logic value "1", both storage circuits 29 and 42 shift to the output holding state, and the memory cell 34 at the address specified by the write address storage circuit 29 is The state of the write data storage circuit 42 is shifted to a state where it is output as is. Subsequent changes in the states of the write address designation signal 32 and the write data input 43 will occur in both storage circuits 29 and 42.
Since it is in a holding state, it does not affect the internal memory cell 34 in any way. In other words, in the write operation, the clock signal 22 changes from the logical value "0" to the logical value "1".
This is performed using the write address designation signal and the write data at the time when the change occurs. Further, the contents of the memory address specified by the read address designation signal 36 are read out to the data output terminal 40. Next, when the state designation signal 21 designates the logical value "1" (shift state), the write address selection circuit 28 and read address selection 35 both select the output of the address counter 23, the write data selection circuit 41 selects the data obtained by shifting the data of the output buffer circuit 39 by 1 bit and the shift input data 43, and the address counter 23 selects the output of the address counter 23. It is in a state where it can step in synchronization with the clock signal 22. In this state, when the clock signal 22 has a logic value of "0", the write address storage circuit 29 and the write data storage circuit 42 output their inputs as they are, but the output signals of the AND circuit 31 all have a logic value of "0". ”, so all memory cells are not affected in any way. At this time, both address decoding circuits 30 and 37 designate the same address because their input address designation signals are both outputs of the address counter 23. Therefore, the address being read at this point is the address to be written next, and the write data is a combination of the data being read out at this point shifted by 1 bit and the shifted input data. It is. When the clock signal 22 changes from the logical value "0" to the logical value "1", both storage circuits 29 and 42 shift to the output holding state, and the storage cell 34 specified by the write address storage circuit 29
The state shifts to a state where the state of the write data storage circuit 42 is output as is. At this time, the address counter 23 is also incremented and its contents are incremented by one. Therefore, the output of the read address decoding circuit 37 changes and the contents of the next address are read, but since both storage circuits 29 and 42 are in the holding state, the internal memory cell 34 is not affected at all. As a result, the contents of one address are shifted by one bit and rewritten. Note that shift input data from the outside is written in the bit positions that are shifted and missing at this time.

4 words about shift operation in shift state ×
Taking a 4-bit memory circuit as an example for further explanation, FIG. Only the shift input data terminal (upper left), shift output (lower right: output data that is not rewritten), and the address specified by the address counter (arrow on the right side) are shown. In this state, when the clock signal changes from the logic value "0" to the logic value "1", the clock signal shown in Fig. 3B
As shown in the figure, three bits of the contents of address 0 are written in a state shifted by one bit to the right, and at the same time, shift input data Q is written to the leftmost bit position. Also, at this time, the contents of the address counter are incremented by 1, so the contents of address 1 are read out to the output terminal. Similarly, FIGS. 3C to 3H show how the memory circuit changes each time the clock signal changes from logic value "0" to logic value "1". As the clock signal is further changed, it is easy to see that the data input from the shift input terminal is output in the same order as when it was input. Next, FIG. 4 shows how a plurality of such memory circuits are cascaded with respect to the shift path. In this figure, the shift output 5 of the first storage circuit 50
1 is connected to the shift input data terminal 53 of the second memory circuit 52, and the shift output 54 of the second memory circuit 52 is connected to the shift input data terminal 56 of the third memory circuit 55. As a result, when the shift state is designated by the state designation signal, the shift input data terminal 57 is changed to the shift output terminal 58.
In between, a shift register is formed which includes in its path all the bits of the storage circuit.

Therefore, in the logic circuit device using the memory circuit of this embodiment, the state of all memory elements (registers and memory circuits) in the device can be set to any value via the shift register path by the state designation signal. Furthermore, after normal operation, the contents of all storage elements can be read out again via the shift register path by a state designation signal. This makes it possible to treat all memory elements of the logic circuit device including memory elements equally as input terminals and output terminals of the device.

Although this embodiment shows an example in which the external write address designation signal and the external read address designation signal are independent, the present invention can also be applied to a configuration in which they are shared. In this case, it is possible to share the address decoding circuit, the bit line, the sense line, etc., but in the normal state, it becomes impossible to independently execute the write operation and the read operation. However, there is no problem in the shift state.

As explained above, the present invention has the advantage that it can provide a memory circuit that is effective for inspection and diagnosis by configuring all bits of the memory circuit to be incorporated into the shift register path based on the state designation input.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a logic device including a conventional memory circuit, FIG. 2 is a diagram showing an embodiment of the present invention, and FIGS. 3A to 3H explain the operation of the embodiment of the present invention. FIG. 4 is a diagram showing a state in which the memory circuits of the present invention are connected in cascade with respect to the shift path. In the figure, 11, 12...logic circuit, 1
3, 50, 52, 55...Memory circuit, 14, 21
...State designation signal, 15...Data switching circuit, 2
2... Clock signal, 23... Address counter, 24... Write circuit, 25... Read circuit, 26... Write data supply circuit, 28...
Write address selection circuit, 29...Write address storage circuit, 30...Write address decoding circuit, 32...
...Write address designation signal from outside, 34...Storage cell, 35...Read address selection circuit, 36...
... Read address designation signal from outside, 37 ... Read address decoding circuit, 39 ... Output buffer circuit, 40 ... Data output terminal, 41 ... Write data selection circuit, 42 ... Write data storage circuit, 43 ... External write data signal, 4
4, 53, 56, 57...Shift input data, 5
1, 54, 58... are shift outputs.

Claims (1)

[Claims] 1 A storage means for storing data, a state specifying means for specifying whether the memory means should be used in the normal state or in the shifted state, and a clock signal is provided only when the shifted state is specified by the state specifying means. The address whose contents are to be advanced synchronously.
a counter, and a storage position of the storage means determined by a write address signal given from the outside when the normal state is designated by the state designation means, and by an output signal of the address counter when the shift state is designated. writing means for writing write data into the memory; and when the normal state is designated by the state designation means, the determination is made by a read address signal applied from the outside, and when the shift state is designated, the output signal of the address counter is determined. A readout means reads data from a corresponding storage location of the storage means; and when a normal state is designated by the state designation means, the data given from the outside is read out; and when a shift state is designated, the readout means reads out the data. A memory circuit comprising write data supply means for supplying bit-shifted data and external 1-bit shifted input data as write data of the memory means, wherein in a shift state, all bits of the memory circuit are transferred to the shift register. A memory circuit characterized in that it can be incorporated into a path.