JPS583188A - Address decoding system - Google Patents

Abstract

PURPOSE:To reduce the access time, by directly inputting an address to a decoding circuit and applying the output of this circuit to a signal storage circuit. CONSTITUTION:An address A0-n is first applied to a decoder DEC for decoding. An output *DEC0-n is applied to a terminal D of a flip-flop and stored with an address set clock CLK-E. As a result, decoding outputs DEC0E-CnE are obtained from an output Q' terminal of the flip-flop. This is mentioned for ''E side'' and this can also be applied to ''O side''. All the decoding signals DEC0O-CnO can be selected at memory refresh by inputting a refresh signal *REFCY to reset terminals R of the flip-flops.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an address decoding method for a storage device that can reduce reaccess time l.

A conventional address decoding method for accessing a memory and storing data will be explained with reference to FIGS. 1 and 2. FIG. 2 shows a case where the memory is divided into two blocks and each block is activated by a different memory access go signal (memory activation signal). At this time, each memory block is designated as E1llll and Ollll for convenience.
It is called l.

The E side will be explained below. , Ao−An is n+
1 bit is used as the access address given to the address bus, and the memory access go signal E side %GO1[
If i is given in the middle of specifying the "E side" address, the register F consisting of the flip-flop FF-P
FoE to FFnB are the “E side” address set clock OLK-1[! held by. After that, the outputs of the flip-flops A E O to AKn are sent to the decoder DEC.
is applied to and decoded. Only one of the decode outputs -%DOoE to %DOnFi is selected (“0”) and applied to one side of the NAND circuit NAND, and the logical OR operation is performed with the refresh cycle signal -X-REPOY applied to the other side, and the arithmetic output is output. That is, the decoded signal DIIiOQ
E to DFiOnK. Only one is selected (l") except during refreshing, and all are selected (all "1") during refreshing.

The above operation is the same for all addresses on the "0 side". Note that the application times of the refresh go IN signal %RFGδ and the refresh cycle signal %REFOY are indicated by dotted lines at the bottom of FIG.

The refresh cycle signal %RIFOY is a signal for "all selecting" the decoded signal DEOoP etc. at the time of memory refresh, and is "0" at the time of refresh.
"', the decode signal is set to all "L" and is held for 1 memory cycle. At this time, the address set clock 0L
KEi or 0LKOl Ememory access go signal
It is created from CLE or arrow Gδ6 ID number, and then the address is held in a flip-flop, so it is decoded after the address is given, including the decoding time, such as 2. As shown in Figure 1, it takes a long time to obtain the address DECoE, etc. Furthermore, since it requires twice as many NAND circuits as the number of address bits, the circuit configuration is complicated.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an address decoding method for a storage device that can improve the above-mentioned drawbacks and shorten memory access time with a simple configuration. Therefore, the gist of the present invention is characterized in that the address is directly applied to the circuit for decoding the address, and the output 1:r of the circuit is applied to the signal holding circuit.

Tru. FIG. 3 shows an embodiment of the present invention corresponding to FIG. 2, and FIG. 4 shows an operation time chart of FIG. In FIG. 3, the same reference numerals as in FIG. 1 indicate similar parts.

Addresses Ao to An are first applied to the decoder DEC and decoded. The output signals X-DEOO to %DIOn are then applied to the D terminal of the flip-flop and held by the address set clock CLK-E. As a result, the decode output DECo is output from the output terminal of the flip-flop.
Obtain E to DFiOnE'q. The above description has been made regarding the "E side", but the same applies to the "0 side".

Also refresh signal %RF! By inputting FOY to the reset terminal R of the flip-flop.

When refreshing the memory, all decode signals DFiOQE to DKOnδ are selected. In the operation time chart of Fig. 4, from address application time TO to decode output %D
KOo-%D1i! Time T until T2 when On is obtained
It can be seen that O-T2 is much shorter than the similar time TO-T1 in FIG.

In this manner, according to the present invention, since the address is decoded during the rise of the memory access activation signal after the address is applied, the time until the address set clock signal is created by the memory access activation signal does not become a loss time. . That is, the memory access time becomes faster, a NAND circuit is not required, and the refresh cycle signal is used to reset the 7-lip-flop, so the overall circuit is simplified.

[Brief explanation of the drawing]

Fig. 1 shows an example of a conventional decoding system circuit, Fig. 2 shows a + time chart in Fig. 11, Fig. 3 shows an embodiment of the present invention, and Fig. 4 shows the timing diagram of Fig. 3. Show chart. DFtO...Decode circuit FF'...Flip-flop patent applicant Fujitsu Co., Ltd. Representative Eisuke Benkondo Suzuki

Claims (1)

[Claims] In an address decoding method in which a storage device is accessed by decoding an address given on a data bus, the address is input directly to a circuit for decoding, and the output of the decoding circuit is applied to a signal holding circuit and held. Characteristic address decoding method.