JPS59186193A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To decrease the wiring resistance by providing a selection switch decoding circuit and a selection switching circuit at each block included in divided decoding circuits. CONSTITUTION:Blocks 1, 2- having the decoding circuits divided and formed into blocks are provided respectively with the selection switch decoding circuit and the selection switching circuits 13a, 5a-8a, and 13b and 5b-8b and the circuits 13a-, and the circuits 5a-8a- are controlled respectively by common lines 18, 19 and a common line 17 connected to word drive timing generator 16. Throgh the configuration above, a part brought into a high resistance due to crossed wirings is decreased, the wiring resistance is decreased and generation of electrical delay is prevented. As a result, the semiconductor storage device is operated in high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention particularly relates to a semiconductor memory device having a circuit configuration that allows high-speed access.

The demand for higher speed semiconductor memory devices is increasing, and in order to achieve this, efforts are being made to miniaturize elements, shorten wiring, and minimize the electrical delay time inside semiconductor devices. There is.

In order to minimize electrical delays in internal wiring, in addition to size reduction, it is necessary to reduce wiring resistance and conductivity. However, it is generally difficult to sufficiently reduce the electrical resistance of the wiring due to the load circuit, and it is no exaggeration to say that reducing the wiring resistance holds the key to increasing the speed of semiconductor memory devices.

FIG. 1 shows the components of a conventionally known semiconductor memory device, in which blocks 1 to 4 each have a decoding circuit arranged inside, 5 to 8 are selective switching circuits, and 9 to 12 are common blocks. 13 is a selection switch decoding circuit, 14 is an output from the selection switch decoding circuit, 15 is an input to the decoding circuit, and 16 is a word line drive timing generator. In Fig. 1, the shaded areas are the areas where wiring intersects in the semiconductor device.For example, if the common lines 9 to 12 are made of aluminum, the shaded areas are made of polysilicon, etc., which has a higher resistance than aluminum. be done.

In order to increase the speed of semiconductor devices, it is important to minimize the electrical delay in the path from common lines 9 to 12 to the decoder site in Figure 1, and therefore the resistance in the shaded area is a problem. is easily understood.

The present invention focuses on the wiring resistance of conventionally known semiconductor memory devices and provides a new circuit configuration for reducing this.

FIG. 2 shows the main parts of one embodiment of the present invention.
a ”-5d + 6 a ~ 6 d + 7 a
~7d+8a~8d are MOSs that are independently grouped for each block newly provided according to the present invention.
A number of selection switching circuits are made up of transistors, and 133 to 13d are selection switch decoding circuits independent for each block.

The outputs from the selection switch decoding circuit are 14a to 14.
d and is connected to the control terminal or gate of the selection switching circuit. Here, the shaded areas are locations where the wiring intersects and the resistance is partially reduced, as in FIG. 1. 15a to 15d in FIG. 2 are inputs to the selection switch decoding circuit, and 16 is the word ff.
Mi dynamic timing generators 17, 18, and 19 are common lines.

Selection switching circuits 5a-5d, 6a-5d.

One end of each of 7a to 7d and 8a to 8d is connected to a common line 17, and the other end is connected to a circuit inside a block consisting of a decoding circuit.

Comparing FIG. 1, which shows a conventionally known device, with FIG. 2, which shows an embodiment of the present invention, in FIG. Common line 171 selection switching circuit 5a-5
d, 5a to 6d, 78 to 7d, 8a to 8d, and it can be seen that there are no hatched areas along the decoding circuits. Therefore, it can be seen that according to the present invention, there is no high resistance portion in the current path, thereby causing no pulse delay.

Although there is a shaded area in FIG. 2 showing an embodiment of the present invention, this area is only provided with a selection control signal.
Almost no current flows, and the effect of resistance is negligible.

The present invention has been described above in comparison with conventionally known devices, and according to the present invention, a semiconductor memory device capable of high-speed operation can be obtained.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of a main part of a conventionally known semiconductor memory device, and FIG. 2 is an explanatory diagram of a main part of an embodiment of the present invention. 1 to 4... Blocks having decoder circuits, 5
~8, 5a-5d, 6a-6d, 7a-7d, 8a-8
d...Selection switching circuit, 9~12゜17
~19...Common line, 13.13a~13d...
...Selection switch decoding circuit, 14114a~1
4d... Output from the selection switch decoding circuit, 15° 15a to 15d, input to the selection switch decoding circuit, 16...°゛° word line drive timing generator. 5- Z diagram-559-

Claims (1)

[Claims] A decoding circuit divided into multiple blocks,
a plurality of selection switching circuits independently grouped for each block; a selection switch decoding circuit independent for each block; and means for connecting to each control terminal of the selection switching circuit; A semiconductor memory device, wherein one end of the selection switching circuit and each input of the selection switch decoding circuit are connected to a plurality of common lines that extend across the plurality of blocks.