KR100260550B1 - Data transfer method in semiconductor memory - Google Patents

Abstract

PURPOSE: A data transmission method in a semiconductor memory device is provided to improve the overall efficiency of the semiconductor memory device by preventing the mis-operation of each circuit in a semiconductor chip and suppressing noise generated during data transmission. CONSTITUTION: The semiconductor memory device consists of a data register, a cell array corresponding to the data register and a number of memory blocks which include transmission gate transistor transmitting data between the data register and the memory cell array. After a control stage of the transmission gate receives a data transmission control signal, it transmits the data transmission control signal to one memory block selected among the memory blocks at first, and then to another memory block after a fixed time delay sequentially.

Description

Improved Data Transfer Method in Semiconductor Memory Devices

1 is a diagram of a data transfer gate transistor control method according to the prior art.

2 is a diagram of a data transfer gate transistor control method according to the present invention;

3 is a diagram of a data transmission control signal generation according to the present invention.

4 shows a data transmission control signal generator according to the invention.

5 shows a delay element according to the invention.

6 is a waveform diagram of each signal according to the present invention, and

7 is a noise generation distribution diagram according to the prior art and the present invention.

The present invention relates to a data transfer method of a memory device of a semiconductor device, and more particularly, to a data transfer method between a data register and a memory cell array.

A semiconductor memory device comprising a plurality of memory cell arrays and corresponding data registers and transfer gate transistors connected between the data registers and the memory array cells to transfer data, wherein the data between the data registers and the memory cell array is provided. The transfer must be made quickly and stably, and the suppression of noise generated during data transfer to the maximum is an important requirement for improving the efficiency of the entire semiconductor memory device.

Techniques for data transfer in semiconductor memory devices are disclosed in detail in ISSCC Volume 26 (April 1991 Vol26, NO4, pages 555-448).

In the prior art, a method of controlling a data transfer gate transistor for switching data transfer between a data register and a memory cell array is the same for a data transfer gate transistor in each block consisting of a data register and a memory cell array and a data transfer gate transistor. By simultaneously applying control signals, data transfer between each data register and the memory cell array can be performed simultaneously. FIG. 1 shows, in the prior art, each memory block consisting of a data register, a memory cell array, and a data transfer gate transistor and the same data transfer pulses (DTP) that control the data transfer gate transistors in the memory block. It is shown.

In FIG. 1, when data transfer is performed between a data register in each memory block and a memory cell array, the same control signal DTP is simultaneously applied to each data transfer gate transistor, that is, memory block A, memory block B,... By simultaneously controlling the data transfer gate transistors in the memory block Z, data transfer between each data register and the memory cell array is simultaneously performed. However, the simultaneous transfer of data in all the memory blocks may cause noise to increase rapidly at the same time, adversely affecting the operation of each circuit in the semiconductor chip, causing malfunction of the circuit, and causing data in the memory device. There may be an error that may cause an error in the overall efficiency of the semiconductor memory device.

Accordingly, an object of the present invention is to provide an improved data transfer method that can minimize noise generated during data transfer and prevent malfunction of each circuit in the semiconductor chip, thereby improving the efficiency of the entire semiconductor memory device.

An object of the present invention is to provide a data transfer control signal applied to a data transfer gate transistor in each memory block including a data register, a memory cell array, and a data transfer gate transistor separately at predetermined time intervals, so as to be different from each other. This is achieved by distributing noise by allowing data transfer to occur at that point in time.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a semiconductor memory device including a plurality of memory blocks including a data register and a memory cell array and a transfer gate transistor connected between the data register and the memory cell array to transfer data. A control signal is sequentially applied to the data transfer gate transistor in the block. In FIG. 2, data transfer between the data register of each memory block and the memory cell array is performed by sequentially applying different control signals to each data transfer gate transistor, that is, memory block A, memory block B,... The data transfer control signals A _P , B _P , and P _P corresponding to the data transfer gate transistors in the memory block Z are applied at predetermined time intervals to sequentially perform data transfer between each data register and the memory cell array. . The data transmission control signals applied in the memory blocks at different points in time may be applied regardless of the arrangement order of the memory blocks. will be.

3 shows a block diagram of data transmission control signal generation in accordance with the present invention. That is, the data transfer signal A _P for controlling the data transfer gate transistor of the memory block A is generated through the predetermined data transfer control signal generator, and the data transfer signal A _P passes through the predetermined delay device and then the data transfer control signal generator Through the data transfer signal B _P for controlling the data transfer gate transistor of the memory block B is sequentially generated. Through this series of processes, the data transfer signal Z _P for controlling the memory block Z is generated, thereby completing the data transfer in each memory block.

4 is a diagram showing a data transmission control signal generator according to the present invention. 5 is a detailed view of the delay elements provided between the data transmission signal generators. In FIG. 4, the input signal IN _AP is input to an inverter chain consisting of a NOR gate and a plurality of inverters, respectively. When the input signal IN _AP of the logic “high” is input to the data transmission control signal generator, the data transmission control signal A _{P, which} is an output signal of the data transmission control signal generator, maintains a logic “low”. When the input signal IN _AP transitions to a logic "low", the data transfer control signal A _{P, which} is the output signal of the data transfer control generator, remains a logic "high." The data transfer control signal A _P of logic "high" conducts the data transfer gate transistor of the memory block A shown in FIG. On the other hand, the data transfer control signal A _P is input to the delay element shown in FIG. The delay element according to the present invention is composed of four inverters. It is well known that the delay time can be adjusted by the number of inverters, the resistance or the capacitor. When the data transmission control signal A _P is input to the delay element and the predetermined time elapses, the output signal IN _BP of the delay element is again input to the data transmission control signal generator shown in FIG. 4 to generate the data transmission control signal B _P.

6 shows data transfer control signals A _P , B _P ,... Applied to each memory block of FIG. And signals input to the data transmission control signal generator IN _AP , IN _AP . Is a waveform diagram for. The waveform diagram of FIG. 6 shows that data transfer data signals applied to data transfer gate transistors in each memory block are sequentially generated at predetermined time intervals.

7 briefly shows the noise peak value generated during data transmission in the present invention and the prior art. That is, the conventional technique shows that the noise peak is suddenly seen at the same time when transferring data between the data register and the memory cell array. However, in the present invention, unlike the conventional technique, the data transfer signal applied to the data transfer gate transistor is By sequentially applying a delay for a predetermined time interval, it is shown that the noise is distributed by changing the timing of data transfer of each memory block.

In the semiconductor memory device comprising a plurality of data registers and corresponding memory arrays according to the present invention as described above, a data transfer control signal of each memory block comprising a data register, a memory cell array, and a data transfer gate transistor. By separately applying, the data is transmitted at different time points rather than at the same time, thereby dispersing noise, thereby preventing malfunction of circuits in the semiconductor chip due to a sudden increase in noise, thereby improving efficiency of the entire semiconductor memory device.

Claims (7)

And a plurality of memory blocks including one data register, one cell array corresponding to the data register, and at least one transfer gate transistor connected between the data register and the cell array cell to transfer data. A data transfer method of a semiconductor memory device configured to apply a data transfer control signal to a control end of at least one transfer gate transistor, wherein the data transfer control is applied to a control end of each transfer gate transistor of each of the plurality of memory blocks. The signal is once applied to one of the selected memory blocks of the plurality of memory blocks and then delayed by a predetermined time interval to be applied to another memory block, which is sequentially applied to another memory block by a predetermined time interval. Presented to the data transfer method of a semiconductor memory device, it characterized in that the so applied. The semiconductor memory according to claim 1, wherein the predetermined time interval is a time interval until one memory block selected to be applied to the data transfer control signal is disabled, and then the next selected memory block is enabled. Method of data transmission on the device. The method of claim 2, wherein the predetermined time interval is generated by a predetermined delay means. The semiconductor memory device as claimed in claim 3, wherein the data transfer control signal applied to the control terminal of the data transfer gate transistor in the memory block is applied at different times regardless of the arrangement order of the memory blocks. Data transfer method. And a plurality of memory blocks including one data register, one cell array corresponding to the data register, and at least one transfer gate transistor connected between the data register and the cell array cell to transfer data. A semiconductor memory device configured to apply a data transfer control signal to a control terminal of at least one transfer gate transistor, characterized by further comprising a data transfer control signal generating means and a delay means for generating the data transfer control signal. Semiconductor memory device. 6. The semiconductor memory device according to claim 5, wherein said data transfer control signal generating means preferably comprises at least one inverter and a NOR gate. 6. The semiconductor memory device according to claim 5, wherein said delay means preferably comprises at least one inverter to delay the start of generation of said data transfer control signal.