KR940008285B1 - Data output driver having the least noise - Google Patents

Abstract

The output circuit which receives paired signal data from the output buffer to produce the driving output data comprises pull-up transistors receiving the first signal which is one of the paired signal; the first pull-down transistor receiving the second signal which is the other paired signal; the second pull-down transistor receiving the said second signal; delay components which reside between the first and the second pull-down transistors delaying the turn on time of the second pull-down transistor after the first pull-down transistor is activated.

Description

Minimal Noise Data Output Driver

1 is a conventional data output driver circuit diagram.

2 is an operation timing diagram of FIG.

3 is a circuit diagram showing an embodiment of a data output driver according to the present invention.

4 is an operation timing diagram of FIG.

5 is a layout diagram of FIG.

6 is a layout diagram of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data output driver in a semiconductor memory device, and more particularly, to a data output driver having minimum noise.

As semiconductor memory devices are increasingly integrated and operation speeds are increased, noise problems in chips are increasing. Among them, the noise induced from the pull-up and pull-down transistor stages of the data output driver is known to be quite large. The reason why the noise is generated in the data output driver is that the channel current flowing in the pull-up transistor stage and the pull-down transistor stage is from the "high" level of the supply voltage stage level to the "low" level of the ground voltage stage level, or "low" level. This is because the instantaneous change to the "high" level results in an impulsive peak current.

A conventional data output driver circuit is shown in FIG. 1 is composed of a data output buffer 90, a data output driver 100 ', and a data output pad 110'. In FIG. 1, CLK is an output clock of the data output buffer 90 'and the DO and Are respectively read data from the memory cell and its inversion data. The SI signal is generated from the data output buffer 90 'and is a control signal of a pull-down transistor of the data output driver 100'. The S2 signal is generated from the data output buffer 90 'and is a control signal of the data output driver 100' pull-down transistor. As shown, the data output driver 100 'has one (i = 1, 2, 3, ...) pull-up transistors in which one end of a channel is connected in parallel to a power supply voltage terminal and receives the S1 signal as a common gate voltage. j (j = 1,2,3…) pull-down transistors md1. md2, md3, ... mdj). Between the channel of the pull-up transistors mu1, mu2, mu3,. The second inductance L'2 lies between them. The output line 1 has a common connection between the other end of the channels of the pull-up transistors mu1, mu2, mu3, ... mui and the other end of the channels of the pull-down transistors md1, md2, md3, ... muj.

FIG. 2 shows an operation timing diagram of a conventional data output driver. (A) in FIG. 2 shows the case where the potential of the output line 1 of FIG. 1 is at the "low" level, and (B) shows the case where the potential of the output line 1 is at the "high" level. . And (C) is a diagram showing the generation of the S1 and S2 signals according to the input signal of the data output buffer 90 'and to help understand the value of Dout. In the above (C) it is noted that D.C is a don't care state and H-Z is a high impedance state. The operation of the conventional data output driver of FIG. 1 will be described with reference to FIG. Prior to the description, all of the first pull-up transistor mu1 constituting the pull-up transistor stage in FIG. 1 from the first pull-up transistor mu1 are directly connected to the S1 signal and simultaneously turned on or turned off by the S1 signal. It should be noted that it is "turned off". In addition, it should be noted that all of the first pull-down transistors md1 to j-th pull-down transistors mdj constituting the pull-down transistor stage are directly connected to the S2 signal, and are simultaneously turned "on" or "turned off" by the S2 signal. something to do. First, the case where the potential of the output line 1 is at the "low" level. It will be readily appreciated that the "high" signal is applied. On the other hand, those skilled in the art will readily understand that the output of the data is in a "high" impedance state when both the S1 and S2 signals are "low" signals. By means of the S1 and S2 signals, the transistors of the pull-up transistor stage are " turned off " and all transistors of the pull-down transistor stage are " turned on " simultaneously to bring the potential of the output line 1 to the ground voltage level. However, as shown in FIG. 2, all the transistors of the pull-down transistor stage are " turned on " at a time, so that a severe noise phenomenon occurs due to the generation of the peak current toward the ground voltage. This can be seen from V = L · di / dt (L: inductance connected to the ground voltage terminal). As the "turn-on" time of the pull-down transistor stage is shorter, the value of dt becomes smaller and the value of V becomes larger. . Next, the case where the potential of the output line 1 is at the "high" level will be described. The S1 signal is applied as a "high signal" and the S2 signal is applied as a "low" signal. Then, by the S1 and S2 signals, all transistors of the pull-down transistor stage are "turned off" and all transistors of the pull-up transistor stage are applied. Is simultaneously " turned on " to bring the potential of the output line 1 to a power supply voltage level, but as shown in FIG. 2 (b), by turning all transistors of the pull-up transistor stage "turned on" at a time. As a result, a severe noise phenomenon occurs due to the generation of peak current at the power supply voltage side, which is also known from V = L · di / dt (L: inductance connected to the power supply voltage terminal), which is referred to as “turn on” of the pull-up transistor stage. The shorter the time, the smaller the value of the dt and the larger the V value, the greater the noise, moreover, the larger the capacitor loading of the output line 1, the larger the output. Fed to line (1), or exiting the charge amount is further increased at a time is a phenomenon that occurs the more severe will result in bad phenomenon such that, as well as increasing power consumption of the chip causing the malfunction of the other circuits in the chip.

It is therefore an object of the present invention to provide a data output driver in which generation of noise is suppressed as much as possible.

In order to achieve the object of the present invention, the present invention provides a data output driver that operates by receiving a pair of signals buffered and output from a data output buffer and transmitting a corresponding signal to a data output pad through a predetermined output node. A first pull-up transistor having a gate inputted with a first signal of the pair of signals and a channel formed between a first power supply terminal and the output node, a gate input of the first signal, and the first power supply terminal and the A second pull-up transistor having a channel formed between the output node, a delay element connected between a gate of the first pull-up transistor and a gate of the second pull-up transistor, and a second signal of the pair of signals; At least a pull-down transistor which is input and has a channel formed between the second power supply terminal and the output node. Configuration is further characterized in that the first of the first pull-up transistor and second pull-up transistor in response to the activation input of the signal "turn-on" the operation data output driver comprising in sequence as the delay time of the delay elements.

The present invention also provides a data output driver which operates by receiving a pair of signals buffered and output from a data output buffer and transmitting a corresponding signal to a data output pad through an output node. A pull-up transistor having a gate input and a channel formed between the first power supply terminal and the output node, and a gate inputting a second signal of the pair of signals, and a channel being formed between the second power supply terminal and the output node A first pull-down transistor; a gate input of the second signal; a second pull-down transistor having a channel formed between the second power supply terminal and the output node; a gate of the first pull-down transistor and the second pull-down transistor; At least a delay element connected between the gate and the gate of the second signal; The said first pull-down transistor and the first "turn-on" operation of the second pull-down transistor makin done sequentially by the delay time of the delay elements is characterized in that the data output drivers.

Hereinafter, preferred embodiments of a data output driver according to the present invention will be described in detail with reference to the accompanying drawings.

3 is an example of the sealing of the data output driver according to the present invention, and FIG. 4 is an operation timing diagram according to the embodiment. As shown in FIG. 3, an optimum embodiment for realizing the idea of the present invention, a resistance element is implemented in both pull-up and pull-down stages as delay means. The configuration of FIG. 3 will be described. 3 shows resistance elements Ru, Ru2, Ru3, ... Rui as the delay means of the signal between the gates and the gates of the pull-up transistors adjacent to each other in the conventional data output driver, and each of the pull-down transistors adjacent to each other. The resistive elements Rd1, Rd2, Rd3, ... Rdj are provided as delay means for the control signal between the gate and the gate. Thus, for example, when the S1 signal is applied, the S1 signal is applied to the gate of the first pull-up transistor MU1 and applied to the gate of the second pull-up transistor MU2 after a predetermined delay time, and also has a predetermined time interval. 3, 4,... And gates of the i-th pull-up transistors MU3, MU4, ..., MUi. In addition, when the S2 signal is applied, the pull-down transistors MD1, MD2, ..., MDj undergo the above-described process by the resistance elements Rd1, Rd2, Rd3, ..., Rdj, and the " turn on: "

The operation of the data output driver of the present invention will be described with reference to FIG. Prior to the description, CLK, DO, DO, are the same as the signals applied to the conventional data output buffer, and the signals applied to the pull-up and pull-down transistor gates of the data output driver of the present invention are also generated in the same manner as the first diagram. It should be noted. In addition, the CLK signal must be generated as an enable signal to enable the data output driver 100. First, the case where the potential of the output line 10 is at the "low" level will be described. The S1 signal is applied "low" and the S2 signal is applied "high". All transistors of the pull-up transistor 100-A are " turned off " by the " low " level S1 signal. After the first pull-down transistor MD1 of the pull-down transistor stage 100-B is turned on by the S2 signal of the "high" level, the remaining pull-down transistors MD2, MD3, ..., MDj are spaced at a predetermined time interval. Are sequentially " turned on " to bring the potential of the output line 10 to a ground voltage level. As shown in FIG. 4 (a), since each transistor of the pull-down transistor stage 100-B is " turned on " sequentially, the generation of peak current toward the ground voltage stage is considerably reduced and the noise phenomenon accordingly Suppressed. This can be seen in V = L · di / dt (L: inductance connected to the ground voltage terminal), and as the “turn on” time of the pull-down transistor stage 100-B becomes longer, the value of dt becomes larger and the V The value becomes smaller. Next, the case where the potential of the output line 10 is at the "high" level will be described. The S1 signal is applied "high" and the S2 signal is applied "low". All transistors of the pull-down transistor stage 100-B are " turned off " by the " low " level S2 signal. After the first pull-up transistor MU1 of the pull-up transistor stage 100-A is turned on by the S1 signal having the "high" level, the remaining pull-up transistors MU2, MD3, ..., Mui are spaced at a predetermined time interval. Are sequentially " turned on " to bring the potential of the output line 10 to a power supply voltage level. As shown in FIG. 4 (b), since each transistor of the pull-up transistor 100-A is "turned on" sequentially, generation of peak current at the power supply voltage side is considerably reduced and noise phenomenon is suppressed accordingly. do. This can be seen in V = L · di / dt (L: inductance connected to the power supply voltage terminal), and as the “turn on” time of the pull-up transistor stage 100-A becomes longer, the value of dt becomes larger and the V The value becomes smaller. In addition, even when the capacitor loading of the output line 1, which has been a problem in the conventional circuit, is very large, the amount of charge supplied or exited to the output line 10 is sequentially supplied or exited, thereby suppressing generation of noise. It will be easy to understand.

The layout of the conventional data output driver of FIG. 1 and the layout of the data output driver according to the present invention are shown in FIG. 5 and FIG. 6 to help understand the realization of the data output driver according to the present invention. Each is shown.

The conventional data output driver of FIG. 5 is configured to simultaneously apply the S1 and S2 signals to a plurality of pull-up and pull-down transistors, respectively. In contrast, the data output driver according to the present invention of FIG. 6 is configured such that the S1 and S2 signals enter the gate inputs of the first pull-up and pull-down transistors.

The data output driver according to the present invention shown in FIG. 3 is one embodiment in which the spirit of the present invention is realized, and the resistance element used as the delay means can be replaced with another element that can be used as the delay means. In the present invention, the resistive element is used as polysilicon, but it should be noted that it can be replaced with another resistive element capable of producing the same effect as the polysilicon.

As described above, the data output driver according to the present invention can minimize the occurrence of noise at the power supply voltage terminal or the ground voltage terminal, thereby preventing chip malfunction, thereby improving reliability of the semiconductor memory device. In addition, there is an effect that can be easily realized in the existing semiconductor memory device.

Claims (7)

A data output driver which operates by receiving a pair of signals buffered and output from a data output buffer and transmitting a corresponding signal to a data output pad through a predetermined output node, wherein the first signal of the pair of signals is gate inputted. A first pull-up transistor in which a channel is formed between a first power terminal and the output node, and a second pull-up in which a channel is formed between the first power terminal and the output node by gate-input the first signal; A delay element connected between a transistor, a gate of the first pull-up transistor, and a gate of the second pull-up transistor, a second signal of the pair of signals is gated in between the second power supply terminal and the output node. At least a pull-down transistor each having a channel formed at the first pull-up transistor, the first pull-up responding to an activation input of the first signal; And a " turn on " operation of the transistor and the second pull-up transistor in sequence by the delay time of the delay element. The data output driver according to claim 1, wherein the delay element is made of polysilicon formed on an upper layer of the same chip. A data output driver which operates by receiving a pair of signals buffered and output from a data output buffer and transmitting a corresponding signal to a data output pad through a predetermined output node, wherein the first signal of the pair of signals is gated and A pull-up transistor in which a channel is formed between a first power supply terminal and the output node, and a first pull-down in which a channel is formed between the second power supply terminal and the output node by gate-input a second signal of the pair of signals; A second pull-down transistor having a transistor inputted through the second signal and having a channel formed between the second power supply terminal and the output node, a gate of the first pull-down transistor, a gate of the second pull-down transistor, At least each of the delay elements connected between the plurality of delay elements; First pull-down transistor and a second pull-down "turn-on" the operation data output driver, characterized in that constituted by any sequence as long as the delay time of the delay elements of the transistor. 4. The data output driver according to claim 3, wherein the delay element is made of polysilicon formed on an upper layer of the same chip. A data output driver which operates by receiving a pair of signals buffered and output from a data output buffer and transmitting a corresponding signal to a data output pad through a predetermined output node, wherein the first signal of the pair of signals is gate inputted. A first pull-up transistor in which a channel is formed between a first power terminal and the output node, and a second pull-up in which a channel is formed between the first power terminal and the output node by gate-input the first signal; A first delay element connected between a transistor, a gate of the first pull-up transistor, and a gate of the second pull-up transistor, a second signal of the pair of signals is gated, and a second power supply terminal and the output node A first pull-down transistor having a channel formed therebetween; and a gate input of the second signal, and a connection between the second power terminal and the output node. A second pull-down transistor having a channel formed thereon, and a second delay element connected between a gate of the first pull-down transistor and a gate of the second pull-down transistor, respectively, and activating the first signal. When the first pull-up transistor and the second pull-up transistor respond to the input, the turn-on operation is sequentially performed by the delay time of the first delay element, and the first pull-down responded to the activation of the second signal. And the " turn on " operation of the transistor and the second pull-down transistor are sequentially performed by the delay time of the second delay element. 6. The data output driver according to claim 5, wherein the first and second delay elements are each formed of a resistance element having a predetermined resistance component. 7. The data output driver according to claim 6, wherein each of the resistance elements is made of polysilicon formed on an upper layer of the chip.