KR0144487B1 - Variable delay circuit - Google Patents

Abstract

The variable delay circuit of the present invention can vary the delay time of a signal and can be used in a pulse generator circuit or the like to generate pulses of various widths, thereby improving the speed of the semiconductor device. To this end, at least three inverters connected in series between the input line and the output line and the control terminals connected to the input line and connected to the output terminals of at least two inverters close to the input terminal, respectively, and are inputted through respective control lines. At least two transfer transistors are provided for each jumping a signal on an input line according to the logic of the signal.

Description

Variable delay circuit

1 is a block diagram of a conventional delay circuit.

2 is a circuit diagram of a variable delay circuit according to an embodiment of the present invention.

3 is a waveform diagram of signals related to the circuit shown in FIG.

* Explanation of symbols for main parts of the drawings

Q1, Q2, Q3, Q4: Transfer transistor 10, 11: Input line

20, 40: Delay 21, 31: Control line

30, 70: output line 50: first control unit

60: second control unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable delay circuit, and more particularly, to a variable delay circuit configured to generate various delay times.

1 is a block diagram illustrating a conventional delay circuit. An input line 10 for inputting a signal from which an external delay is required and a delay for delaying a signal input through the input line 10 for a predetermined time. The unit 20 and an output line 30 for outputting the signal delayed by the delay unit 20 to the outside.

The delay unit 20 is a plurality of inverters are arranged in series, or composed of a MOS capacitor.

Accordingly, the signal delay time of the delay unit 20 is determined according to the signal transmission time of the inverter and the number of the inverters. In addition, when the MOS capacitor is a component, it will be determined according to the capacity of the capacitor.

However, there is a problem that the delay circuit cannot be used in an apparatus requiring various delay times.

For example, the delay circuit is included in the pulse generator of the memory compiler to generate only a pulse of a predetermined width.

However, the pulse generator designs the pulse width according to the memory having the largest size, thereby supplying a large width pulse to the memory having the smallest size, thereby lowering the overall operation speed.

Accordingly, an object of the present invention is to provide a variable delay circuit capable of generating various signal delay times.

In order to achieve the above object, a variable delay circuit according to an embodiment of the present invention includes a delay unit for delaying an input signal by being composed of an even number of inverters installed between an input line and an output line and connected in series with each other; A plurality of common connections and connected to different connection nodes of the even-numbered inverters to apply a signal from the input line to a corresponding connection node of the delay means according to a control signal from each control line to vary the delay time. A control means is provided.

Hereinafter, with reference to the drawings related to the present invention will be described in detail.

2 is a circuit diagram of a variable delay circuit according to an exemplary embodiment of the present invention, in which an input line 11 for inputting a signal requiring delay and an even number of inverters 12 to 17 connected in series with the input line 11 are shown. A delay time between the delay unit 40 and a delay unit 40 formed between the delay unit 40 and the input side of the first inverter 12 of the delay unit 40 and the output terminal N1 of the Nth inverter 13. A difference between the first control unit 50 and the first control unit 50 of the delay unit 40 and the output side N2 of the 2Nth inverter 15, which is different from the first control unit 50. In addition, the second control unit 60 for varying the delay time in the delay unit 40 is provided.

Here, referring to the inverters 12 to 17 constituting the delay unit 40, when the inverters 12 to 13, the inverters 14 to 15, and the inverters 16 to 17 are set to one group, respectively, The group consists of N (N is an even multiple) inverters.

The first controller 50 includes a transfer transistor comprising a PMOS transistor Q1 and an NMOS transistor Q2 for supplying a signal on the input line 11 to the node N1 in the delay unit 40, and a first transistor. An inverter 22 is provided between the control line 21 and the gate of the PMOS transistor Q1 to invert a control signal from the outside input through the first control line 21.

The second controller 60 includes a transfer transistor comprising a PMOS transistor Q3 and an NMOS transistor Q4 for supplying a signal on the input line 11 to the node N2 in the delay unit 40, and a second transistor. An inverter 32 is provided between the control line 31 and the gate of the PMOS transistor Q3 to invert a control signal from the outside input through the second control line 31.

Next, the operation of the variable delay circuit according to the embodiment of the present invention configured as described above will be described with reference to the timing of FIG.

First, as shown in FIG. 3A, the control signals from the first control line 21 and the second control line 31 are at the low (L; 0) level, and the signals from the input line 11 are In the case where the high H level is maintained for a predetermined time, the transfer transistors Q1 and Q2 in the first control unit 50 and the transfer transistors Q3 and Q4 in the second control unit 60 are turned off. The signal from the input line 11 is input to the first inverter 12 of the delay unit 40. Therefore, the output line 70 of the delay unit 40 outputs a delayed signal for a predetermined time (3a; delay time due to passing 3N inverters 12 to 17).

As shown in FIG. 3B, the control signal of the first control line 21 is high level for a predetermined time, the control signal from the second control line 31 is low level, and the input line 11 is used. In the case where the signal from the signal is maintained at the high level under the high level region of the control signal of the first control line 21, the transfer transistors Q1 and Q2 in the first control unit 50 are turned on and the second control unit 60 is turned on. Since the transfer transistors Q3 and Q4 in Fig. 2 are turned off, the signal from the input line 11 is input to the node N1 of the delay section 40 through the transfer transistors Q1 and Q2. Accordingly, the output line 70 of the delay unit 40 outputs a delayed signal for a predetermined time (a delay time due to passing 2a: 2N inverters 14 to 17).

Of course, when the signal from the input line 11 maintains a high level under the high level region of the control signal of the first control line 21, the signal in the delay unit 40 through the input line 11. The signal is also branched to the inverter 12 and input to some extent.

However, since the delay time through the inverter 12 and the later inverters is 3a, the transfer transistors Q1 and Q2 in the first control unit 50 at the time when a signal is transmitted to the node N1 through the inverter 13. Since the node N1 is already at the low level when the signal is turned on, the signal after the delay time 2a (the signal corresponding to 3a-2a = 1a) among the signals through the inverters 12 to 13 is the same. Flow into the first control unit 50. Therefore, the inverter 14 located at the rear end of the inverters 12 to 13 receives a signal that is not sufficient to perform the inversion operation, and no further inversion operation is performed. As shown in FIG. Only the signal waveform of the output line 70 is shown.

Meanwhile, as shown in FIG. 3C, the control signal of the second control line 31 is high level for a predetermined time, the control signal from the first control line 21 is low level, and the input line 11 is used. In the case where the signal from the second control line 31 maintains the high level under the high level region of the control signal of the second control line 31, the transfer transistors Q1 and Q2 in the first control unit 50 are turned off and the second control unit ( Since the transfer transistors Q3 and Q4 in the 60 are turned on, the signal from the input line 11 is input to the node N2 of the delay unit 40 through the transfer transistors Q3 and Q4. Accordingly, the output line 70 of the delay unit 40 outputs a delayed signal for a predetermined time 1a (delay time due to passing 1N inverters 16 to 17).

Of course, when the signal from the input line 11 maintains a high level under the high level region of the control signal of the second control line 31, the signal in the delay unit 40 through the input line 11. The signal is also branched to the inverter 12 and input to some extent.

However, since the delay time through the inverter 12 and the subsequent inverters is, for example, 3a, when the signal is transmitted to the node N2 through the inverter 15, the transfer transistor Q3, in the second control unit 60, Since the node N2 is already at the low level when Q4) is turned on, the signal after the delay time 1a (signal corresponding to 3a-1a = 2a) among the signals through the inverters 12 to 15 is Flow into the second control unit 60. Therefore, the inverter 16 located at the rear end of the inverters 12 to 15 is not supplied enough to perform the inversion operation, and no further inversion operation is performed. Thus, as shown in FIG. Only the signal waveform of the output line 70 is shown.

As described above, the variable delay circuit of the present invention can be included in a circuit such as a pulse generator to reduce power consumption due to various signal delay times, and is also advantageous in ASIC library design.

Claims (2)

Delay means for delaying an input signal, comprising an even number of inverters connected between the input line and the output line and connected in series, and connected to the input lines and connected to different connection nodes of the even number of inverters, respectively. And a plurality of control means for varying a delay time by applying a signal from the input line to a corresponding connection node of the delay means in accordance with a control signal from a line. The control circuit of claim 1, wherein the plurality of control means comprises: an inverter for inverting a control signal input through the respective control line, and a transfer transistor driven on / off according to an output of the inverter and a control signal on the control line. A variable delay circuit comprising: