KR100197560B1 - Pulse generating circuit of semiconductor memory device - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Pulse generating circuit of a semiconductor memory device.

2. The technical problem to be solved by the invention

The present invention provides a pulse generating circuit capable of adaptively adjusting a width of a pulse output when a power supply voltage provided to a semiconductor memory device is changed by various factors.

3. Summary of Solution to Invention

An improved pulse generation circuit of a semiconductor memory device includes a pulse generator for generating a pulse having a predetermined width in response to a transition of an input signal, and a detection control signal by detecting a change in a power supply voltage applied to the semiconductor memory device. And a pulse width adjusting section for outputting a voltage detector for outputting a pulse width adjusting section for outputting a pulse width in response to the detection control signal of the voltage detecting section.

4. Important uses of the invention

It is used as a pulse generating circuit of a semiconductor memory.

Description

Pulse generator circuit of semiconductor memory device

1 is a diagram illustrating a word line enable pass of a general semiconductor memory device.

2 is an operation timing diagram according to the pulse width delay according to FIG.

3 is a conventional pulse generation circuit diagram.

4 is a timing relationship diagram of output signals of each part according to FIG. 3;

5 is a block diagram of a pulse generating circuit of the present invention.

6 is a circuit diagram of an embodiment according to FIG.

7 is a timing relationship diagram of output signals of respective parts according to FIG. 5.

8 is a circuit diagram of another embodiment of the pulse width adjusting section used in the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse generating circuit of a semiconductor memory device, and more particularly to a pulse generating circuit of a semiconductor memory device capable of providing a pulse width that is adaptive to a change in applied power supply voltage.

In general, in a semiconductor memory device, particularly an asynchronous semiconductor memory, a pulse generating circuit detects a transition of an external address signal or a specific control signal to generate a pulse for holding or adjusting a signal for a longer time controlling a specific circuit inside the chip. It is being used to generate.

FIG. 1 is a diagram illustrating a word line enable path of a general semiconductor memory device. The pulse generation circuit employs the pulse generation circuit to further maintain a word line voltage of a memory cell for a predetermined time during recovery of a write. Referring to FIG. 1, the pulse generator 100 detects a transition of an input signal received on a line L1 or a line L2 and outputs an output pulse SPG having a predetermined width on the line L3 or a line L4. If the output pulse SPG having a constant width on the line L4 is output, the decoder 10 receives the output of the output pulse and the pre-decoder 8 and supplies an enable signal to the word line to further maintain the corresponding word line at a constant level. to provide. Therefore, the memory cell connected to the word line has an improved tWR margin. In FIG. 2, the operation timing diagram by the pulse width delay is shown in FIG. 1 as waveforms 2A-2K corresponding to the reference numerals of the respective parts in FIG. When the waveform 2I generated by the arrow symbol 1A of FIG. 2 is provided to the word line W / L-B of the memory cell B 12, it can be seen that the word line voltage of the memory cell is maintained for a predetermined time during the write recovery. The pulse generator 100 of FIG. 1 performing the function as described above typically has a circuit configuration as shown in FIG.

3 is a conventional pulse generating circuit diagram, which comprises a pulse generator 110 and a pulse expander 120. The pulse generator 110 receives the address signal or the write enable signal from the input terminal IN and outputs the first delay unit D11 and the output of the first delay unit D11 and the address signal or write enable signal to delay for a predetermined time. And a first NAND gate N1 output by NAND gating. The pulse extension unit 120 performs a NAND gating operation on the second delay unit D12, the second delay unit D12, the output of the second delay unit D12, and the output pulse SP to delay the output pulse SP of the pulse generator for a predetermined time. It consists of.

4 shows timing relationships of the output signals of the respective parts according to FIG. 3 as waveforms 4A-4C. Referring to FIG. 4, it can be seen that the waveform 4B is the output of the pulse generator 110, where the interval T2 is a first delay for receiving the address signal or the write enable signal from the input terminal IN and delaying the signal for a predetermined time. This is due to the delay width of D11. The waveform 4B has an inverted level unlike waveform 4A because the first delay unit is composed of odd delay elements I 1 -I 5. The waveform 4B is finally output as the waveform 4C by the pulse extension 120. Thus, the waveform 4C, which is a short pulse, is used for the unique purpose of the pulse generator 100 as described above. Similarly, the period T3 in the waveform 4C is a delay caused by the second delay unit. The pulse generation technique according to the circuit of FIG. 3 described above is disclosed in more detail in US Pat. No. 4,233,525.

On the other hand, when the power supply voltage provided to the semiconductor memory device changes due to various factors, it may be necessary to change the width of the pulse output from the pulse generation circuit having the above function. For example, due to the higher speed of operation in memory such as static RAM, the externally applied power supply voltage is lowered from 5 volts to 3.3 volts, while the pulse width needs to be longer to improve the tWR margin. There is. In addition, in some cases, the width of the pulse may be shorter. In addition, there is a need to provide a pulse width that is adaptive to variations in the power supply voltage when the power supply voltage fluctuates relatively small. For example, the pulse width may be shortened or lengthened when the power supply voltage is higher than the usual applied voltage, and the pulse width may be shortened or lengthened when the power supply voltage is lower than the usual applied voltage. However, the conventional technique as described above fixedly provides an output pulse such as waveform 4C of FIG. 4 at the designed power supply voltage, but only output pulses that are wider or smaller than the waveform 4C of FIG. 4 at increased power supply voltage. Will be able to provide. Therefore, there is a problem in that it is not possible to provide an output pulse suitable for various needs as described above.

This problem is often a cause of malfunction of the semiconductor memory device.

Accordingly, it is an object of the present invention to provide an improved pulse generating circuit which can solve the above-mentioned conventional problems.

Another object of the present invention is to provide a pulse generating circuit which can stably ensure the operation of a semiconductor memory by maintaining the word line voltage of the memory cell for a predetermined time even when the power supply voltage is changed. .

It is still another object of the present invention to provide a pulse generation circuit capable of adaptively adjusting the width of a pulse output when a power supply voltage provided to a semiconductor memory device is changed by various factors.

Another object of the present invention is to shorten or lengthen the pulse width when the power supply voltage applied to the memory is higher than the set voltage, and to shorten or lengthen the pulse width when the power supply voltage is lower than the set voltage. A mode suitable pulse generation circuit is provided.

A pulse generating circuit of the present invention for achieving the above objects includes a pulse generator for generating a pulse having a predetermined width in response to a transition of an input signal; A voltage detector which detects a change in a power supply voltage applied to the semiconductor memory device and outputs a detection control signal; And a pulse width adjusting unit configured to adjust and output a width of the pulse in response to the detection control signal of the voltage detecting unit. The pulse width adjusting unit may output the pulse width large or intact according to the logic level of the detection control signal, and output the pulse width small or intact according to the logic level of the detection control signal. It may be. The pulse generation circuit may apply the adjusted output pulse to the pre decoder of the semiconductor memory device or directly to the decoder.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, description of preferred embodiments according to the present invention will be described with reference to the accompanying drawings. It should be noted that the same reference numbers in the drawings represent the same elements or signals wherever possible.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention, such as the components and components of the pulse generating circuit. However, it will be apparent to one of ordinary skill in the art that the present invention may be practiced without these specific details by the present invention described above.

5 is a block diagram of a pulse generating circuit of the present invention, FIG. 6 is a circuit diagram of an embodiment according to FIG. 5, and FIG. 7 is a timing relationship diagram of each output signal according to FIG. 8 is a circuit diagram of another embodiment of the pulse width adjusting section used in the present invention.

The voltage detector 150 of FIG. 5 may be implemented with block 150 of FIG. 6 to detect a change in a power supply voltage applied to the semiconductor memory device and output a detection control signal. In FIG. 6, the voltage detector 150 outputs the detection control signal to a high level when the variation of the power supply voltage becomes equal to or higher than a predetermined reference voltage, and includes first, second, and third sources respectively connected to the power supply voltage. PMOS transistors 151, 152 and 156, first and second NMOS transistors 153 and 154 having drains connected to drains of the first and second PMOS transistors, and drains connected to a common source of the first and second NMOS transistors, and the source is grounded. And a third NMOS transistor 155 connected to the gate of the first NMOS transistor to receive the set reference voltage, and a source drain channel connected in series between the drain and the ground of the third PMOS transistor. And fifth and fifth PMOS transistors 157 and 158 each having a gate and a drain in common; A resistor 159 connected between the gate and the ground of the second NMOS transistor connected to the gate-drain connection point of the jistor, and an input terminal pain-connected to the drain of the first PMOS transistor and the gate of the third PMOS transistor; An inverter I10 and a second inverter I11 having an input connected to an output of the first inverter. Here, the voltage detector 150 may have a configuration other than the second inverter I11 in the above configuration in order to output the detection control signal to a high level when the variation of the power becomes less than or equal to the set reference voltage.

The pulse generator 100 in FIG. 5 may have the same circuit configuration as that in FIG. 3 described above, and is processed as a block portion in this embodiment.

The pulse width adjusting unit 160 of FIG. 5 may be implemented with circuit elements in block 160 of FIG. 6. 6, the pulse width adjusting unit 160 receives a delay unit 166 for delaying the pulse SPG output from the pulse generator 100 for a predetermined time, a switch 164 connected to the output of the delay unit, and a detection control signal VP. The switch delayed by the delay by having a switching signal generator 161,162 for generating a signal for switching the switch, and a NAND gate 165 for connecting the one end input to the output terminal of the switch and receiving the pulse as the other input When passing through, the width of the pulse is made as large as the delayed pulse, and when not passed, the received pulse is output as it is. Also, if the inverter 161 in FIG. 6 is removed for the opposite purpose, when the delayed pulse from the delay passes through the switch, the width of the pulse is made smaller by the width of the delayed pulse and the received pulse when not passed. Outputs as is.

Another embodiment of the pulse width adjustment unit 160 may be configured as shown in FIG. The configuration of FIG. 8 includes a delay unit 166 for delaying a pulse output from the pulse extension unit for a predetermined time, a switch 164 connected to the delay unit, and a signal for switching the switch by receiving the detection control signal. By having a switching signal generator 162 and a three-input NAND gate 165 connected to the output terminal of the switch with a first input, connected to an intermediate delay point of the delayer as a second input, and receiving the pulse as a third input. When the delayed pulse from the delay passes through the switch, the width of the pulse is made smaller by the sum of the widths of the respective delayed pulses, and when not passed, the width of the received pulse is made smaller by the width of the delayed pulse. In addition, for the reverse operation, when the delayed pulse from the delay passes through the switch, the width of the pulse is increased by the sum of the widths of the respective delayed pulses, and if not, the width of the received pulse is the delayed pulse. It can be as large as.

Figure 7 shows the characteristics of the operation of the pulse generating circuit of the present invention for easy understanding. For example, when the pulse generator 100 outputs a pulse SPG equal to the waveform 7C in response to a transition of the input signal as shown in the waveform 7A, the voltage detector 105 detects a change in the power supply voltage applied to the semiconductor memory device and the waveform. If the detection control signal VP such as 7B is output, the pulse width adjusting unit 160 outputs the output pulse SPGB similar to the waveform 7D when the pulse width is increased. The section L0 represents the pulse width adjusted by the pulse width adjusting unit 160 when the power supply voltage changes. On the other hand, if the voltage detector 150 detects a change in the power supply voltage applied to the semiconductor memory device and outputs a detection control signal VP such as waveform 7E, the pulse width adjuster 160 outputs the same waveform 7F when the pulse width is reduced. Output the pulse SPGB. The section S0 represents the pulse width adjusted by the pulse width adjusting unit 160 when the power supply voltage changes.

Therefore, according to the above-described pulse generation circuit, even when the power supply voltage varies, the word line voltage of the memory cell may be further maintained for a predetermined time during the recovery of the semiconductor memory device, thereby stably guaranteeing the operation of the semiconductor memory. In addition, there is an effect that the power supply voltage provided to the semiconductor memory device can adaptively adjust the width of the pulse outputted by various factors.

In addition, when the power supply voltage applied from the outside rises or falls, there is an advantage that the pulse width can be increased or decreased accordingly.

Claims (11)

A pulse generating circuit of a semiconductor memory device, comprising: a pulse generator for generating a pulse having a predetermined width in response to a transition of an input write enable signal, and detecting and detecting a change in a power supply voltage applied to the semiconductor memory device And a voltage detector for outputting a control signal, and a pulse width adjuster for adjusting the width of the pulse in response to the detection control signal and outputting the pulse width to the decoder. The NAND device of claim 6, wherein the pulse generator comprises: a first delay unit for delaying the write enable signal for a predetermined time; and a first NAND for NAND gating the output of the first delay unit and the write enable signal. The pulse generator comprising a gate; a second delay unit for delaying the output pulse of the pulse generation unit for a predetermined time; and a second NAND gate for NAND gating the output of the second delay unit and the output pulse. Pulse generation circuit, characterized in that consisting of a pulse extension. 8. The pulse generating circuit according to claim 7, wherein the first delay unit is a delay unit for inverting the logic of the signal when the write enable signal is delayed for a predetermined time. 9. The pulse generating circuit according to claim 8, wherein the second delay unit is a delay unit which outputs the output pulses of the pulse generator unit with the logic of the output pulses as they are during a delayed output for a predetermined time. The method of claim 7, wherein the voltage detector is configured to output the detection control signal to a high level when the variation of the power supply voltage becomes equal to or higher than a predetermined reference voltage. A third PMOS transistor, a first and a second NMOS transistors having drains connected to drains of the first, second and PMOS transistors, and a drain connected to a common source of the first and second NMOS transistors, and the source is grounded. A third NMOS transistor configured to receive the reference voltage set to be connected to the gate of the first NMOS transistor, and a source drain channel connected in series between the drain and the ground of the third PMOS transistor; Fourth and fifth PMOS transistors having a common gate and a drain connected to each other, and a gate-de of the fifth PMOS transistor; A resistor connected between the gate and the ground of the second NMOS transistor connected to an in connection point, a first inverter having an input terminal commonly connected to the drain of the first PMOS transistor and the gate of the third PMOS transistor, And a second inverter having an input connected to an output of the first inverter. The method of claim 7, wherein the voltage detector is further configured to output the detection control signal to a high level when the variation of the power supply voltage becomes lower than or equal to a predetermined reference voltage. And a drain connected to a common source of the third PMOS transistor, the first and second NMOS transistors having drains respectively connected to the drains of the first and second PMOS transistors, and the source connected to ground. A third NMOS transistor connected to the gate of the first NMOS transistor to receive the set reference voltage, and a source drain channel connected in series between the drain and the ground of the third PMOS transistor; Fourth and fifth PMOS transistors having a gate and a drain connected in common, and gate-drains of the fifth PMOS transistor A resistor connected between a gate of the second NMOS transistor connected to a connection point and a ground, and an input terminal having a first inverter connected to a drain of the first PMOS transistor and a gate of the third PMOS transistor; Pulse generator circuit. The apparatus of claim 10, wherein the pulse width adjusting unit comprises: a delay unit delaying a pulse output from the pulse expansion unit for a predetermined time, a switch connected to an output of the delay unit, and receiving the detection control signal to switch the switch. And a switching signal generator for generating a signal, and a NAND gate connected to an output terminal of the switch and receiving the pulse as an input of the other side, the width of the pulse being passed through the switch delayed from the delay unit. Pulse width of said delayed pulse and outputting said received pulse if it does not pass. 12. The apparatus of claim 11, wherein the pulse width adjusting unit is configured to delay a pulse output from the pulse extension unit for a predetermined time, a switch connected to an output of the delay unit, and the detection control signal to switch the switch. And a switching signal generator for generating a signal, and a NAND gate connected with an input of one end of the switch and receiving the pulse as an input of the other side, when a delayed pulse from the delay passes through the switch. And the width is made smaller by the width of the delayed pulse and the outputted pulse is output as it is. 12. The apparatus of claim 11, wherein the pulse width adjusting unit is configured to delay a pulse output from the pulse extension unit for a predetermined time, a switch connected to an output of the delay unit, and the detection control signal to switch the switch. And a switching signal generator for generating a signal, and a three input NAND gate connected to an output terminal of the switch, a first input connected to an intermediate delay point of the delay unit as a second input, and receiving the pulse as a third input. Configured to make the width of the pulse as small as the sum of the widths of the delayed pulses when the delayed pulse from the delay passes through the switch and to make the width of the received pulse smaller as the width of the delayed pulse when not passed. Pulse generation circuit characterized in that. 12. The apparatus of claim 11, wherein the pulse width adjusting unit is configured to delay a pulse output from the pulse extension unit for a predetermined time, a switch connected to an output of the delay unit, and the detection control signal to switch the switch. A switching signal generator for generating a signal and a three input NAND gate connected to an output terminal of the switch, a first input connected to an intermediate delay point of the delay unit as a second input, and receiving the pulse as a third input. And cause the width of the pulse to be as large as the delayed pulse when the delayed pulse from the delay passes through the switch. 16. The pulse generating circuit according to claim 15, wherein the output signal of the pulse generating circuit is used to further maintain the word line voltage of the memory cell for a predetermined time during the write recovery of the semiconductor memory device.