KR0179774B1 - Semiconductor memory enabling signal generating circuit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an activation signal generating circuit of a semiconductor memory. In the conventional circuit, a transition detection signal (ATD) is used in various situations such as a transition of an external address is mis-matched in time or a difference in an internal signal path. Is input with a temporal mis-match, in particular, when the mis-match is greater than the delay time of the delay unit 111, the clock pulse ATDSUM is a mis-matched detection signal among the transition detection signals ADT1 to ADTn. There is a problem of having a pulse width equal to the temporal sum of these. In order to solve this conventional problem, the present invention generates a clock pulse at an arbitrary width by the sum of the transition detection signals after a delay for an arbitrary set time, thereby making a mis-match of the transition detection signals at the transition of the input signal. In order to minimize the flow of the DC current by the present invention, the present invention provides a transition between the pull-up element and the pull-down element when the transition detection signal ATD is input with a temporal mis-match. The DC current can be minimized and a stable clock pulse can be generated by preventing a potential rise of the terminal NCOM due to the resistance ratio of the pull-up element and the pull-down element.

Description

Activation signal generation circuit of semiconductor memory

1 is a conventional circuit diagram.

2 is an operational waveform diagram of FIG.

3 is a circuit diagram of the present invention.

4 is a circuit diagram for general signal summation.

5 is an operational waveform diagram of FIG.

* Explanation of symbols for main parts of the drawings

201: clock generator 202: pulse width adjustment unit

203: Signal adder 211: Delay

ND1: NAND gate IN1 to IN4: Inverter

PM1, PM2: PMOS transistors NM1 to NMn: NMOS transistors

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and in particular, in a semiconductor memory that is activated asynchronously, transition detection signals (ATDs) generated when a transition of an external input signal are mis-matched in time to generate an activation signal. The present invention relates to an activation signal generating circuit of a semiconductor memory for minimizing a direct current (DC) current.

FIG. 1 is a conventional circuit diagram. As shown therein, the clock generation unit 101 which generates the clock pulse ATDSUM by the chip select signal CS and the transition detection signals ADT1 to ADTn are inputted. The pulse width adjusting unit 102 adjusts the width of the clock pulse ATDSUM of the clock generating unit 101.

The clock generation unit 101 sequentially inverters IN1 to IN3 for sequentially inverting the chip select signal CS and outputting them as clock pulses ATDSUM, and a delayer for delaying the output of the inverter IN2 by a predetermined time ( 111, an inverter IN4 for inverting the output of the retarder 111, a NAND gate ND1 for inverting the output of the inverter IN4 when the chip select signal CS is enabled, and The PMOS transistor PM1 pulls up the output terminal of the inverter IN2 by the output of the NAND gate ND1.

The inverter IN2 is composed of weak PMOS logic.

The pulse width adjusting unit 102 is configured by applying the transition detection signals ADT1 to ADTn to the gates of the NMOS transistors NM1 to NMn connected in parallel between the output terminal of the inverter IN2 and the ground, respectively.

The conventional circuit of such a configuration is to generate a clock pulse ATDSUM having an arbitrary pulse width by logically adding a transition detection signal ATD generated when the external input signal transitions.

In particular, even when the transition detection signal ATD is input in the form of a short pulse, a clock pulse ATDSUM having a predetermined pulse width is generated.

Referring to the operation of the conventional circuit as follows.

First, when the chip select signal CS is 0 and is in a disabled state, the clock generator 101 always turns off the PMOS transistor PM1 because the output NG1 of the NAND gate ND1 is always at a high level. State is maintained.

At this time, since the chip select signal CS which is 0 is inverted through the inverters IN1 and IN2 sequentially, the potential of the terminal NCOM is kept low.

Accordingly, the potential of the output terminal NCOM of the inverter IN2 is kept low, so that the clock pulse ATDSUM, which is the output of the inverter IN3, is kept high.

After that, when the chip select signal CS is enabled as 1, the terminal NCOM is maintained at the high state by the inverter IN2 configured of the weak PMOS when no address transition occurs.

At this time, since the high signal of the inverter IN2 is delayed by the delay unit 111 and then inverted through the inverter IN4 to become a low signal, the output NG1 of the NAND gate ND1 is kept high. The MOS transistor PM1 maintains a turn off state.

Accordingly, since the output NCOM of the inverter IN2 maintains a high state, the clock pulse ATDSUM of the inverter IN3 maintains a low state.

Subsequently, when one or more of the transition detection signals ATD1 to ATDn becomes high due to the address transition when the chip select signal CS is enabled to 1, the NMOS transistors NM1 to NMn of the pulse width adjusting unit 102 become high. The transistor is turned on to pull down the output terminal NCOM of the inverter IN2 of the clock generator 101.

At this time, since the inverter IN2 has a very large resistance value compared to the NMOS transistors NM1 to NMn, the inverter IN2 does not affect the state change of the output terminal NCOM, so that the potential of the output terminal NCOM is at a low level. It is a transition.

After that, when the transition detection signals ADT1 to ADTn are turned low, the NMOS transistors NM1 to NMn are turned off, and the level of the output terminal NCOM of the inverter IN2 is almost floating, thereby lowering the low level. Will be maintained.

At this time, since the low signal NCOM of the inverter IN2 is delayed by the delay time through the delay unit 111 and inverted to a high signal at the inverter IN4, the output signal NG1 of the NAND gate ND1 becomes low and is avoided. The MOS transistor PM1 is turned on so that the output terminal NCOM of the inverter IN2 transitions to a high level as a ratio.

Accordingly, the clock pulse ATDSUM becomes low because the high signal NCOM of the inverter IN2 is inverted in the inverter IN3, and the width of the clock pulse ATDSUM is equal to the delay time of the delay unit 111. Done.

However, in the conventional circuit, when the transition detection signal ATD is input with a temporal mis-match in various situations such as a transition of an external address is mis-matched in time or a difference in an internal signal path. In particular, when the mismatch is greater than the delay time of the delay unit 111, the clock pulse ATDSUM has a pulse width equal to the temporal sum of the mismatched detection signals among the transition detection signals ADT1 to ATDn. There is a problem that the flow of current increases.

That is, when the output terminal NCOM of the inverter IN2 goes low after the transition detection signal ADT1 goes high in the waveform diagram of FIG. 2, the output terminal NCOM of the NAND gate ND1 goes low. The time until the same as the delay time of the delay unit 111.

Accordingly, when the transition detection signal ADTn maintains the high state, both the PMOS transistor PM1 and the NMOS transistor NMn are turned on so that the potential value of the output terminal NCOM of the inverter IN2 is changed to the PMOS transistor. It has a random value due to the resistance ratio between the PM1 and the NMOS transistor NMn, and the direct current (DC) current flowing through the PMOS transistor PM1 and the NMOS transistor NMn is a retarder 111. Because of the delay time, the amount of DC current increases.

In order to solve the conventional problem, the present invention generates a clock pulse at an arbitrary width by adding a transition detection signal after being delayed for an arbitrary set time, thereby making a mis-match of the transition detection signal at the transition of the input signal. It is an object of the present invention to provide a circuit for generating an activation signal of a semiconductor memory, which is designed to minimize the flow of direct current.

3 is a circuit diagram according to an embodiment of the present invention. As shown therein, a signal adder 203, a chip select signal CS, and an output signal of the signal adder 203 which logically sum the transition detection signals ADT1 to ADTn. A clock generator 201 for generating a clock pulse ATDSUM by NG2, and a width of the clock pulse ATDSUM of the clock generator 201 by the transition detection signals ADT1 to ATDn. The pulse width adjusting section 202 is configured.

The clock generator 201 sequentially inverts the chip select signal CS to generate clock pulses ATDSUM, from IN1 to IN3, and a delay for delaying the output of the inverter IN1 by a predetermined time ( 211), an inverter IN4 for inverting the output of the delay unit 211, and a NAND gate ND1 for outputting an output signal of the inverter IN4 when the chip select signal CS is enabled as 1; When the output signal NG1 of the NAND gate ND1 and the output signal NG2 of the signal summing unit 203 are all 1, the voltage Vcc is pulled up to pull up the output terminal NCOM of the inverter IN2. It consists of the PMOS transistor PM1 (PM2) connected in series.

The pulse width adjusting unit 202 is configured by connecting the transition detection signals ADT1 to ADTn to the gates of the NMOS transistors NM1 to NMn connected in parallel between the terminal NCOM of the clock generator 201 and the ground. do.

The signal summing unit 203 is configured as shown in FIG. 4, and the tree-shaped or wired orifice of the address transition detection signal generating circuit is generally present for each input buffer in the semiconductor memory. It is a means used for the operation of logically adding the output (ATD).

As an example of the tree-type orifice, as shown in FIG. 4 (a), the transition detection signals ATD1 to ADTn are connected to the input terminals of (n / 2) noah gates, respectively. The N / 2 gate output signals are logically combined in one NAND gate.

In addition, as shown in FIG. 4 (b), the wired oragate, which is another example of the above, has a transition detection signal ADT1 connected between the source and the drain of the PMOS transistor having the gate grounded. NATMOS connected to the gates are connected in series, and the common connection point potential of the PMOS transistor and the n NMOS transistors is inverted in the inverter to output the inverted signal NG2. .

Referring to the operation and effect of the present invention configured in this way in detail as follows.

First, when the chip select signal CS is 0 and is in a disabled state, the clock generator 101 always turns off the PMOS transistor PM1 because the output NG1 of the NAND gate ND1 is always at a high level. State is maintained.

At this time, since the chip select signal CS which is 0 is inverted through the inverters IN1 and IN2 sequentially, the potential of the terminal NCOM is kept low.

Accordingly, since the output terminal NCOM of the inverter IN2 maintains the low level state, the clock pulse ATDSUM, which is the output of the inverter IN3, maintains the high state.

Subsequently, when the chip select signal CS is enabled as 1, if there is no transition of the address, the terminal NCOM is kept high by the inverter IN2 configured of the weak PMOS, and the inverter IN2 ) Is delayed by the retarder 111 for a predetermined time and then is inverted through the inverter IN4 to become a low signal. Therefore, the output NG1 of the NAND gate ND1 is kept high, thereby the PMOS transistor PM1. Will remain turned off.

At this time, the transition detection signals ADT1 to ADTn are in a low state, and since the signal NG2 logically combined by the signal adding unit 203 is in a low state, the PMOS transistor PM2 is maintained in the on state.

Accordingly, since the high signal NCOM of the inverter IN2 is inverted in the inverter IN3, the clock pulse ATDSUM is kept low.

Subsequently, when one or more of the transition detection signals ATD1 to ATDn becomes high due to the transition of the address when the chip select signal CS is enabled to 1, the NMOS transistors NM1 to 1 of the pulse width adjusting unit 102. The transistor of NMn is turned on so that the clock generator 101 pulls down the output terminal NCOM of the inverter IN2.

At this time, since the inverter IN2 has a very large resistance value compared to the NMOS transistors NM1 to NMn, the inverter IN2 does not affect the state change of the output terminal NCOM, so the potential of the output terminal NCOM is at a low level. It is a transition.

When at least one of the transition detection signals ADT1 to ADTn becomes high, the signal summing unit 203 outputs a high signal NG2 by performing a logical combination so that the PMOS transistor PM2 of the clock generator 201 is generated. ) Is turned off.

After that, when the transition detection signals ADT1 to ADNn are turned low, the NMOS transistors NM1 to NMn are turned off, and the output NG2 of the signal summing unit 203 is turned low again, so that the PMOS transistor PM2 is turned off. Is turned off, but since the NMOS transistor PM1 is turned off, the level of the output terminal NCOM of the inverter IN2 is almost floating to maintain a low level.

At this time, since the low signal NCOM of the inverter IN2 is delayed by the delay time through the delay unit 111 and inverted to a high signal at the inverter IN4, the output signal NG1 of the NAND gate ND1 becomes low and is avoided. The MOS transistor PM1 is turned on so that the output terminal NCOM of the inverter IN2 transitions to a high level.

Accordingly, the clock pulse ATDSUM becomes low because the high signal NCOM of the inverter IN2 is inverted in the inverter IN3, and the width of the clock pulse ATDSUM is equal to the delay time of the delay unit 111. Done.

When the skew of the transition detection signal ADT is input, the operation waveform is as shown in FIG.

That is, when the transition detection signal ATDn is in a high state, the output signal NG1 of the NAND gate ND1 transitions low after the delay time of the delay unit 211 passes, thereby turning on the PMOS transistor PM1. Since the output NG2 of the signal summing unit 203 is maintained at a high state, the PMOS transistor PM2 is maintained at a turned off state.

Thereafter, when all the transition detection signals ADT are in the low state, the output signal NG2 of the signal summing unit 203 is in the low state, thereby turning on the PMOS transistor PM2, so that the output terminal NCOM of the inverter IN2 is turned on. Will pull up.

Therefore, the DC current path between the PMOS transistors PM1 and PM2 as the pull-up element and the NMOS transistors NM1 to NMn as the pull-down element does not occur even during the skew input of the transition detection signal ADT.

This invention devises a relatively large direct current when the skew of the transition detection signal ADT is greater than the delay time of the delay unit 211. The PMOS transistors PM1 and PM2 connected in series are pull-up devices. Phosphorus flows through the NMOS transistors NM1 to NMn.

In particular, when the high speed operation is required, the present invention increases the current driving capability of the pull-up device and the pull-down device by increasing the amount of DC current.

As described in detail above, the present invention relates to a pull-up element and a pull-down when a transition detection signal ATD is input with a temporal mis-match for various reasons, in particular, when the mis-match is larger than a delay time. The DC current generated between the devices can be minimized, and a stable clock pulse can be generated by preventing a potential rise of the terminal NCOM due to the resistance ratio of the pull-up device and the pull-down device.

Claims (2)

In a semiconductor memory in which a memory cell is selected by selecting an arbitrary word line and an arbitrary bit line by an address combination, a signal summing unit 203 for logically adding the transition detection signals ADT1 to ADTn and a chip select signal ( A clock generator 201 for generating a clock pulse ATDSUM by the CS and the output signal NG2 of the signal summing unit 203, and the clock generator (2) by the transition detection signals ADT1 to ADTn. And a pulse width adjusting unit 202 for adjusting the width of the clock pulse ATDSUM of 201. 2. The inverter of claim 1, wherein the clock generator 201 sequentially inverts the chip select signal CS to generate a clock pulse ATDSUM, and the output of the inverter IN1 for a predetermined time. A delaying delay 211, an inverter IN4 for inverting the output of the delaying 211, and an output signal of the inverter IN4 when the chip select signal CS is enabled as 1; When the NAND gate ND1, the output signal NG1 of the NAND gate ND1 is 0, the PMOS transistor PM1 which is turned on to output the voltage Vcc, and the output signal of the signal summing unit 203 ( And a MOS transistor (PM2) for outputting the output voltage of the PMOS transistor (PM1) to the output terminal (NCOM) of the inverter (IN2) when NG2 is zero.