KR100596852B1 - Internal clock signal generator - Google Patents

Abstract

The present invention relates to an internal clock signal generator used to generate an internal master clock signal in a synchronous memory device operating in synchronization with an external input clock signal. In particular, a pad for measuring a pulse width of an internal master clock signal, and a pulse width control device are used. By providing a fuse in the delay means for measuring the pulse width of the master clock signal to the DC level through the pad, and then the pulse width adjustment by the fuse-option method on the premise of the measured value is made easier and faster The present invention relates to an internal clock signal generator that enables generation of an internal clock signal at a speed.

Description

Internal clock signal generator

1 is a block diagram of a pulse generator used for generating an internal clock signal in a conventional synchronous memory device.

2 is an operation timing diagram of the pulse generator shown in FIG.

3 is a circuit diagram illustrating an embodiment of the delay unit illustrated in FIG. 1.

4 is a block diagram of an internal clock signal generator according to the present invention;

5 is a circuit diagram showing an embodiment of the pulse width measuring means shown in FIG.

6 is a DC level waveform diagram of an internal master clock measured in the pad shown in FIG.

FIG. 7 is a circuit diagram illustrating an embodiment of the delay unit illustrated in FIG. 4.

<Description of Symbols for Major Parts of Drawings>

10: pad 100, 150: delay means

200: pulse generating means 300: pulse width measuring means

f1, f2: fuse

The present invention relates to an internal clock signal generator used to generate an internal master clock signal in a synchronous memory device that operates in synchronization with an external input clock signal. More specifically, the pulse width of the master clock signal is controlled through a pad. The present invention relates to an internal clock signal generator that makes it possible to generate a clock signal at an easier and faster speed by performing pulse width adjustment by a fuse-option method after measuring at a level.

In general, in the case of the synchronous DRAM operating in synchronization with the external input clock signal ext_CLK, in the operation of generating an internal command signal, all control signals based on the internal master clock signal generated by the external clock signal ext_CLK are generated. The timing is adjusted. Therefore, the pulse width of the internal master clock signal becomes a reference for all control signal pulse widths.

FIG. 1 is a block diagram of a pulse generator used to generate an internal clock signal in a conventional synchronous memory device, and is delayed by a time corresponding to a required pulse width by receiving an external input clock signal ext_CLK. Delay means 100 for performing the operation, the signal CLK_D delayed for a predetermined time through the delay means 100 and the external input clock signal ext_CLK are received by a combination of these two signals CLK_D and ext_CLK. And a pulse generating means (200) for generating an internal clock signal (CLKp) having a pulse width corresponding to the delay time made by the delay means (100).

In the case of the figure, the pulse generating means 200 comprises a NAND gate NAND1 and an inverter IV1 connected in series with each other in order to combine and combine the two signals CLK_D and ext_CLK.

This configuration generates an internal clock signal CLKp having a constant pulse width of the waveform as shown in FIG.

However, in the conventional clock signal generator according to the related art, a method of directly searching for and measuring a metal signal line in a memory chip has been used to measure a pulse width of a master clock signal. Because of the need for a separate instrument that can be measured, there is a problem of inefficient efficiency and cost.

FIG. 3 is a circuit diagram illustrating an embodiment of the delay means 100 shown in FIG. 1. The mutual serial series of receiving an external input clock signal ext_CLK and adding a predetermined delay to each inverter connected to the next stage is connected to each other. A plurality of connected inverters (in the figure, simply implemented by three inverters IV1, IV2, IV3), and a plurality of resistors R1, R2 connected in series between any two inverters IV1, IV2; And a plurality of MOS capacitors (in the drawing, simply implemented with three capacitors C1, C2, and C3) connected in parallel between the output terminal and the ground terminal of the resistor R2.

The resistors R1 and R2 and the MOS capacitors C1, C2 and C3 are each connected with a metal-option structure, and the delay amount is adjusted by the selective connection of these elements to adjust the pulse width of the internal clock signal.

As described above, the resistances R1 and R2 and the MOS capacitors C1, C2 and C3 in the delay stage 100 provided for adjusting the pulse width of the internal clock signal are connected with a metal-option structure. In order to adjust the pulse width of the master clock signal, the metal 2 line serving as the uppermost layer in the process is used as an option, and the pulse width adjustment operation is possible only by attaching and detaching the metal 2 option. There is a problem that this is not easy and there are various restrictions.

The present invention has been made to solve the above problems, and an object of the present invention is to measure the pulse width of the internal master clock signal at a DC level through a pad and to adjust the pulse width using a fuse-option method according to the measured value. An object of the present invention is to provide an internal clock signal generator capable of generating an internal clock signal more easily at a higher speed.

In order to achieve the above object, the internal clock signal generation apparatus according to the present invention receives the internal clock signal pulse width measuring means for measuring the pulse width of the internal clock signal to the DC level through the pad; Delay means for receiving an external input clock signal and performing a delay corresponding to a required pulse width by adjusting a delay amount by a fuse-option method according to a measured value of the pulse width measuring means; And a pulse generating means for receiving a delayed signal and an external input clock signal through a delay means and generating an internal clock signal having a pulse width corresponding to the delay time made by the delay means by a logical combination of these two signals. Characterized in that.

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The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram of an internal clock signal generator according to an embodiment of the present invention, in which a pulse is required by controlling an amount of delay by a fuse-option method by receiving an external input clock signal ext_CLK. Delay means for performing a delay corresponding to the width 150, and the signal CLK_D and the external input clock signal (ext_CLK) delayed for a predetermined time through the delay means 150 receives these two signals (CLK_D, ext_CLK) Receiving a pulse generating means 200 and an internal clock signal CLKp for generating an internal clock signal CLKp having a pulse width corresponding to a delay time made by the delay means 150 by a logical combination of And a pulse width measuring means 300 for measuring the pulse width of the internal clock signal CLKp at a DC level through a pad PAD 10.

FIG. 5 is a circuit diagram illustrating an exemplary embodiment of the pulse width measuring means 300 shown in FIG. 4. The inverter IV1 receives the internal clock signal CLKp and inverts the same. The resistor R1 is connected, the capacitor C1 is connected between the output terminal and the ground terminal of the resistor R1, and the pad 10 is connected to the output terminal of the resistor R1.

By the above configuration, when the internal master clock signal is driven with the resistor R1 and the capacitor C1 having a relatively large driving capability through the inverter IV1 having a relatively small size, the measured DC level is averaged. It has a voltage value.

FIG. 6 shows a DC level waveform diagram of an internal master clock measured by the pad shown in FIG. 5. As can be seen from the figure, for example, the internal master clock signal of the internal master clock signal on a 100MHz operating memory chip is shown. If the logic high 'pulse width has a value of 5 ns, the' logic high 'and' logic low 'areas have the same value in time, and the average voltage value at this time is Vint / 2, which is half of the internal power supply voltage (Vint). Becomes

Therefore, when the internal power supply voltage Vint is about 2.5V, the DC level value of the internal clock signal measured through the pad PAD 10 becomes 2.5 / 2V (= 1.25V) on average.

As described above, as the pulse width of the internal master clock signal can be measured at the DC level through the input / output pad 10, the ratio of the time can be easily known, and the pulse width can be calculated accordingly.

FIG. 7 is a circuit diagram illustrating an exemplary embodiment of the delay unit shown in FIG. 4. The external unit receives the external input clock signal ext_CLK and adds a predetermined delay to each of the delay units connected to the next stage. A plurality of inverters connected in series (simply shown as three inverters IV1, IV2, IV3 in the figure) and a plurality of resistors (in the figure) interconnected in series between any two inverters IV1, IV2. In the figure, a plurality of MOS capacitors (in the same figure) are connected in parallel between an output terminal and a ground terminal of a resistor R2 connected to the last of the plurality of resistors R1 and R2. And three capacitors (C1, C2, C3), and the plurality of resistors (R1, R2) and MOS capacitors (C1, C2, C3) are connected in parallel between the respective connection nodes. These fuses are further provided with respective fuses f1 and f2. The connection is selectively controlled according to whether or not blowing is performed.

The delay means 150 having the above configuration uses the DC level value measured through the pulse width measuring means 300 to increase the pulse width when the fuse f1 connected to the resistor is disconnected to increase the pulse width. On the other hand, in order to reduce the pulse width by cutting the fuse (f2) connected to the MOS capacitor it is possible to reduce the pulse width.

By selectively connecting the resistor and the MOS capacitor connected to each fuse by the fuse blowing method, it is possible to control the pulse width by adjusting the amount of delay accordingly, and this method is much more than the conventional method of attaching and detaching metal lines. This makes it simpler to significantly reduce the time and cost required to adjust the spread width.

As described above, according to the internal clock signal generator according to the present invention, the pulse width of the internal master clock signal can be measured at a DC level through a pad, so that the measurement cost and measurement required for the pulse width measurement of the internal clock signal are measured. It is very effective and can save you a lot of time.

In addition, it is possible to adjust the amount of delay using the fuse-option method of the fuse in the delay means by using the DC level measurement value measured through the pad, thereby making it possible to easily adjust the pulse width of the internal clock signal. There is.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the scope of the claims You will have to look.

Claims (3)

Pulse width measuring means for receiving an internal clock signal and measuring a pulse width of the internal clock signal at a DC level through a pad; Delay means for receiving an external input clock signal and adjusting a delay amount in a fuse-option manner according to the measured value of the pulse width measuring means to perform a delay corresponding to a required pulse width; And Pulse generation for receiving the delayed signal and the external input clock signal through the delay means and generating the internal clock signal having a pulse width corresponding to the delay time made by the delay means by a logical combination of these two signals. Way Internal clock signal generator comprising a. The method of claim 1, The delay means includes a plurality of inverters connected in series with each other to receive the external input clock signal and add a predetermined delay to each of the inverters connected to the next stage; Multiple resistors connected in series between any two inverters, A plurality of MOS capacitors connected in parallel between an output terminal and a ground terminal of the resistor connected to the last of the plurality of resistors; And the resistor and the MOS capacitor are each selectively connected to a fuse. The method of claim 1, The pulse width measuring means includes an inverter for receiving the internal clock signal and inverting it; A resistor connected to the inverter output terminal; A capacitor connected between the output terminal and the ground terminal of the resistor; And a pad connected to the output terminal of the resistor.

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