KR100457331B1 - Pulse generation circuit - Google Patents

Abstract

The present invention relates to a semiconductor device, and more particularly, to a pulse generating circuit, comprising: transfer means for receiving a clock signal from an external device and transmitting the clock signal; First inverting means for receiving the transferred clock signal and inverting the transferred clock signal; First delay means for receiving a pulse signal generated from said first inverting means and delaying it; Second delay means for receiving a delayed signal from said first delay means and delaying it; Combining means for receiving a signal generated from the first delay means and the second delay means and combining the signals generated from the first delay means; Second inverting means for inverting and outputting a combined signal generated from the combining means; And output means for receiving the inverted signals generated from the first inverting means and the second inverting means and outputting a pulse signal. The pulse signal from the output means has the same width as the high period of the clock signal applied from the outside. Such a pulse generating circuit can obtain a more stable pulse signal.

Description

Pulse generation circuit.

The present invention relates to a semiconductor device, and more particularly to a pulse generating circuit.

The semiconductor device operates by receiving pulse signals pulsed in synchronization with the external clock signal CLK. In this case, the sum of the rising period tCH and the falling period tCL of the clock signal corresponds to a cycle time of the clock, and the width of the pulse signal is determined by the length of the cycle. Until the pulse signal is output, the delay of the signal affects the operation of the memory chip.

1 is a circuit diagram showing the configuration of a pulse generating circuit according to a conventional embodiment.

Referring to FIG. 1, the pulse generating circuit outputs a pulse signal having a predetermined width in synchronization with a clock signal CLK applied from the outside. The pulse generating circuit is composed of a transmission circuit 10, a first inversion circuit 20, a delay circuit 30, a combination circuit 40, a second inversion circuit 50, and an output circuit 60. . The transfer circuit 10 receives an external clock signal CLK and transfers it, and the first inversion circuit 20 receives a signal transferred from the transfer circuit 10 and inverts it and outputs it to the first node. do. Subsequently, the signal of the first node is applied to the delay circuit 30 to output a delay signal delayed by a predetermined time to the second node. The delay signal of the first node is transmitted to the nand gate 15 of the combination circuit 40 in which one input terminal is fixed at the VCC level. The NAND gate 15 combines the applied signals and transfers an output signal to the second inversion circuit 50. The second inversion circuit 50 inverts the signal and outputs the signal to the third node. The output circuit 60 receives the signals of the first node and the third node and outputs a pulse signal PULSE having a width corresponding to a rising period of the clock signal.

2A is an output waveform diagram of nodes according to the pulse generation operation of FIG. 1, and FIG. 2B is an output waveform diagram of another case according to the pulse generation operation of FIG. 1.

When the clock signal CLK generated at a predetermined period passes through the transfer circuit 10 and passes through the first inverting circuit 20, a signal having the same width as the clock signal CLK but having a predetermined time delay is transmitted to the first node. It can be seen that. The delay circuit 30 receives the signal of the first node and delays it for a predetermined time to transfer the signal to the second node. When the second node is applied to the NAND gate 15 of the combination circuit 40, the NAND gate 15 is connected to the input terminal and the high voltage of the VCC level applied to the one input terminal. Output the combined signal. The signal generated from the NAND gate 15 is transmitted to the third node through the second inversion circuit 50, and the inversion signal of the first node is transmitted to the output circuit 60 to have a pulse signal having a predetermined width. To occur. The output circuit 60 outputs a pulse signal PULSE having a predetermined width to the output terminal when the first node is ″ H ″ and the third node is ″ L ″.

At this time, since the one input terminal of the NAND gate 15 is tied to the VCC level, the signal of the second node is transmitted to the third node as it is. The output circuit 60 generates a pulse signal PULSE having a predetermined width only when the first node is ″ H ″ and the third node is ″ L ″. However, since the second node is a signal generated by delaying the signal of the first node, even if the first node changes to the rising period, the third node may be the rising period through the NAND gate 15 having one input terminal fixed to VCC. There is a case. If the third node keeps the ″ H ″ section, a pulse signal is generated from the output circuit 60 so that the ″ L ″ section is long. This is because the third node receives the delayed signal of the second node from the NAND gate 15 as it is.

As shown in FIG. 3, it can be seen that the second node is further delayed than in FIG. 2. The third node that receives the second node as it is, transitions to ″ H ″ before the first node becomes ″ H ″, and changes to the ″ L ″ section only when the first node is ″ H ″. The pulse signal whose width is narrower to the output stage is output. In particular, when the clock period is shortened, the third node that determines the pulse width cannot be controlled from the NAND gate fixed by the VCC voltage, resulting in a problem that a narrow pulse signal is output.

Accordingly, it is an object of the present invention to provide a pulse generator circuit for stably outputting a pulse signal irrespective of whether the clock cycle becomes small.

(Configuration)

According to one feature for achieving the above object, the transmission means for receiving a clock signal from the outside and transmitting it; First inverting means for receiving the transferred clock signal and inverting the transferred clock signal; First delay means for receiving a pulse signal generated by the first inversion means and delaying it; Second delay means for receiving a delayed signal from said first delay means and delaying it; Combining means for receiving a signal generated from the first delay means and the second delay means and combining the signals generated from the first delay means; Second inverting means for inverting and outputting a combined signal generated from the combining means; And output means for receiving the inverted signals generated from the first inverting means and the second inverting means and outputting a pulse signal.

In a preferred embodiment of such a circuit, the first delay means comprises: a first node; A fourth node; An even number of inverters connected in series between the first node and the fourth node.

In a preferred embodiment of such a circuit, the second delay means comprises: a second node; And an even number of inverters connected in series between the fourth node and the second node.

In a preferred embodiment of such a circuit, the combining means comprises a NAND gate having a first input end connected to the second delay means and a second input end connected to the output end of the first delay means.

In a preferred embodiment of such a circuit, the output driving means receives a second inversion signal from the second inversion means which is lowered before the inversion signal applied from the first inversion means rises, and is applied from the outside. It is characterized by outputting a pulse signal having the same width as the clock signal.

(Example)

Such a circuit allows a signal having a pulse width corresponding to the rising period of the clock signal to be output even if the clock period is reduced.

Hereinafter, reference will be made in detail with reference to FIGS. 3 to 4 according to a preferred embodiment of the present invention.

Referring to FIG. 3, the pulse generating circuit of the novel semiconductor device of the present invention provides a combination circuit 500 for controlling a signal for determining a pulse width. In other words, when delay signals having different delay periods are output from the delay circuits 300 and 400 receiving the signal of the first node, the delay signals 300 and 400 are applied to the combination circuit 500. . The combination circuit 500 may combine the delay signals to adjust a control signal transmitted to the third node of the output circuit 700 to prevent the width of the pulse signal from decreasing.

3 is a circuit diagram showing the configuration of a pulse generating circuit according to a preferred embodiment of the present invention.

Referring to FIG. 3, the pulse generation circuit of the present invention includes a transfer circuit 100, a first inversion circuit 200, a delay circuit 300, a second delay circuit 400, a combination circuit 500, and a second circuit. An inverting circuit 600 and an output circuit 700. The transfer circuit 100 is for transferring an external clock signal to a next stage, and since an input terminal is fixed to ground, a signal opposite to the clock signal CLK is output. In the transfer circuit 100, the NOR gate 101 having one input terminal grounded receives a clock signal CLK from the outside. The first inversion circuit 200 inverts a signal having a phase opposite to that of a clock signal through the transfer circuit 100 and outputs the inverted signal to the first node. The first inversion circuit 200 is composed of an inverter 102 connected between an output terminal of the transfer circuit 100 and a first node.

The first delay circuit 300 receives a signal of the first node and outputs a pulse signal delayed by a predetermined time. In the first delay circuit 300, at least two or more inverters 103, 104, 105, 106, 107, and 108 are connected in series from the first node to the fourth node as positive integers. The second delay circuit 400 further delays the delay signal transmitted from the first delay circuit 300 to output a second delay signal, and at least two inverters connected in series from the fourth node to the second node. Fields 109, 110, 111, 112, 113, and 114. The combination circuit 500 is for controlling a signal for determining a pulse width, and is composed of a NAND gate 115 as a preferred embodiment of the present invention.

It is known to those skilled in the art that the combination circuit 115 may be composed of other NOR gates, inverters, and gates, or gates. The NAND gate 115 is applied with a delay signal passing through the first delay circuit 300 and the second delay circuit 400 to one input terminal, and the first delay signal of the first delay circuit 300 to the input terminal. Is applied to control the third node that determines the pulse width. The second inversion signal 600 is for inverting the signal generated from the combination circuit 500 and outputting the inverted signal to the third node. The second inversion signal 600 includes an inverter 116. The output circuit 700 receives the signals of the first node and the third node and outputs a pulse signal. The output circuit 700 includes a plurality of PMOS transistors MP1, MP2, MP3, and MP4, NMOS transistors MN1, MN2, MN3, and MN4, and inverters 117 and 118.

4 illustrates an output waveform diagram of nodes according to the pulse generation operation of FIG. 4.

Referring to FIG. 4, the output circuit 700 receives signals from a first node and a third node, and the third node receives a signal obtained by inverting a signal generated from the NAND gate 115 of the combination circuit 500. Licensed. The NAND gate 115 receives a second delayed signal and a first delayed signal having a shorter delay period than the second delayed signal and combines them. In the second node to which the second delay signal is transmitted and the fourth node to which the first delay signal is transmitted, as shown in the output waveform diagram, the fourth node having the short delay period is activated first, and the second node is the fourth node. The output is only delayed after the node. At this time, the third node becomes ″ H ″ after a predetermined time delay by the second node, and then falls to the ″ L ″ level by the fourth node regardless of the falling section of the second node.

Therefore, before the first node becomes ″ H ″, a signal is outputted to the third node, where the width of the rising section is narrow and the width of the falling section is long. As a result, the output circuit 700 is synchronized with the clock signal applied from the outside, and outputs a pulse signal having a width substantially equal to the clock signal. If the period of the external clock decreases, the third node is controlled by changing the configuration of the first delay circuit applied to the combination circuit 500, and thus has a width similar to that of the clock signal without being affected by the period. A stable pulse signal can be obtained.

In the pulse generating circuit according to the present invention having the above-described configuration, the NAND gate of the combination circuit receives the first delay signal and the second delay signal so that a pulse signal having a pulse width corresponding to the clock signal is not delayed. You can get it. As shown in FIG. 4, the NAND gate receives a first delay signal having a relatively short delay period, so that the third node transitions from ″ H ″ to ″ L ″ before the first node is ″ H ″. A pulse signal having a width to be obtained from an output terminal can be obtained without being affected by the third node.

As described above, the combination circuit generates a signal for controlling the pulse width by receiving delay signals having different delay intervals, thereby preventing the width of the pulse signal from being reduced and obtaining a more stable pulse signal. .

1 is a circuit diagram showing a configuration of a pulse generating circuit according to a conventional embodiment;

2A is an output waveform diagram according to the pulse generation operation of FIG. 1;

2B is an output waveform diagram according to the pulse generation operation of FIG. 1;

3 is a circuit diagram showing a configuration of a pulse generating circuit according to an embodiment of the present invention;

4 is an output waveform diagram according to the pulse generation operation of FIG.

* Explanation of symbols on the main parts of the drawings

100: transfer circuit 200: first inversion circuit

300: first delay circuit 400: second delay circuit

500: combination circuit 600: second inversion circuit

700: output circuit

Claims (5)

Transfer means for receiving a clock signal from the outside and transferring the clock signal; First inverting means for receiving the transferred clock signal and inverting the transferred clock signal; First delay means for receiving a pulse signal generated from said first inverting means and delaying it; Second delay means for receiving a delayed signal from said first delay means and delaying it; Combining means for receiving a signal generated from the first delay means and the second delay means and combining the signals generated from the first delay means; Second inverting means for inverting and outputting a combined signal generated from the combining means; And output means for receiving the inverted signals generated from the first inverting means and the second inverting means and outputting a pulse signal. And the pulse signal from the output means is a signal having a pulse having a width equal to a high section of the clock signal applied from the outside. The method of claim 1, The first delay means A first node; A fourth node; And an even number of inverters connected in series between the first and fourth nodes. The method according to claim 1 or 2, The second delay means A second node; And an even number of inverters connected in series between the fourth node and the second node. The method of claim 1, The combining means And a NAND gate having a first input terminal connected to said second delay means, and a second input terminal connected to an output terminal of said first delay means. The method of claim 1, The pulse signal from the second inversion means transitions low before the pulse signal from the first inversion means transitions high, and transitions high after the pulse signal from the first inversion means transitions low. Pulse generation circuit characterized in that.

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