JPS6280895A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To attain high-speed writing by decreasing a bit line current at the inversion from read to write and applying a write signal after a prescribed delay time. CONSTITUTION:When an external input write signal descends to L and a potential C is fed to a base in the timing transited from read to write, then a bit line current transistor TC is turned on. Then a current from a read current source IR to both bit lines B01, B11 is cut off, the bit line current is decreased and the stored electric charge in a memory cell MC is reduced. While the bit line current is lost after a prescribed delay time, a large write current from a write current source IW is fed and the write on the cell MC is applied at high speed.

Description

[Detailed Description of the Invention] [Summary] In a semiconductor memory using a flip-flop type memory cell, a bit line current control means is provided to control the bit line current immediately before writing in order to shorten the writing time. The present invention relates to a semiconductor memory in which the amount of charge accumulated in a memory cell is reduced by increasing the speed of writing and reading.

[Industrial application field]

The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory in which the bit line current is reduced to near zero immediately before writing to shorten the writing time of a saturated memory cell, thereby increasing the speed of reading and writing.

[Conventional technology]

FIG. 4 is a circuit diagram of a conventional semiconductor memory.

In FIG. 4, MC is a saturated memory, e.g.
N-type four-layer silices are cross-junctioned, W' and W- are a pair of word lines, BQI and B are a pair of bit lines, and n pairs are provided for each memory cell as shown. Also, ■□ is a current source for reading, and Is= is a current source for writing. T and T3 of memory cell MC are PN
The P-type transistors, T2 and T4, are NPN-type multi-emitter transistors;
It constitutes one side of the NNPN type Irisk.

In such a configuration, when T1 and T2 on one side are in an on state, the collector potential of T2 is at a low (L) level, so the base of T4 is also at an L level, and a flip-flop operation is performed. Memory cell selection is performed using the selected word line pair w”
, w− and the selected bin as a line pair B or + B +
The memory cell where i intersects is selected, and when selected, it is high (
H) level; when not selected, it is L level. In this description, it is assumed that the illustrated memory cell MC is selected. That is, E.C.L.
T31 to T3111 T41-741 that make up the circuit
%+Ts+~TSfi,'r''61~TI,fi, if the H level is input to the base terminal Y of T31, and the L level of Y2~Y,, the current I flows to the bit line pair.
, l are supplied. This causes bit line pair B. 1. B1
1 is selected.

In such a state, terminal A is used for reading.

The signal levels of τ are at the same potential (0), so the bases of the transistors T11 and Tel are at the same potential. At this time, the base potentials of A, -in- level 5, that is, T, and T□ are the base potentials of T2, ■1 and T4, as shown in FIG. 3(b).
The base potential V2 is set at approximately the intermediate level of the base potential V2. In this case, the base potential of T2 is naturally the collector potential of T4, and the base potential of T4 is the collector potential of T2. Now, the base potential of T2 is higher than the base potential of T4 and higher than the base potential of T11, that is, the potential of τ, so T
In the ECL circuit consisting of T2 and Tll, a current flows from T2 to bit line 13o+. On the other hand, in the ECL circuit consisting of T4 and T21, the base potential of T is T2. Since the potential of the base of the bit line B is lower than that of the base of the bit line B, that is, the potential of the bit line B
A current flows through 11. Reading is performed by comparing the currents flowing through bit lines BOI and B11 in this manner.

On the other hand, during writing, it is necessary to turn off T2, so it is necessary to raise the base potential of Tll to a level higher than the base potential of T2. That is, as shown in FIG. 3(b), τ
Raise the level to Vl.

As a result, the current flowing through the bit line BOI decreases and T
2, it is in the off state. At the same time, when the base potential of T21, that is, the level of A, is set to 2 and is lower than the base potential of T4, a current flows from T to the bit line Bll. In this case, to turn on T4 earlier.

A current Sr is applied to the bit line B11. is supplied from T41. That is, by applying a potential V2 as shown in FIG. 3(b) to the base terminal of T, T7 is turned off, and the current I that has been flowing through 'r7. is supplied to the bit line B11 via T41, and a large current is supplied to T, thereby increasing the speed of writing.

[Problem that the invention seeks to solve]

The above configuration has the following problems. That is, just before writing, current still flows through T2 to bit line SO+, and at this time, accumulated charges are still accumulated at the base-collector junction of T and T2. This is because, in a structure consisting of a base region and an epitaxial region, accumulated charges are mainly accumulated in the epitaxial region.

It is possible to speed up writing and reading by extracting this accumulated charge as quickly as possible, reducing the bit line current as much as possible during writing, and increasing the bit line current during reading. If the line current is increased, the accumulated charges on the on side of T t and T z will increase, and there is a problem that the inversion time for transition to writing will increase.

〔Example〕

FIG. 1 is a circuit diagram of a semiconductor memory according to the present invention. In FIG. 1, the same components as in FIG. 4 are given the same reference symbols. A feature of the present invention is that a multi-emitter transistor Tc is provided in common to each bit line pair in a conventional semiconductor memory circuit as a means for controlling bit line current. As mentioned above, in order to increase the speed of writing and reading, bit line B is used when switching from reading to writing.
It is necessary to reduce the bit currents of OI and B as much as possible and allow a large current to flow into the bit line B, for example, during writing, but this is possible by providing a bit line current control transistor Tc that controls the read current r. becomes. The function of the bit line current control means Tc will be explained below, but the other circuit operations are the same as the conventional circuit shown in FIG. 4, so the explanation will be omitted.

An external input write signal WE is applied to the base terminal C of the bit line current control transistor Tc as shown in FIG. 3(a).
, is supplied at the same timing as .

That is, WE is at H level at the time of reading, and then WE,
At the same timing as T falls to L level and shifts to writing, a potential as shown in C is applied to T.

supply to the base of As a result, Tc is turned on, so that currents I and l do not flow to both bit lines B01°B and are canted. As a result, both bit line currents decrease to approximately zero, as shown at T in FIG. Next, after a predetermined delay time T, the internal write signal WE is supplied to A, τ and B, B at the same timing as shown in FIG. 3(a). The subsequent write operation is the same as that of the circuit shown in FIG. 4 and will therefore be omitted, but as shown in FIG.
There is no bit line current in ll (, write side bit line Bl
By supplying a large current as shown by the current 11 to the l side, it is possible to speed up the writing. Incidentally, in FIG. 2, the solid line indicates the magnitude of the bit line current in the case of the present invention, and during reading, the IR current becomes almost zero during the delay time between reversing from reading to writing, and a large current (8) occurs during writing. flows. On the other hand, as shown by the dashed-dotted line, in the past, the current in the bit line BOI could not be completely drained, making it impossible to increase the speed.

A few nanoseconds is sufficient for this delay time.

〔Effect of the invention〕

According to the present invention, the bit line current is reduced at the time of reversal from read to write, and the write signal is supplied after a predetermined delay time, which reduces the accumulated charge in the memory cell and enables high-speed writing. As a result, read and write speeds can be increased.

[Brief explanation of drawings]

FIG. 1 is a semiconductor memory circuit diagram according to the present invention, FIG. 2 is a timing chart comparing the bit line current of the present invention and the conventional bit line current, FIG. 3(a) is a signal timing chart according to the present invention, FIG. 3(b) ) is a conventional signal timing chart, and FIG. 4 is a conventional semiconductor memory circuit diagram. (Explanation of symbols) HC...Memory cell w'', w-...Word line 1301, Bll, Bon+B+n...
Bit line Tc...Bit line current control transistor I,
I...Read current source Iw...Write current source

Claims (1)

[Claims] 1. In a semiconductor memory having a flip-flop type memory cell provided at the intersection of a plurality of word line pairs and a plurality of bit line pairs, bit line current control means is commonly provided for each bit line pair. The bit line current control means reduces the bit line current flowing through the selected bit line pair immediately before writing, and after the reduction, the write current is supplied to the writing side bit line. semiconductor memory. 2. The semiconductor memory according to claim 1, wherein the bit line current control means comprises a multi-emitter transistor.