JPH01171192A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To execute high-speed reading and writing actions by providing a circuit to control a current source by means of an address signal and a reading signal. CONSTITUTION:A current source circuit for a reading current ID and a current source circuit for a writing current IW are connected to digit lines D0-Dn, and a circuit 90 to control the IW by a WE input signal and a data input signal DIN and a control circuit 91 to control the IW by the WE input signal and an address input signal AY are connected to the current source circuit for the IW. The reading signal and address signal are inputted to the circuit 91 to control the writing current IW in making it into a second reading current, and the gate delaying time of the control circuit 91 is adjusted so that the second reading current can be made to flow for a time until the digit lines discharge a parasitic capacity and a DC level is attained. Thus, the high-speed reading action can be executed without slowing down writing speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor memories, and more particularly to high-speed semiconductor memories composed of bipolar transistors.

[Prior Art] A conventional semiconductor memory cell using a PNP transistor as a load consists of two multi-emitter bipolar transistors 200 and 201 whose bases and collectors are cross-connected to each other, as shown in FIG. The load PNP) transistors 202 and 203 are used. This semiconductor memory cell has a small area and can hold information with even less current, making it suitable for high integration and low power consumption. On the other hand, in the memory cell, the base potential in the on state is sufficiently higher than the collector potential, so the collector junction of the NPN transistor is forward biased and saturated, and a large amount of charge is accumulated in the collector. Therefore, during writing, the large amount of accumulated charge is quickly discharged, so a write current IW is added as shown in FIG. 2.

[Problems to be Solved by the Invention] The conventional memory cell described above is suitable for high integration, but in order to increase the speed of the read operation, it is necessary to increase the read current. That is, in order to drive a memory cell, a word line is selected and then a digit line is selected, but as the degree of integration increases, the time required to drive these lines increases. On the other hand, the word line driving method is
As is well known, it is possible to easily increase the speed by using a delayed discharge circuit, but regarding the digit line, the parasitic capacitance of the wiring and the NP connected to the digit line
N) The junction capacitance of the emitter of the transistor is large, and in order to discharge this quickly using only the read current ID, it is necessary to increase the read current. However, this memory cell has a problem in that when the read current is increased as described above, the charge accumulated in the memory cell becomes even larger, resulting in a slow write speed.

[Differences between the invention and the prior art] In contrast to the above-described conventional circuit, the present invention uses a control circuit that is supplied with a WE (over par) input signal and an address signal to control the write current that conventionally functioned only during a write operation. It has the content that it functions as a second read current that operates for an arbitrary time.

[Means for Solving the Problems] An object of the present invention is to solve these conventional problems and provide a semiconductor memory capable of high-speed read/write operations.

The present invention provides a semiconductor memory in which a pair of transistors constituting a flip-flop and a memory cell having a PNP load transistor are connected between a pair of digit lines, and digit line selection means connected to the digit line;
A first current source connected to the digit line, a second current source for flowing a larger current than the first current source, a write signal, and write data are manually input to the second current source. The second current source is configured by providing means for controlling a current source, and means for controlling the side leg means by an address signal and a write signal so that the second current source causes a current to flow from the digit line for an arbitrary time only during reading. Ru.

[Example code] Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows one embodiment of the invention. In this embodiment, the digit lines DO'Do (over par) to Dn (Dn
(over par)) is connected to a current source circuit for read current ID and a current source circuit for write current IW, and the current source circuit for IW is connected to the WE (over par) manual signal and data input signal DIN. , I'vV, and a control circuit 91 that controls IW using a WE (over par) input signal and an address human input signal AY.
are connected. In the figure, 100 and 101 indicate a pair of transistors constituting a flip-flop.
Reference numeral 3 designates load transistors, and these transistors 100 to 103 constitute a memory cell 104.

Next, the operation will be explained. For a write operation, the digit lines (e.g., DO, Do (over par)) are connected to the RC/WC in response to the write input signal and the data input signal.
It is set to high or low level through the signal line, and the selected memory cell has its emitter connected to the high level digit line (NPN) transistor is off and its emitter is connected to the low level digit line. The NPN) transistor in the memory is turned on, and data is written. At the same time, the IWW control circuit 90 controls the signal lines \VCA, WC
B becomes a high level or a low level depending on the write data, and the write current ■W is made to flow only on the digit line side to which the transistor of the memory cell to be turned on is connected, thereby speeding up the write operation. At this time, signal lines WCA, WC
Since the circuit connected to B is in an off state as described below, it does not affect the write operation.

Next, the read operation will be explained. The read signal and address signal are input to a circuit 91 that controls the write current I'vV as a second read current. As shown in FIG. 3, the control circuit 91 is composed of an exclusive OR circuit and a gate delay circuit, and generates a pulse output for the address signal AY for a time corresponding to the speed delay caused by the gate. do. This is WE
(Over Par) When writing with the input signal, the output is fixed at a low level, so the control circuit 91 is not involved in the writing operation. In addition, in the case of access only in the word direction, the digit line is not switched, so the control circuit 9
1 need only be considered for the address input signal on the digit side. The transistor Q1 is turned on by the pulse generated by the read signal and the address input signal AY, and current flows through the diodes D1 and D2, so that the IW control signal on the signal lines WCA and WCB becomes low level. Therefore, the current IW flows as a read current through the digit line for a time corresponding to the output pulse.

This is shown in FIG. Here, the second read voltage ff1
The time that I to V flows through the digit line must be neither long nor short. This is because if the second read current IW is made to flow for a long time, a large amount of charge will be accumulated in the memory cell, resulting in a slow write speed, and if it is too short, the read operation will not be able to speed up. Therefore, the second read current is caused by the digit line discharging the parasitic capacitance as described above.
If the gate delay time of the control circuit 91 is adjusted so that the time required to reach the C level is adjusted, a high-speed read operation can be performed without slowing down the write speed.

FIG. 5 shows another embodiment of the invention. In this example, I
The second control circuit that controls the W control signals WCA and WCB is composed of two current switch circuits, and the operation during reading and writing is the same as in the above embodiment.

[Effects of the Invention] As explained above, the present invention provides a circuit that controls a current source that conventionally functions only during writing using an address signal and a read signal, thereby achieving high-speed reading. Write operation becomes possible.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, Fig. 2 is a circuit diagram showing a conventional example, Fig. 3 is a block diagram showing a part of one embodiment, and Fig. 4 is a timing diagram of one embodiment. The chart, FIG. 5, is a circuit diagram showing another embodiment of the present invention. 100.101...transistor, 102.103
...Load transistor, 104...Memory cell, DO, Do (over par), Dn, Dn (
Over par)...Digital line, 90.91...Control circuit, Ql, Q2...Transistor, DI, D2...
····diode. ”c/wc Figure 3

Claims (1)

[Claims] A pair of transistors forming a flip-flop and a PN
A memory cell having a P load transistor is connected between a pair of bit lines, a bit line selection circuit connected to the bit line, and a first current for a read/write operation connected to the bit line selection circuit. In a semiconductor memory device having a current source and a second current source that operates as an additional write current source during writing, the second current source is activated during reading by a one-shot control signal generated in response to a read signal and an address signal. A semiconductor memory device comprising a control circuit that functions as a one-shot read current source.