JPS60217725A - Buffer circuit - Google Patents

Abstract

PURPOSE:To obtain an ECL input/output buffer circuit connected directly to a logical circuit of bipolar transistor (TR) constitution by providing a resistive element between a source of an NMOS and a negative power supply being components of a CMOS logical circuit. CONSTITUTION:The buffer circuit consists of an input buffer circuit of a block 2 shown in broken lines in Fig. and an output buffer circuit of a block 19 in broken lines. A diode D3 is inserted between a source of an NMOSM2 of a CMOS inverter of the block 2 and a negative power terminal VEE, and even when the potential of a node A is insufficient to a CMOS input level, the source potential of the M2 is boosted by the diode D3, the M2 is turned off and the power consumption of the CMOS is cut off. Thus, low power consumption is attained to a buffer of an address recorder 9. A diode D4 in the block 19 is used for level shift and high speed operation is attained by bringing a TRQ5 of the next stage into the unsaturated state.

Description

[Detailed Description of the Invention] [Technical Field] The present invention is applicable to a) turf-nice circuit of a logic circuit composed of bipolar transistors and a CMO8 (complementary insulated gate field effect transistor). It is about effective techniques.

[Background technology]

As a MOS interface circuit that can output ECL level signals, 19'82 IEEE Inter-na
tional 5olid-8tate C1rcui
As described in TS Conference P248-P249, a configuration is known in which an ECL level signal is obtained by combining a CMOS inverter and an emitter follower circuit. However, with this configuration, the output low level is clamped to -2.0 volts and is not ECL compatible.

The present invention has been devised to eliminate this drawback.

[Purpose of the invention]

The purpose of the present invention is to provide an ECL that can directly connect the output of a CMO8 logic circuit to a logic circuit composed of bipolar transistors, which aims to reduce power consumption without sacrificing high operating speed.
The purpose of the present invention is to provide an input/output buffer circuit.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a diode is inserted between the negative power supply terminal and an N-channel MO8FET that constitutes a CMOS inverter that receives the output from a logic circuit made up of bipolar transistors, thereby suppressing the through current flowing through the CMOS inverter.

In addition, the P-channel MO8 that constitutes the CMOS inverter
By providing a level shifting diode between the FET and the other power supply terminal and supplying this level-shifted signal to the differential transistor that constitutes the next-stage differential amplifier circuit, This is to prevent movement.

[Example 1] In the same figure, a static type tAM (random type) composed of a bipolar transistor and a MOSFET is shown.
A circuit diagram of the access memory is shown.

In the figure, each circuit block surrounded by a dashed-dotted line is
It is formed on one semiconductor substrate, for example, a silicon substrate, using well-known semiconductor integrated circuit technology.

In the figure, numerals 1 to 14 are memory cells, each having a similar structure.

In the figure, a specific circuit is shown only for the memory cell 11 as a representative. Memory cells are P-channel type MOS FET M42Me and N-channel type M
CMO8! composed of O8FETM, , M7!
A transmission gate MOS FET M provided between a flip-flop, a pair of input/output nodes of this flip-flop, and a pair of complementary data lines Do, Do.
s 2M a . The gate of the transmission gate MO8FET in the memory cell is coupled to the word mW, for transmitting the selection signal from the X address decoder 9 to the memory cell.

The X address decoder 9 receives an internal complementary address signal output from an address buffer, which will be described later, and selects a word line specified by this internal complementary address signal from a plurality of word lines. A selection signal is generated to select a memory cell coupled to the memory cell. Although not particularly limited, this X address decoder 9 is composed of a plurality of unit decoders,
Each unit decoder is composed of a NAND (NAND) circuit.

0 is a Y address decoder, which receives an internal complementary address signal output from an address buffer, which will be described later, and receives a plurality of data line pairs D0 . D,,D,
, Dt, a selection signal is generated for selecting the data line pair designated by this internal complementary address signal.

The selection signal formed by the Y address decoder 1 (HC) is supplied to the column switch circuit 16. Upon receiving the selection signal, the column switch circuit connects the data line pair specified by the selection signal to the common data line. Bind to CD and CDlIC.

A desired memory cell is selected from among the plurality of memory cells ~14 by the X, X address decoders 9, 10 and column switch 16 described above. , a no-repel (GND) selection signal is supplied from the X decoder 9 to the word line W, and a low level (V□) selection signal is supplied to the word line W. As a result, the storage contents of the memory cell 11 are transmitted to the complementary data line pair Do, Do, and the storage contents of the memory cell 13 are transmitted to the complementary data line pair, , D,. The X address decoder 10 outputs a selection signal for selecting the complementary data line pair Do, Do. As a result, the complementary data line pair D0°D is coupled to the common data line pair CD, CD via the column switch circuit 16. That is, the storage contents of the memory cell 11 are
It is transmitted to the common data line pair CD, CD.

Common data line pair CD, storage information transmitted to CD is
The signal is supplied to the amplifier 11@circuit 17, where it is amplified and supplied to the next stage logic circuit 18. The operation of the amplifier circuit 17 is controlled by an internal step selection signal C8.

That is, when this RAM is not selected, the amplifier circuit 17 is rendered inactive by the internal chip selection signal C8. This makes it possible to reduce power consumption in a chip non-selected state.

The logic circuit 18 transmits the output signal from the amplifier circuit 17 to the output buffer circuit 19 during a read operation,
During a write operation, it works so as not to transmit the above output signal. In order to do this, although not particularly limited, in this embodiment, the internal write enable signal WE,
The logic circuit 18 is constituted by an AND circuit receiving the output signal.

Note that the output of the output buffer circuit 19 is coupled to the -1 terminal of the resistor R6 via an external terminal. The other terminal of this resistor R6 is coupled to, for example, a -2.0 (V) power supply terminal as shown in the figure. As a result, the output signal V. The low level of LIT is approximately -2.0 (
V).

Internal signals such as the above-mentioned internal chip selection signal and internal write enable signal are converted into IR by an internal signal generation circuit 15 which receives the write enable signal WE and the chip selection signal C8.

Note: The circuitry used to write information to the memory cells has been omitted to simplify the drawing.

In the figure, numerals 1, 4 to 8 are address buffer circuits to which the present invention is applied, respectively, which receive an external address signal AXn (or AYn) and form the above-mentioned internal complementary address signal. These address buffer circuits have similar configurations. In order to simplify the drawing, only the detailed circuit diagram of address buffer circuit 1 among these address buffer circuits is shown in the figure.

Note that the internal complementary address signal is the internal address signal aXn(AYn) which is in phase with the external address signal Axn(AYn).
aYn) and an internal address signal 1xn (□Yn) whose phase is inverted with respect to it.

In the drawings, 1 is a buffer circuit to which the present invention is applied. This buffer circuit J consists of a bipolar transistor Q
an emitter 7 follower circuit consisting of I, a diode D1, and a constant current circuit, a differential transistor Q to which the output from the emitter follower circuit is supplied, a differential transistor Qs to which a reference voltage is supplied, and the differential transistor Qt.
- To supply a reference voltage to the differential amplifier circuit consisting of a constant current circuit connected to the load resistors R1 and R of Qa and the common emitters of the differential transistors Qx and Qs, and the differential transistor Q. Resistance Rs = 14
and a bipolar transistor QCs to which the −1 output signal of the differential amplifier circuit is supplied; an emitter follower circuit consisting of a diode D2 and a constant current circuit; and a P-channel MO to which the output from the emitter 7 follower circuit is supplied.
8FETM.

and a CMOS inverter consisting of an N-channel MO8FET, and an N-channel/I that constitutes the above CMOS inverter.
/MO8FETM, and a diode D3 connected between the source of the MO8FETM and the power supply terminal v0. Then, the output signal of the CMOS inverter (internal address signal ax
n) is supplied with the above-mentioned X address decoder 9Vc. Further, the other output signal of the differential amplifier circuit is supplied to a logic circuit 3 configured similarly to the logic circuit 2 consisting of the emitter follower circuit, CMOS inverter, and diode D3. The output signal of this logic circuit 3 (
Internal address signals (i, n) are also supplied to the X address decoder 9. Output signals of address buffer circuits 4 and 5 (
The internal complementary address signal) is supplied to the X address decoder 9, and the output signals of the address buffer circuits 6, 7 and 8 (
(internal complementary address signal) is supplied to Y address decoder 1o.

If the potential of node A is insufficient to reach the CMO8 power level due to the logic circuit composed of bipolar transistors, both MO8FETM and M constituting the CMOS inverter are turned on, and the MO8FETM1 is turned on.
A through current flows through M2 and M2. In order to reduce this, a diode is inserted between the source of the MO8FETM and the power supply terminal EE. As a result, the above MO8F
Since the source potential of ETM is raised, MO8FET
M is turned off and the through current is cut. As a result, power consumption can be reduced.

[Embodiment 2] In the drawings, 19 is an output buffer circuit to which the present invention is applied.

This output buffer circuit 19 consists of a MO8FETM+st M+a and a level shift diode D4 that constitute a CMOS inverter, a MO8FETM+7°M+a and a level shift diode D, and a differential amplifier circuit that constitutes a differential amplifier circuit to which the output of the CMOS inverter is supplied. It is composed of dynamic transistors Q,5, Qa, a resistor R6, a constant current circuit, and a bipolar transistor Q7 to which the output of the differential transistor is supplied. One end of the level shift diodes D4 and D5 is connected to the power supply terminal GND, and the other end is a P channel ff that constitutes a CMOS inverter.
Connected to the sources of iMO8FETM+5 and M, □. The CMOS inverter has a two-stage configuration, and the signal passed through the two stages of the CMOS inverter is sent to the differential transistor Q that constitutes the next-stage differential amplifier circuit.

supplied to the base of Further, the signal passed through one stage of CMOS inverter is supplied to the base of differential transistor Q6. The output signal of the differential amplifier circuit is then sent to the output terminal via the output bipolar transistor Q of the oven collector. , issued from T.

In this embodiment, the logic circuit 8 is constituted by a CMO8 logic circuit. Therefore, the output buffer circuit I
9 is supplied with a high level or low level signal formed by the CMO8 logic circuit 18.

Now, if the output signal of the CMO8 logic circuit 18 is at a low level (approximately GNDt), the N-channel MO8FETM 1a constituting the CMOS inverter is turned on, and the signal level at the node B is at low level ■E+,
, and is supplied to the second stage CMOS controller. As a result, the P-channel type MO8FET MI7 that constitutes the second stage CMOS inverter is turned on, and the signal level of node C becomes high level, and the differential transistor Q that constitutes the next stage differential amplifier circuit is turned on. supplied to the base.

The high level supplied to the base of the differential transistor Q is the P-channel type MOS FET M1? which constitutes the previous stage CMOS input/<-. The power supply terminal GN is adjusted by the amount of level shift caused by the level shift diode D provided between the source of the power supply terminal GN and the power supply terminal GN
The potential is level-shifted from the potential of D. Therefore, the potential supplied to the base of the differential transistor Q is a potential shifted by the level shift amount from the potential supplied to the collector thereof.

will operate in the non-saturated region. The high-level potential supplied to the base of the differential transistor Q6 is also lower than the potential of its collector for the same reason as described above. Therefore, the differential transistor Q6 also operates in the non-saturation region. As a result, the output buffer circuit can operate at high speed.

[Example 3] Although not shown, the P-channel type MOS is used in the circuit of Example 20.
F E TM+s (Ml?) source and power supply terminal G
Level shift diode D4 provided between ND
And, the above MOS FETMI! l(
M+? ) and the output terminal B (Q). In this case as well, the high level is level-shifted and a differential transistor configured with a bipolar transistor in the next stage is formed, as in the second embodiment. Since the differential transistor Qs (or Q,) is supplied to Q, (or Q,), operation in the saturation region of the differential transistor Qs (or Q,) can be prevented, and the same effect as in the second embodiment can be obtained.

〔effect〕

(1) When a signal from a logic circuit composed of bipolar transistors is supplied to an MO8 logic circuit composed of MOSFETs, the M
By inserting a diode D between the source of the MO8FETM and the power supply terminal V, it is possible to increase the source potential of the MO8FETM2, thereby reducing the through current flowing through the CMOS inverter. This has the effect of reducing power consumption.

(2) By inserting a level shift diode D between the source and the power supply terminal GND or on the drain side of the MOS FET M 1a constituting the CMOS inverter as a CMO8 logic circuit, the high level is level shifted. Since the signal is outputted, the differential transistor Q constituting the next-stage differential amplifier circuit operates in a non-saturation region, resulting in an effect that the operating speed can be increased.

(3) According to (1) above, it is possible to achieve the effect of reducing the power consumption of the RAM.

(4) According to (2) above, it is possible to achieve the effect that the RAM can operate at high speed.

(5) The synergistic effect of the above (3) and (4) makes it possible to obtain a RAM with low power consumption and high speed operation.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the diode D provided between the source of the MO8FETM constituting the CMOS inverter and the power supply terminal v0 is not limited to a diode, but may be a resistive element. Also, the level shift diode can be connected in two stages.

[Application field]

The present invention can be widely used, for example, by being applied to an input/output buffer circuit as an interface circuit between a logic circuit composed of bipolar transistors and a logic circuit composed of MOSFETs.

[Brief explanation of the drawing]

The drawing shows a semiconductor memory circuit showing an embodiment of the present invention.

Claims (1)

[Claims] 1. A buffer characterized in that a resistance element is provided between the source of an N-channel MO8FET and a negative power supply terminal forming a complementary MO8 logic circuit that receives an output from a logic circuit composed of bipolar transistors. circuit.