JP2972960B2 - Digital output circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology effective when applied to a digital output circuit, and further to a digital output circuit implemented as a semiconductor integrated circuit device. The present invention relates to a technique effective for use in an output buffer unit for converting a sense output to a level and outputting the converted output to the outside (for example, Nikkei BP, “Nikkei Electronics December 29, 1986 (No. 410), No. 129). Pp. 146).

[Prior Art] For example, in a semiconductor memory having a BiCMOS configuration, in an output buffer unit for converting the level of storage information read from a selected storage cell and outputting the converted information to the outside, the output is changed from H (high level) to L (low level) or L (low level). A switching noise occurs during a transition when the driving is switched from "H" to "H". This switching noise becomes remarkable as the speed of the semiconductor memory is increased, and is likely to cause a malfunction.

Therefore, the present inventors have developed an output preset type digital output circuit as shown in FIG. 3 as a measure against the switching noise.

The digital output circuit shown in FIG. 1 is configured for use in a data output buffer section of a semiconductor memory, and includes a level conversion circuit 1 for converting a signal (not shown) from a sense circuit to a predetermined logic level. An output stage 2 which digitally drives the output out to H or L by being driven by the level conversion circuit 1; and an L preset level VpL which makes the output out higher than the normal L level VoL.
And an H level preset circuit 4 for selectively driving the output out to an H preset level VpH lower than the normal H level VoH. As shown in FIG. 4, before the output out is switched from L to H or from H to L, the output out is synchronized with a preset clock CP generated based on, for example, a read signal or a chip enable signal. Then, by operating the preset circuits 3 and 4, the output out is switched stepwise through the L or H preset level VpL or VpH, thereby reducing the switching noise accompanying the switching of the output out. It is intended to be dispersed and reduced.

The circuit shown in FIG. 3 will be described in more detail. The output stage 2 includes a bipolar transistor Q1 connected to the high-level power supply potential Vcc and forming a pull-up driving element.
And an n-channel MOS transistor N1 connected to the low-level power supply potential V _EE (GND) and forming a pull-down drive element
And a bipolar transistor Q2 which is diode-connected and performs a level shift.

The level conversion circuit 1 complementarily turns on and off Q1 and N1 of the output stage 2 in a steady state. As a result, the output out in the steady state is driven to the specified L level VoL or H level VoH. Further, although not shown in detail, when the output out is switched and driven, the level conversion circuit 1 uses the preset clock CP which is set to the active level of H prior to the switching drive to output the output stage 2. Q1 and N1
Are both turned off. Thus, the level of the output out is controlled by the preset circuits 3 and 4 at the time of presetting when the output out is switched and driven.

The L-level preset circuit 3 is connected in parallel to Q1, which is a pull-up drive element of the output stage 2, so that the L-level preset circuit 3
Bipolar transistor Q4 as a preset drive element
When preset, a constant voltage (VpL +
2VBE VBE is constituted by a constant voltage circuit 31 for applying a voltage between the base and the emitter of the bipolar transistor. The Q4 serving as the L preset drive element pulls up the output out to an L preset level VpL, which is slightly higher than the L level VoL in a steady state, by a constant base voltage (VpL + 2VBE) given at the time of preset.

In this case, the constant voltage circuit 31 is a bipolar transistor
The voltage applied between the collector and emitter of Q3 is
By dividing the voltage by 2 and applying it to the base of Q3, the values of the resistors R1 and R2 and the base-emitter voltage VBE of Q3
Is formed between the collector and the emitter. According to the active type constant voltage circuit 31, the constant voltage value can be arbitrarily set variably by the values of the resistors R1 and R2.
The L preset level VpL can be optimized.

The H-level preset circuit 4 is connected in parallel to N1 serving as a pull-down driving element of the output stage 2 so that the H-level preset circuit 4 has an H level.
Bipolar transistor Q6 as a preset drive element
And a constant voltage circuit 41 for transmitting the voltage appearing at the output out by lowering the voltage by a constant voltage (≒ VpH + VBE), and the constant voltage circuit 41
When presetting the voltage dropped by 41
An n-channel MOS transistor N2 applied to the base of
And a resistor R5 for extracting the base charge of the Q6. The Q6, which constitutes the H preset drive element, has its output out limited to an H preset level VpH slightly lower than the H level VoH in a steady state by a base voltage applied by being lowered by a constant voltage (≒ VpH + VBE) from the output out. Drive down.

Also in this case, the constant voltage circuit 41 employs an active circuit. That is, the voltage applied between the collector and the emitter of the bipolar transistor Q5 is divided by the resistors R3 and R4 and applied to the base of the Q5, whereby the resistors R3 and R
A constant voltage determined by the value of 4 and the base-emitter voltage VBE of Q5 is obtained between the collector and emitter. With this, the preset level Vp
L can also be optimized by the values of the resistors R3 and R4.

[Problems to be solved by the invention] However, it has been clarified by the present inventors that the above-described technology has the following problems.

That is, in the above-described technique, in the H-level preset circuit 4, the voltage lowered by the constant voltage circuit 41 from the output out voltage is applied to the base of the bipolar transistor Q6, which is the H preset drive element.
In other words, at the time of the H preset performed before the output out is switched from H to L, the voltage obtained by subtracting the voltage drop in the constant voltage circuit 41 from the steady-state H level VoH remaining in the output out. Is applied to the base of Q6. Therefore, when the power supply potential Vcc becomes higher than the specified potential, the increased power is added to the base voltage of Q6 and applied as it is. For example, power supply potential Vcc
Rises from the specified 4.5V to 6.5V, this rise (6.5
−4.5 = 2V) directly becomes the rise of the base applied voltage of Q6. As a result, the Q6 is excessively conductively driven, and the output out is excessively pulled down. As a result, as shown by a dotted line in FIG. 4, the H preset level VpH becomes too low and approaches the logical threshold Vth. As a result, the fluctuation range of the level of the output out at the time of presetting becomes large, and the switching noise increases. Further, when the output out after the preset is continuously driven to H, a malfunction such that the output out is instantaneously driven to L easily occurs. As described above, the above-described technique has a problem that the power supply potential Vcc is highly dependent and the allowable variation range of the power supply potential Vcc is very narrow.

Further, in the above-described technique, the bipolar transistor Q5 forming the constant voltage circuit 41 in the H-level preset circuit 4 is in an inactive state in which it is completely turned off by turning off N2 in a normal state. For this reason, at the time of the H preset, it takes time until the above-mentioned Q5 is raised from the completely inactive state to the active state in which the predetermined constant voltage operation is performed, and the output out is driven to the predetermined H preset level VpH. Has been slowed down, which has hindered the speeding up of the output operation.

An object of the present invention is to provide a digital output circuit with a switching circuit.
An object of the present invention is to provide a technique for stably performing an output preset operation for reducing noise without being affected by fluctuations in a power supply potential.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for Solving the Problems] The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, when driving the digital output to the H preset level lower than the normal H level, together with the first constant voltage circuit for applying a voltage obtained by lowering a constant voltage from the voltage appearing at the output to the H preset active terminal. And a second constant voltage circuit for limiting the voltage applied to the control terminal of the H preset drive element to a certain value or less.

[Operation] According to the above-described means, even if the voltage lowered by the constant voltage by the first constant voltage circuit increases at the time of presetting due to an increase in the power supply potential, the control terminal of the H preset driving element is connected to the control terminal. By limiting the actually applied voltage to a certain voltage or lower, it is possible to prevent the H preset level from abnormally lowering due to transient driving of the H preset driving element.

Thus, the object of stably performing the output preset operation for reducing the switching noise of the digital output circuit without being affected by the fluctuation of the power supply potential is achieved.

EXAMPLES Hereinafter, preferred examples of the present invention will be described with reference to the drawings.

In the drawings, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows an embodiment of a digital output circuit to which the technique of the present invention is applied.

The digital output circuit shown in FIG. 1 is configured to be used for a data output buffer section of a semiconductor memory, and its basic configuration is similar to that of the above-described technology, in that a signal from a sense circuit (not shown) is used. ) To a predetermined logic level, an output stage 2 driven by the level conversion circuit 1 to digitally drive the output out to H or L, and the output out to L at a steady state.
An L-level preset circuit 3 for performing a pull-up drive to a preset level VpL higher than the level VoL, and a pull-down drive for the output out to an H-preset level VpH lower than the H level VoH in a normal state. As shown in FIG. 2, before the output out is driven to be switched from L to H or from H to L, for example, based on a read signal or a chip enable signal, as shown in FIG. By operating the preset circuits 3 and 4 in synchronization with the created preset clock CP, the output out is switched stepwise through the L or H preset level VpL or VpH, thereby outputting The purpose is to reduce the switching noise caused by switching out by dispersing it.

The output stage 2 includes a bipolar transistor Q1 connected to the high-level power supply potential Vcc and forming a pull-up drive element,
It is composed of an n-channel MOS transistor N1 connected to the low-level power supply potential V _EE (GND) and serving as a pull-down drive element, and a bipolar transistor Q2 diode-connected and performing a level shift.

The level conversion circuit 1 complementarily turns on and off Q1 and N1 of the output stage 2 in a steady state. As a result, a prescribed L level VoL or H level VoH is output to the output out during the steady state. Further, although not shown in detail in the level conversion circuit 1, when the output out is switched and driven,
Prior to this switching drive, Q1 of the output stage 2 is connected to the preset clock CP which is set to the active level of H.
Both N1 are configured to be turned off. Thus, the level of the output out is controlled by the preset circuits 3 and 4 at the time of presetting when the output out is switched and driven.

The L-level preset circuit 3 is connected in parallel to Q1, which is a pull-up drive element of the output stage 2, so that the L-level preset circuit 3
Bipolar transistor Q4 as a preset drive element
When preset, the constant voltage (VpL + 2
VBE: VBE is constituted by a constant voltage circuit 31 for applying a voltage between the base and the emitter of the bipolar transistor. Q4, which is an L preset drive element, is driven by a constant base voltage (VpL + 2VBE) given at the time of preset.
The output out is limitedly pulled up to an L preset level VpL which is slightly higher than the L level VoL in a normal state.

The constant voltage circuit 31 of the level preset circuit 3 divides the voltage applied between the collector and the emitter of the bipolar transistor Q3 by the resistors R1 and R2 and applies the voltage to the base of the Q3, thereby obtaining the resistors R1 and R2. , And a constant voltage determined by the base-emitter voltage VBE of Q3 between the collector and emitter. The values of the resistors R1 and R2 are selected and set so as to optimize the L preset level VpL.

The H-level preset circuit 4 is connected in parallel to N1 serving as a pull-down driving element of the output stage 2 so that the H-level preset circuit 4 has an H level.
Bipolar transistor Q6 as a preset drive element
And a constant voltage circuit 41 for transmitting the voltage appearing at the output out by lowering the voltage by a constant voltage (≒ VpH + VBE), and the constant voltage circuit 41
When presetting the voltage dropped by 41
And an n-channel MOS transistor N2 applied to the base of the transistor. H-preset drive element
Q6 is a preset voltage VpH which is slightly lower than the steady-state H level VoH by the base voltage which is given by lowering the output out by a fixed voltage (≒ VpH + VBE).
The pull-down drive is limited.

The constant voltage circuit 41 of the H level preset circuit 4 is also an active circuit, and the voltage applied between the collector and the emitter of the bipolar transistor Q5 is divided by the resistors R3 and R4 and applied to the base of the Q5. The resistance R
3. A constant voltage determined by the value of R4 and the base-emitter voltage VBE of Q5 is obtained between the collector and emitter. And the above H preset level
The values of the resistors R1 and R2 are selected and set so as to optimize VpH.

Here, the embodiment shown in FIG. 1 has the following configuration in addition to the above-described configuration.

That is, in the H-level preset circuit 4, the voltage appearing at the output out is lowered by a constant voltage (≒ VpH + VBE) and applied to the base of the Q6.
In addition, there is provided a second constant voltage circuit 42 for limiting the voltage applied to the base of Q6 to a certain voltage (Vp) or less. The second constant voltage circuit 42 includes a first constant voltage circuit 41
Similarly, the voltage applied between the collector and the emitter of the bipolar transistor Q8 is divided by the resistors R7 and R8 and applied to the base of the Q8, whereby the values of the resistors R7 and R8 are The constant voltage determined by the base-emitter voltage VBE of Q6 is
It is obtained between the emitters. The values of the resistors R7 and R8, which determine the constant voltage value, are selected and set so that the H preset drive by Q6 is properly performed.

As a result, the power supply potential Vcc rises,
At the time of presetting, even if the voltage lowered by the constant voltage by the first constant voltage circuit 41 increases, the voltage actually applied to the base of the H preset driving element Q6 is limited to a constant voltage (Vp) or less. You. As a result, an abnormal decrease in the H preset level VpH due to the transient driving of Q6 is prevented. For example, even when the power supply potential Vcc rises from 4.5 V to 6.5 V, as shown by the dotted line in FIG. 2, the decrease in the H preset level VpH can be reduced to almost negligible level. Therefore, the output preset operation for reducing the switching noise of the digital output circuit can be stably performed without being affected by the fluctuation of the power supply potential Vcc.

Further, in the embodiment shown in FIG. 1, a predetermined idling current is supplied to the first constant voltage circuit 41 by the bipolar transistor Q7 and the n-channel MOS transistor N3.
Circuit means 43 for flowing Iid at a normal time is provided. The MOS transistor N3 operates as a constant current circuit when a constant control voltage Vcs is applied to its gate.

As a result, the bipolar transistor Q5 of the first constant voltage circuit 41 maintains an active state of performing a predetermined constant voltage operation even in a steady state. As a result, the above Q5 becomes
The constant voltage operation is performed at the same time when the preset clock CP rises to H, so that the limited drive of the H preset driving element Q6 can be immediately performed. As a result, the time for driving the output out to the predetermined H preset level VpH is greatly reduced, and the output operation is further speeded up.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Nor.

For example, the preset driving element may be a MOS transistor. Further, a plurality of MOS transistors N2 whose on / off control is performed by the preset clock CP can perform a logical operation by being connected in series.

In the above description, the case where the invention made by the present inventor is applied to a semiconductor memory, which is the application field of the background, has been mainly described. However, the present invention is not limited to this. For example, a semiconductor integrated circuit such as a gate array is used. Applicable to devices.

[Effects of the Invention] The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, an effect is obtained that the output preset operation for reducing the switching noise of the digital output circuit can be stably performed without being affected by the fluctuation of the power supply potential.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of a digital output circuit to which the technology of the present invention is applied, FIG. 2 is a diagram showing an operation example of the above-mentioned circuit, and FIG. 3 is a digital output studied prior to the present invention. FIG. 4 is a diagram illustrating a configuration example of a circuit, and FIG. 4 is a diagram illustrating a configuration example of the circuit. 1 ... Level conversion circuit, 2 ... Output stage, Q1 ... Bipolar transistor as pull-up drive element, N1 ... MOS transistor as pull-down drive element, 3 ... L
Level preset circuit, Q4 ... Bipolar transistor as L preset drive element, 31 ... Constant voltage circuit,
4... H level preset circuit, Q6... Bipolar transistor as H preset drive element, 41.
Constant voltage circuit, 42... Second constant voltage circuit, 43... Circuit means for flowing an idling current Iid, out.
CP: Preset clock, VoL: L level at steady state, VpL: L preset level, VoH: H at steady state
Level, VpH ... H preset level.

Claims (5)

(57) [Claims] An output is digitally driven to a high level or a low level by a pull-up driving element and a pull-down driving element which are driven complementarily to each other, and prior to switching the output to a high level or a low level, A low-level preset circuit that turns off both the pull-up drive element and the pull-down drive element and selectively pulls up the output to a low level that is higher than the steady-state low level; A high-level preset circuit that performs pull-down driving limited to a high level lower than the high level of the output preset type digital output circuit, wherein the high-level preset circuit is connected in parallel with the pull-down drive element. Reduce the voltage appearing at the connected preset drive element and the output by a predetermined voltage, and And a second constant voltage circuit for limiting a voltage applied to the control terminal of the preset drive element to a certain level or less. Digital output circuit. 2. The first constant voltage circuit is constituted by an active constant voltage circuit whose constant voltage value can be variably set by a resistor, and a predetermined idling current is constantly supplied to the first constant voltage circuit. 2. A digital output circuit according to claim 1, further comprising a circuit means for flowing. 3. The constant voltage circuit according to claim 1, wherein the voltage applied between the collector and the emitter of the bipolar transistor is divided by a resistor and applied to the base of the bipolar transistor. 3. A digital output circuit according to claim 1, wherein said digital output circuit comprises an active circuit for obtaining a constant voltage determined by an emitter-to-emitter voltage between said collector and emitter. 4. The digital output circuit according to claim 1, wherein said pull-up driving element is a bipolar transistor, and said pull-down driving element is a MOS transistor. . 5. The digital output circuit according to claim 1, wherein said preset driving element is a bipolar transistor.