JP2820006B2 - Semiconductor integrated circuit with small standby current - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit including a logic gate circuit formed of MOS transistors and performing a logical operation.

[0002]

2. Description of the Related Art In recent years, with the development of fine processing technology, the element size of a MOS type field effect transistor used in a semiconductor integrated circuit has been extremely miniaturized. At the same time, circuit speed performance has been improving, but various reliability problems have arisen. For example, there is a deterioration phenomenon of a transistor due to a hot carrier effect, a breakdown of a gate insulating film due to TDDB, and the like. In addition, an increase in power consumption due to an increase in the degree of integration of a semiconductor integrated circuit is a problem that cannot be ignored.

Therefore, in a semiconductor integrated circuit in which the gate length of a MOS field effect transistor is 0.5 μm or less, measures are generally taken to lower the power supply voltage. In the future, it is inevitable that the power supply voltage will be further reduced as the MOS field effect transistor becomes finer.

However, if the power supply voltage is lowered without changing the threshold voltage of the MOS field effect transistor, there is a problem that the operation speed of the semiconductor integrated circuit is reduced. This is due to a physical phenomenon in the operation of the transistor that the drain current of the MOS field effect transistor substantially follows the following equation (1).

Drain current = {(gate voltage) − (threshold voltage)} to the power of α (1) (where α is about 2) As can be seen from the above equation (1), the threshold voltage is fixed. As the power supply voltage is reduced, the difference between the applicable gate voltage and the threshold voltage becomes smaller, and the transistor drive current cannot be obtained.

[0006]

In the above-mentioned conventional semiconductor integrated circuit, the threshold voltage of the MOS field-effect transistor is reduced in order to keep the operating speed from decreasing when the power supply voltage is reduced. However, when the threshold voltage is reduced in a conventional semiconductor integrated circuit using a MOS field-effect transistor, there is a problem that a standby current passing from the power supply side to the ground side becomes extremely large as shown in FIG. The reason is because the components of Sabusure Tsu Shorudoriku current of the MOS-type field effect transistor can not be ignored. Due to this restriction, it is very difficult to reduce the absolute value of the threshold voltage to, for example, 0.4 V or less in a normal semiconductor integrated circuit.

In view of the above problems, the present invention can drive a MOS field effect transistor under a low power supply voltage,
It is an object of the present invention to provide a semiconductor integrated circuit that can reduce a standby current.

[0008]

The semiconductor integrated circuit of the present invention SUMMARY OF] includes a data holding circuit for holding the data given in synchronization with a clock signal, a logic gate circuit formed of MOS transistors performing a logical operation, the data Retention times
Power supply line for supplying power to the circuit and the logic gate circuit.
And in the to the logic gate circuit on the basis of the control signal
The supply or stop of power supply from the power supply line have a switching circuit for performing the scan based on the control signal
The switching circuit switches the data
After the data holding circuit holds the data, the data holding circuit
Clock signal is stopped and data is read into
After a predetermined time, the power supply to the logic gate circuit is
When stopping and shifting to the operating state, the logic gate circuit
After a predetermined time from the start of power supply to the
And outputting data from the data holding circuit when the data is supplied.
The sub-threshold of the logic gate circuit in the idle state
Suppress the leak current .

The switching circuit is a MOS type field effect transistor, and the control signal makes the MOS type field effect transistor conductive and inactive when activating the logic gate circuit. In this case, it is preferable to make the MOS field effect transistor non-conductive. Further, a bipolar transistor may be used instead of the MOS field effect transistor.

[0010]

When the logic gate circuit is not activated, the switching circuit is turned off. The non-conductive switching circuit prevents the standby current from flowing from the power supply through the inactive logic gate circuit.

[0011]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the semiconductor device of the present invention, FIG. 2 is a circuit diagram showing a logic gate circuit in the embodiment of FIG. 1 in detail, and FIG. 3 explains the operation of the embodiment of FIG. It is a timing chart for performing. In this embodiment, the semiconductor integrated circuit also includes a clock signal CK, as in the case of the semiconductor integrated circuit generally including an asynchronous logic gate circuit and a flip-flop for holding data.
And flip-flops 11 and 12 (hereinafter referred to as FFs 11 and 12) which hold data applied in synchronization with the logic gate circuits 21 and 22 controlled by the cutoff signal CF
It is composed of

Further, the logic gate circuits 21 and 22 correspond to FIG.
, A NAND gate N1 receiving an input signal
And a NAND gate N for receiving an output of the NAND gate N1
2 and a power supply current cutoff element Q that is inserted into a common power supply line for both of the NAND gates N1 and N2, and that cuts off or connects the power supply line in response to the Katoff signal CF.
1 (N-channel MOS transistor). Note that the MOs constituting the NAND gates N1 and N2
The threshold voltage of the S transistor is set to 0.25V, and the threshold voltage of the power supply current cutoff element Q1 is set to 0.7V. Since the power supply current cutoff element Q1 is inserted in the power supply line, the M constituting the NAND gates N1 and N2
Even when the threshold voltage of the OS transistor is reduced to 0.25 V, the standby current is suppressed to a very small value (see the comparison in FIG. 5).

Next, the operation of the above embodiment will be described with reference to FIG. First, a period during which the semiconductor integrated circuit is inactive (time t1 to t2), that is, data is FF11, 1
2 and the logic gate circuits 21 and 22
Is inactive, power supply current cutoff element Q1 is turned off by cutoff signal CF. The power supply current cutoff element Q1 in the non-conductive state allows the logic gate circuit 21,
The standby current of 22 is kept to a very small amount.

At time t2, the power supply current cutoff element Q1 is turned on by the cut-off signal CF and the semiconductor integrated circuit is activated. At a time t3 after a predetermined time, the clock signal CK is supplied to the FFs 11 and 12. FF11,1
2 starts operation. When the operation of the semiconductor integrated circuit is completed at time t4 and the data is held in the FFs 11 and 12, the power supply current cutoff element Q1 is turned off again by the cutoff signal CF at time t5 to suppress the standby current. I do.

That is, after the logic gate circuits 21 and 22 are activated, the data signals are output from the FFs 11 and 12, and the logic operation proceeds. However, when the semiconductor integrated circuit transitions to the sleep state, first, the FFs 11 and 12 enter the data holding state in synchronization with the clock signal, and then the logic gate circuits 21 and 22 operate by the operation of the power supply current cutoff element Q1.
Is cut off.

In general, when the logic gate circuit has a high impedance, the internal potential becomes unstable and the stored data is lost even when the logic gate circuit is connected to only one side of the power supply terminal. However, according to the present embodiment, by the above-described operation, all data is stored in the FFs 11 and 1 even when the power supply current is cut off.
2 and the data being handled is not lost. Further, in the present embodiment, as shown in FIG. 2, one power supply current cutoff element Q1 is assigned to a set of two logic gate circuits 21 and 22,
One power supply current cutoff element may be assigned to each of the logic gate circuits 21 and 22.

Next, a second embodiment of the present invention will be described with reference to FIG. In the present embodiment, the power supply current cutoff element Q of the first embodiment shown in FIGS.
N instead of the N-channel MOS transistor
The PN bipolar transistor Q2 is used. In this case, cutoff signal CF is set to 0 V (transistor Q2 is non-conductive) or 1.2 V (transistor Q2 is conductive and logic gate circuits 21 and 22 are activated). Since the conduction resistance of the bipolar transistor Q2 can be lower than the conduction resistance of the MOS transistor,
Even if the bipolar transistor Q2 is inserted into the power supply line as a power supply current cutoff element, there is an advantage that the influence on the operation of the logic gate circuit can be reduced as compared with the first embodiment.

[0018]

The present invention described above, according to the present invention divides the internal structure of a semiconductor integrated circuit in the logical circuit portion and a data holding circuit portion, with the logic circuit portion is composed of a lower MOS transistor threshold voltage, A power supply current cutoff element is inserted into a power supply line to the logic circuit portion, and only when the data holding circuit portion holds data stably, the supply of power to the logic circuit portion is cut off by the power supply current cutoff device. Thus, there is an effect that a semiconductor integrated circuit in which the operation of the circuit is high-speed and the standby current can be extremely low can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a semiconductor device of the present invention.

FIG. 2 is a circuit diagram showing a logic gate circuit in FIG. 1 in detail.

FIG. 3 is a timing chart for explaining the operation of the embodiment of FIG. 1;

FIG. 4 is a block diagram showing a second embodiment of the semiconductor device of the present invention.

FIG. 5 is a graph illustrating a difference in characteristics between the semiconductor device of the present invention and a conventional example.

[Explanation of symbols]

 11, 12 flip-flop (FF) 21, 22 logic gate circuit N1, N2 NAND gate Q1, Q2 power supply current cutoff element

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03K 19/00-19/23 G06F 1/32

Claims (3)

(57) [Claims] A data holding circuit for holding the data <br/> data given in synchronization with 1. A clock signal, and a logic gate circuit for performing a logic operation is formed from MOS transistors, said de
Power to the data holding circuit and the logic gate circuit
And a power supply line, and a switching circuit based on the control signal to supply or stop of power supply from the power supply line to the logic gate circuit possess the switching circuit based on the control signal, hibernation
The data holding circuit holds the data when
After reading the data, the data
After a predetermined period of time after the
When the power supply to the logic gate circuit is stopped and the operation state transits, the power supply to the logic gate circuit is stopped.
After a predetermined time from the start of the supply, the clock signal is
By outputting data from the data holding circuit,
Sub-threshold of the logic gate circuit in a quiescent state
A semiconductor integrated circuit that suppresses the peak current . 2. The switching circuit is a MOS field effect transistor, and the control signal causes the MOS field effect transistor to be conductive when the logic gate circuit is activated, and to be inactive. 2. The semiconductor integrated circuit according to claim 1, wherein the MOS-type field effect transistor is turned off when the switching is performed. 3. The switching circuit is a bipolar transistor, and the control signal causes the bipolar transistor to be conductive when the logic gate circuit is activated, and causes the bipolar transistor to be non-conductive when the logic gate circuit is inactive. The semiconductor integrated circuit according to claim 1.