JPH05291929A - Semiconductor circuit - Google Patents

Abstract

PURPOSE:To obtain a semiconductor circuit in which the possibility of an inverted output is precluded, stable operation is attained and high speed stability operation is implemented with low power consumption by providing a level hold circuit to an output terminal of a logic circuit so as to hold an output of the logic circuit. CONSTITUTION:In the operation of a logic circuit LC, switches SWH, SWL are closed to confirm an output OUT in response to an input IN, then the switches SWH, SWL are open. Then, a current path from a current source VHH to a source VLL via the logic circuit LC is interrupted and a level hold circuit LH holds an output of the logic circuit LC. On the other hand, the circuit with a large drive capability is used for the circuit LC to attain high speed operation in a short delay time. Furthermore, since no current flows through the circuit LC in the standby state, the current consumption is due to a current flowing through the circuit LH and the circuit LH keeps the output OUT of the circuit LC, then, the circuit is realized in which the possibility of malfunction is precluded, the operation is stable at a high speed with low power consumption.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit, and more particularly to a semiconductor circuit which consumes low power and operates stably at high speed.

[0002]

2. Description of the Related Art CMOS logic circuits are widely used because they have low power consumption and are suitable for high integration. As an example,
A CMOS inverter is shown in FIG. It is composed of an NMOS transistor MN and a PMOS transistor MP.
The input IN is input to the gates of the transistors MN and MP, and the output OUT is obtained at the drains of MN and MP.

1989 International Symposium on VLS Technology,
Systems and Applications, Proceedings of Technical Papers (1989 May 5
Mon) 188 to 192 (1989 International S
ymposium on VLSI Technology, Systems and Applicati
ons, Proceedings of Technical Papers, pp.188-192
(May 1989)), the evolution of CMOS logic circuits has been supported by scaling of MOS devices due to improvements in manufacturing technology. On the other hand, as the breakdown voltage of the gate oxide film is reduced due to this scaling, it is necessary to reduce the operating voltage of the semiconductor device. In addition, in a semiconductor device that needs to be used in a battery-operated portable device or the like, it is necessary to further reduce the operating voltage in order to reduce power consumption. Also,
In order not to reduce the operating speed even if the operating voltage is lowered, in order to secure the driving ability of the transistor,
The threshold voltage of the transistor must be reduced. For example, according to the above document, the channel length is 0.25 μ.
The threshold voltage of a transistor operating at 1.5V at m is expected to be 0.35V. According to a well-known scaling rule, the threshold voltage is proportional to the operating voltage, so if the operating voltage is 1V, the threshold voltage will be about 0.24V.

[0004]

When the threshold voltage is decreased, the subthreshold current of the transistor which is turned off increases. For example, in FIG. 8, when the input IN is at the high level VHH, the PMOS transistor MP is off because both the gate and the source are VHH, but when the threshold voltage of MP is small, a subthreshold current flows. At this time, since the NMOS transistor MN is on, the subthreshold current of MP is equal to the first power supply voltage V
A through current flows from HH to the second power supply voltage VLL.
However, since the ON resistance of MN is sufficiently small, the output OUT does not become high level due to the subthreshold current of MP. Thus, the subthreshold current of the transistor does not make the signal output operation of the static circuit unstable. In addition, the subthreshold current is generally smaller than the current that charges and discharges the load capacitance connected to the output terminal OUT, and has a small effect on the consumption current during operation. However, it is described in the above-mentioned document that power consumption due to a through current is a problem in a device that operates on a battery and remains in a standby state for a long time. Extended Abstracts of the 1991 International Conference on Solid State Devices and Materials (August 1991) 468-471 (Extended Abstracts of the
1991 International Conference on Solid State Devic
es and Materials, pp.468-471 (Aug. 1991)), the minimum threshold voltage of the peripheral circuit transistor of the battery-operated CMOS DRAM is 0.22 V or more,
Furthermore, considering the manufacturing variations, the value should be about 0.4 V or more. Therefore, since the threshold voltage cannot be scaled, it is impossible to reduce the operating voltage to about 1 V or less by conventional scaling.
In order to reduce the shoot-through current in the standby state, the transistor M
A method in which a switch is inserted in series with N and MP and the switch is turned off during standby to cut off the through current is conceivable. However, in that case, when the switch is turned off, the output terminal OUT becomes in a floating state, so that the output may be inverted due to a leak current or the like, and the operation becomes unstable. The present invention has been made to solve the above problems. That is, it is an object of the present invention to provide a semiconductor circuit which has a small delay time during operation, a high speed, a low through-current does not flow in the standby state, low power consumption, and an output that is stable even in the standby state.

[0005]

A feature of the present invention for achieving the above object is to provide a switch in a path of a through current for a logic circuit in which a through current flows between power supplies in a standby state where an input does not change. In the standby state, the switch is turned off to interrupt the current path flowing through the logic circuit, a level hold circuit is provided at the output terminal of the logic circuit, and the level hold circuit outputs the output of the logic circuit at least while the switch is off. To hold.

[0006]

The effect of the level hold circuit on the delay time is small, and the delay time is determined by the logic circuit. Even if a high-speed circuit having a large driving capability is used as the logic circuit, current does not flow through the logic circuit in the standby state, so the current consumption is only the current flowing through the level hold circuit. Since the level hold circuit only holds the output, it may have a small driving capability, and the current consumption can be reduced. Even if the switch is turned off, since the output of the logic circuit is held by the level hold circuit, there is no risk of the output being inverted, and stable operation is achieved. Therefore, it is possible to realize a semiconductor device with low power consumption and stable operation at high speed.

[0007]

EXAMPLES The present invention will be described below with reference to examples. FIG. 1 shows a conceptual embodiment of the present invention. The logic circuit LC receives the high-potential power line VH via the switches SWH and SWL.
It is connected to H and a low potential power supply line VLL. Logic circuit L
A level hold circuit LH is connected to the output terminal OUT of C. Switches SWH and SWL have control pulse CK
It is controlled by and turns on and off at the same time. The logic circuit LC is
It is composed of a logic gate such as an inverter, a NAND circuit, a NOR circuit, a flip-flop circuit, or a combination of a plurality thereof. The level hold circuit LH can be composed of a positive feedback circuit. The operation of the logic circuit LC is performed by turning on the switches SWH and SWL. After the output OUT according to the input IN of the logic circuit LC is determined, the switch S
WH and SWL are turned off and V via logic circuit LC
The current path from HH to VLL is cut off, and the output of the logic circuit LC is held by the level hold circuit LH. Since the gate input capacitance of the level hold circuit LH is small, the delay time of the circuit is substantially determined by the delay time of the logic circuit LC with little influence by the level hold circuit LH. On the other hand, it is possible to perform a high-speed operation with a short delay time by using a circuit having a large driving capability for the logic circuit LC. Moreover, since no current flows through the logic circuit LC in the standby state, the consumption current is only the current flowing through the level hold circuit LH. Since the level hold circuit LH may have a small driving capability, the current consumption can be reduced. Moreover, since the output OUT of the logic circuit LC is maintained by the level hold circuit LH, there is no risk of malfunction. Therefore, it is possible to realize a circuit that operates stably at high speed with low power consumption. Hereinafter, specific examples of the present invention will be described in more detail.

An embodiment in which the present invention is applied to a CMOS inverter is shown in FIG. NMOS transistors MN1 and P
The MOS transistor MP1 operates as the switches SWL and SWH in FIG. 1, respectively. In order to reduce the leakage current when the logic circuit LC is turned off, the threshold voltage of the transistors MN1 and MP1 is set higher than the threshold voltage of the MOS transistors forming the logic circuit LC. Further, the channel width / channel length of the transistors MN1 and MP1 is set to a value larger than the channel width / channel length of the MOS transistors forming the logic circuit LC so that the ON resistance does not increase. The control pulse CK is input to the gate of the NMOS transistor MN1 and the control pulse CKB is input to the gate of the PMOS transistor MP1. CKB is a complementary signal of the opposite phase of CK. A CMOS inverter INV composed of an NMOS transistor MN2 and a PMOS transistor MP2 as a logic circuit is connected in series to MN1 and MP1 as switches. Also,
The threshold voltage of the transistors MN2 and MP2 of the CMOS inverter INV is set to be small in order to increase the driving ability by the low voltage operation. Also, the output terminal O of the inverter INV
The UT has NMOS transistors MN3, MN4 and PM.
A level hold circuit LH including OS transistors MP3 and MP4 is connected. In order to reduce the shoot-through current while holding the output OUT, the level hold circuit LH
The threshold voltage of the transistors MN3, MN4, MP3, MP4 is set higher than that of the MOS transistors forming the inverter INV, and the channel width / channel length is reduced to reduce power consumption. Numerical examples of power supply voltage and threshold voltage will be given. VLL is ground potential 0V and VHH is external power supply voltage 1V. The threshold voltage of the NMOS transistor is 0.2V for MN2, MN1 and MN3 and MN
4 is 0.4V. The threshold voltage of the PMOS transistor is -0.2V for MP2, MP1 and MP3 and MP.
4 is -0.4V.

The operation of the semiconductor circuit shown in FIG. 2 will be described with reference to the timing chart shown in FIG. First, the control pulse CK is raised to VHH before the level change of the input signal IN, and C
Lowering KB to VLL, switch transistor MN
1, MP1 is turned on and the inverter INV is powered by VH
It is connected to H and the ground potential VLL. Input signal IN is V
By increasing from LL to VHH, the inverter INV
MP2 is turned off, MN2 is turned on, and the output OUT is V
It is discharged from HH to VLL. At this time, the transistor M
N2 starts conducting in the saturation region, and the current value flowing through MN2 is determined by the voltage between the gate (input terminal IN) and the source (node NL). The switch transistor MN1 is the node N
Since it is provided between L and VLL, the potential of the node NL temporarily rises due to the on-resistance of MN1 and the current flowing from MN2. However, since the gate of MN1 is at VHH, the ON resistance can be designed to be sufficiently small even if the threshold voltage is large, and the influence on the delay time can be reduced. Also, output O
When the UT inverts from VHH to VLL, the level hold circuit LH keeps the output OUT at VHH so that MN4
Is off and MP4 is on. Therefore, MN2
Is turned on, a through current flows from VHH to VLL through MP4 and MN2.
By designing the driving capability of No. 4 small, it is possible to reduce the influence on the delay time and current consumption. Since the drive capacity of the inverter is larger than the drive capacity of the level hold circuit LH, the output OUT decreases in response to the increase of the input IN, so that MN3 of the level hold circuit LH is turned off and MP3 is turned on. The node NLH in the level hold circuit is inverted from VLL to VHH, MN4 is turned on and MP4 is turned off, the level hold circuit LH operates so as to keep the output OUT at VLL, and the through current stops flowing. In addition, the inverter INV
MP2 is off because its gate and source are both VHH, but its threshold voltage is small, so in this state, a large leak current flows and a through current flows through the inverter INV. Then, the control pulse CK is lowered to VLL, CKB is raised to VHH, the switch transistors MN1 and MP1 are turned off, and the inverter INV is separated from the power source VHH and the ground potential VLL. At this time, MN
1, MP1 is completely turned off because the gate and the source have the same potential and the threshold voltage is large. However, the output OUT can be kept at VHH by the positive feedback operation of the level hold circuit LH. At this time, since the NMOS transistor MN2 is turned on, the node NL is kept at VLL by the level hold circuit LH. On the other hand, due to the leakage current of the PMOS transistor MP2 from the node NH to the output terminal OUT, the voltage of the node NH starts to drop due to the influence of the low level output of the level hold circuit LH. Therefore, MP2 has a source potential lower than the gate potential and is completely turned off. As a result, the inverter INV in the standby state
Through current does not flow. Then, before the input signal IN changes, the control pulse CK is again raised to VHH and CKB is lowered to VLL, and the switch transistors MN1 and MP are
1 is turned on to bring the node NH to VHH. Input IN
Is inverted from VHH to VLL, the output OUT is inverted from VLL to VHH, contrary to the previous operation. still,
It is desirable that the level hold circuit LH quickly follow the output OUT so that the period in which the through current flows through the inverter INV and the level hold circuit LH is shortened. Therefore, the inverter INV and the level hold circuit LH are arranged close to each other to reduce the wiring delay. As is apparent from the embodiment described with reference to FIGS. 2 and 3, the threshold voltage of the MOS transistors MN1 and MP1 used as switches is about 0.4 V which is conventionally required to reduce the subthreshold current. With the above configuration, the MOS in the logic circuit is not increased without increasing the shoot-through current in the standby state.
The threshold voltage of the transistors MN2 and MP2 can be reduced. Even if the operating voltage is lowered to 1 V or less, the driving capability can be secured by setting the threshold voltage of the MOS transistors MN2 and MP2 to 0.25 V or less. Therefore, low power consumption can be realized by lowering the voltage. Also, based on the conventional scaling law, performance improvement due to element scaling can be realized. Moreover, except for loading the switch and the level hold circuit, the conventional CMO
Since it has the same configuration as the S logic circuit, it is possible to use the same design method as the conventional one.

FIG. 4 shows another embodiment in which the present invention is applied to a CMOS inverter chain. An inverter chain can be realized by connecting the configuration in which two switches and a level hold circuit are provided to the single-stage inverter shown in FIG. 2 in multiple stages, but in the present embodiment, the switch and the level hold circuit are shared by a plurality of inverters. In this example, the number of elements and the area are reduced. Here, the case of a four-stage inverter chain is taken as an example, but the case of other numbers of stages is similarly configured. Four inverters INV1, INV2, INV3
INV4 is connected in series. Final stage inverter INV
The level hold circuit LH is connected to the output terminal OUT of No. 4. Each inverter is composed of one PMOS transistor and one NMOS transistor having the same threshold and channel width / channel length as INV in FIG. Unlike this, the transistor size (channel width / channel length) of each inverter may be the same or different. As often used as a driver, the channel length is the same and the channel width is set to INV between certain stages.
It is also possible to increase in the order of 1, INV2, INV3, INV4. The source of the PMOS transistor of each inverter is connected to the node NH, and the source of the NMOS transistor of each inverter is connected to the node NL. Node N
The switch SWL is connected between L and the low level power supply VLL,
A switch S is provided between the node NH and the high level power source VHH.
WH is provided. The switches SWL and SWH are controlled by the control pulse CK and are turned on and off at the same time. As shown in FIG. 2, the switch SWL is an NMOS transistor, and SWH is a PMO in which a complementary signal of CK is input to the gate.
It is realized by S-transistor. The operation of the inverter chain is performed by turning on the switches SWL and SWH. For example, when the input IN is inverted from the low level VLL to the high level VHH, the inverter INV1 causes the node N1 to reach VH.
Invert from H to VLL, and the node N2 becomes V by INV2
It is inverted from LL to VHH, the node N3 is inverted from VHH to VLL by INV3, and the output terminal O by INV4.
UT flips from VLL to VHH. When OUT is set to VHH, the level hold circuit LH sets OUT to VHH.
Works to keep on. In standby state, switch SW
By turning off L and SWH, the current path from VHH to VLL via the inverter is cut off. When the present invention is applied to the inverter chain, it is sufficient to provide the level hold circuit only at the output terminal by treating the inverter chain as one logic circuit as a whole as in the present embodiment. Further, the switches SWL and SWH can be shared by a plurality of inverters. The sizes of the switches SWL and SWH are determined by the size of the peak current that flows. The peak of the sum of the currents flowing through the plurality of inverters is smaller than the sum of the peak currents of the respective inverters. For example, when an inverter chain is configured with an interstage ratio of 3, the peak of the current sum is almost the same as the peak current of the final stage.
Therefore, it is better to share a switch among multiple inverters than to provide a switch for each inverter.
The switch area is small.

FIG. 5 shows another embodiment in which the present invention is applied to an inverter chain. Similar to FIG. 4, the case of an inverter chain of four stages is taken as an example, but the configuration is similar for other stages. 4 inverters INV1, IN
V2, INV3, INV4 are connected in series. Level hold circuits LH3 and LH4 are connected to a node N3 which is an output terminal of the inverter INV3 and an input terminal of INV4 and an output terminal OUT of INV4, respectively. Each inverter is composed of one PMOS transistor and one NMOS transistor, similar to INV in FIG. The odd-numbered inverters INV1 and INV3 have nodes NL1 and N
To H1, the even-numbered inverters INV2 and INV4 are connected to the nodes NL2 and NH2. Nodes NL1, N
Switches SWL1 and SWL2 are connected between L2 and the low level power supply VLL, and switches SWH1 and SW are connected between the nodes NH1 and NH2 and the high level power supply VHH, respectively.
WH2 is provided. Switches SWL1, SWL2 and S
WH1 and SWH2 are controlled by a control pulse CK and are turned on and off at the same time. The operation of the inverter is switch S
This is performed by turning on WL1, SWL2, SWH1, and SWH2. For example, when the input IN is low level VLL to high level V
When inverted to HH, the node N1 changes from VHH to VLL,
Node N2 goes from VLL to VHH, node N3 goes to VHH
To VLL, the output terminal OUT is VLL by INV4
To VHH. When N3 is determined to be VLL, the level hold circuit LH1 operates to keep N3 at VLL. When OUT is set to VHH, the level hold circuit LH operates to keep OUT at VHH. In the standby state, the switches SWL1, SWL2,
By turning off SWH1 and SWH2, the current path from VHH to VLL via the inverter is cut off.
At this time, since the node N3 is kept at the low level VLL by the level hold circuit LH3, the node NL1 is also kept at VLL through the inverter INV3. Further, the node N1 is kept at VLL through the inverter INV1. Similarly, the output terminal OUT has a level hold circuit LH.
By being kept at the high level VHH by 4, the nodes NH2 and N2 are also kept at VHH. Therefore, the nodes N1, N2, N3 connecting the inverters are maintained at either VHH or VLL. As described above, two sets of switches are provided, the odd-numbered inverter and the even-numbered inverter are connected to different switches, and one output terminal of the odd-numbered inverter and one output terminal of the even-numbered inverter are connected. To the nodes N1, N2, N between the inverters by connecting level hold circuits to
All three are kept at either high or low level. Even if the standby state continues for a long time, the input of the inverter does not reach the intermediate level, so that the operation is stable, and there is no fear that information will be inverted or a through current will flow when the switch is turned on.

The present invention has been described above with reference to the embodiments applied to the CMOS inverter and the inverter chain, but it is said that a switch and a level hold circuit are added to the logic circuit to perform stable operation at high speed with low power consumption. The present invention is not limited to the embodiments described above without departing from the spirit of the present invention.

For example, another embodiment in which the present invention is applied to a CMOS inverter is shown in FIG. In the embodiment shown in FIG. 2, the transistors MN1 and MP operating as switches
2 is provided between the CMOS inverter INV and the power supplies VLL and VHH. On the other hand, in this embodiment, the NMO
It is provided between the S transistor and the PMOS transistor. Two NMOS transistors MN2 and MN1 and two PMOS transistors MP1 and MP2 are connected in series between a low level power source VLL and a high level power source VHH. The NMOS transistor MN1 and the PMOS transistor MP1 operate as switches. To reduce the leakage current when turned off, the transistor MN
1, the threshold voltage of MP1 is increased. A control pulse CK is applied to the gate of the NMOS transistor MN1 by PMO.
The control pulse CKB of the complementary signal of CK is input to the gate of the S transistor MP1. NMOS transistor M
The gates of the N2 and the PMOS transistor MP2 are connected to the input terminal IN and operate as a CMOS inverter. The threshold voltage of the transistors MN1 and MP1 is set to be small in order to increase the driving capability by the low voltage operation. To the output terminal OUT, the level hold circuit LH configured similarly to FIG. 2 is connected. The operation is performed in the same manner as the embodiment shown in FIG. The control pulses CK and CKB turn on the transistors MN1 and MP1 to turn on the transistor M.
N2 and MP2 are operated as a CMOS inverter.
For example, when the input IN is low level VLL to high level VHH
When it is turned off, the transistor MN that was off until then
2 starts to conduct and operates in the saturation region. At this time, the current value of MN2 is determined by the gate-source voltage. In this embodiment, since the transistor MN1 is provided between the MN2 and the output terminal OUT, the switch transistor MN is provided.
The ON resistance of 1 is connected to the drain of the logic transistor MN2. Therefore, the influence of the ON resistance of MN1 on the current value of MN2 is small. After the output OUT is determined, the transistors MN1 and MP1 are turned off to prevent a through current, and the level hold circuit LH maintains the output OUT. When the switch is inserted on the output terminal side of the logic circuit as in this embodiment, the switch cannot be shared by a plurality of logic gates, but the on resistance of the switch has a small effect. When the transistors used as switches are the same, the delay time becomes shorter than when the switch is provided on the power supply side of the logic circuit as in the embodiment shown in FIG. Alternatively,
If the delay time is designed to be the same, the transistor used as a switch can have a small channel width / channel length and its area can be reduced.

FIG. 7 shows another configuration example of the level hold circuit LH. This level hold circuit LH is provided with NMOS transistors MN3, MN4 and P in the embodiment shown in FIG.
A case where the level hold circuit LH configured by the MOS transistors MP3 and MP4 is used instead will be described. This level hold circuit LH of FIG. 7 has three NMOS transistors MN3, MN4 and M, respectively.
It is composed of N5 and PMOS transistors MP3, MP4 and MP5. To reduce the leakage current in the standby state,
The threshold voltage of each transistor is increased. For example,
The NMOS transistor is 0.4V and the PMOS transistor is -0.4V. MN3 and MP3 form an inverter, and MN4, MN5, MP4 and MP5 form a switching inverter. The control pulse CKB is input to the gate of MN5, and the control pulse CK is input to the gate of MP5. The operation timing is the same as that when the level hold circuit LH shown in FIG. 2 is used, and is as shown in FIG. The control pulse CK is raised to the high level VHH, CKB is lowered to the low level VLL, and the inverter IN
Operate V. At this time, the level hold circuit LH
The transistors MN5 and MP5 are turned off. for that reason,
When the output OUT is inverted, a through current does not flow through the inverter INV and the level hold circuit LH, and the delay time and current consumption can be reduced. In the standby state, the control pulse CK is lowered to the low level VLL, CKB is raised to the high level VHH, and the inverter INV is switched to the power source VL.
Separate from L and VHH. At this time, the transistors MN5 and MP5 are turned on in the level hold circuit, and the output OUT is held by positive feedback. As described above, by configuring the level hold circuit by the combination of the inverter and the switching inverter, the number of transistors is increased by two, but the logic circuit and the level hold circuit do not conflict with each other, and the delay time and current consumption can be reduced. Further, the drive capability of the level hold circuit may be increased, and stable operation can be performed without fear of fluctuation of the output even when the leakage at the output terminal is large.

[0015]

As is apparent from the embodiments described above,
For a logic circuit in which a through current may flow between power supplies in the standby state where the input does not change, a switch is provided in the path of the through current, and in the standby state, the switch is turned off to cut off the current path flowing through the logic circuit. By providing a level hold circuit at the output terminal of the logic circuit and holding the output of the logic circuit by the level hold circuit at least while the switch is off, a semiconductor circuit that realizes stable operation at high speed with low power consumption is realized. it can.

[Brief description of drawings]

FIG. 1 is a diagram showing a conceptual embodiment of the present invention.

FIG. 2 is a circuit diagram of an embodiment in which the present invention is applied to a CMOS inverter.

FIG. 3 is an operation timing chart of an embodiment in which the present invention is applied to a CMOS inverter.

FIG. 4 is a diagram showing an embodiment in which the present invention is applied to an inverter chain.

FIG. 5 is a diagram showing another embodiment in which the present invention is applied to an inverter chain.

FIG. 6 is a diagram showing another embodiment in which the present invention is applied to a CMOS inverter.

FIG. 7 is a circuit diagram of another configuration example of the level hold circuit according to the present invention.

FIG. 8 is a diagram showing a conventional CMOS inverter.

[Explanation of symbols]

LC ... Logic circuit, SWL, SWH, SWL1, SWL
2, SWH1, SWH2 ... Switch, LH, LH3, L
H4 ... Level hold circuit, VHH ... High level power supply,
VLL ... low level power supply, CK ... control pulse, CKB ...
Control pulse which is a complementary signal of CK, IN ... input, OUT
... Output, INV, INV1, INV2, INV3, IN
V4 ... Inverter, MN, MN1, MN2, MN3, M
N4, MN5 ... NMOS transistor, MP, MP1,
MP2, MP3, MP4, MP5 ... PMOS transistor

Claims (14)

[Claims] 1. A logic circuit capable of allowing a through current to flow in a standby state where the input does not change, a switch provided in a path of the through current, and a level hold circuit provided at an output terminal of the logic circuit. In the standby state, the switch is turned off to interrupt the path, and the level hold circuit holds the potential of the output terminal of the logic circuit while the switch is off. .. 2. The semiconductor circuit according to claim 1, wherein the logic circuit is composed of a combination of an NMOS transistor and a PMOS transistor. 3. The semiconductor circuit according to claim 1, wherein the operating voltage of the logic circuit is 1 V or less. 4. The semiconductor circuit according to claim 3, wherein absolute values of threshold voltages of the NMOS transistor and the PMOS transistor are 0.25 V or less. 5. The semiconductor circuit according to claim 1, wherein the switch is provided between a high level power supply and the logic circuit and between a low level power supply and the logic circuit. Semiconductor circuit. 6. The semiconductor circuit according to claim 1, wherein the logic circuit is divided into a high level power supply side circuit and a low level power supply side circuit from the output terminal, and the output terminal and the high level side are provided. The semiconductor circuit, wherein the switch is provided between the output circuit and the circuit on the low level side and between the output circuit and the circuit on the low level side. 7. The semiconductor circuit according to claim 3, wherein the switch provided on the low level power supply side is an NMOS transistor, and the switch provided on the high level power supply side is a PMOS transistor. , Above N
A semiconductor circuit characterized in that complementary control pulses are input to the gates of a MOS transistor and a PMOS transistor. 8. The semiconductor circuit according to claim 7, wherein an NMOS transistor and a PM that operate as the switch are provided.
A semiconductor circuit, wherein the absolute value of the threshold voltage of the OS transistor is 0.4 V or more. 9. The semiconductor circuit according to claim 1, wherein the level hold circuit is a positive feedback circuit. 10. The semiconductor circuit according to claim 6, wherein:
The semiconductor circuit characterized in that the level hold circuit operates as a positive feedback circuit only while the switch is off. 11. The semiconductor circuit according to claim 1, wherein:
A semiconductor circuit, wherein the logic circuit is configured to include a plurality of logic gates, and the switch is commonly provided to the plurality of logic gates. 12. The semiconductor circuit according to claim 8,
A semiconductor circuit, wherein outputs of the plurality of logic gates sharing the switch have the same value. 13. The semiconductor circuit according to claim 1, wherein:
A semiconductor circuit characterized in that the logic circuit is configured by connecting a plurality of logic gates in series, and the level hold circuit is connected only to an output terminal of a final-stage logic gate. 14. The semiconductor circuit according to claim 1, wherein:
The logic circuit is configured by connecting a plurality of logic gates in series, and the output terminal of the last-stage logic gate and the output terminal of any other logic gate that outputs a value different from that of the last-stage logic gate are respectively described above. A semiconductor circuit to which a level hold circuit is connected.