JP2001016093A - Semiconductor circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a table semiconductor circuit, whose delay time at the time of an operation is small, the speed is fast, in which a through-current does not flow and power consumption is small in a standby state and output is kept even in the standby state by turning off a switch installed in the path of the through-current in the standby state and interrupting the path. SOLUTION: A logic circuit LC is connected to a power line VHH of high potential and a power line VLL of low potential via switches SWH and SWL. A level-holding circuit LH is connected to the output terminal 'OUT' of the logic circuit LC. The switches SWH and SWL are controlled by a control pulse and are simultaneously turned on/off. The logic circuit LC is operated by turning on the switches SWH and SWL. After an output 'OUT' corresponding to the input IN of the logic circuit LC is decided according to the input IN of the logic circuit L, the switches SWH and SWL are turned off. Then, a current path to the power line VLL from the power line VHH via the logic circuit LC is interrupted, and the output of the logic circuit LC is held by the level holding circuit LH.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor circuit,
In particular, the present invention relates to a semiconductor circuit that performs stable operation at high speed with low power consumption.

[0002]

2. Description of the Related Art CMOS logic circuits are widely used because they have low power consumption and are suitable for high integration. As an example,
FIG. 8 shows a CMOS inverter. It comprises an NMOS transistor MN and a PMOS transistor MP.
The input IN is input to the gates of the transistors MN and MP, and the output OUT is obtained at the drains of MN and MP.

[0003] 1989 International Symposium on VLSI Technology,
Systems and Applications, Proceedings of Technical Papers, May 1989
Mon.) 188 to 192 (1989 International S
ymposium on VLSI Technology, Systems and Applicati
ons, Proceedings of Technical Papers, pp.188-192
(May 1989)), the development of CMOS logic circuits has been supported by scaling of MOS devices due to improvements in manufacturing technology.

On the other hand, as the breakdown voltage of the gate oxide film decreases due to this scaling, it is necessary to lower the operating voltage of the semiconductor device. In a semiconductor device that needs to be used in a battery-operated portable device or the like, it is necessary to further reduce the operating voltage in order to reduce power consumption.

In order to prevent the operating speed from decreasing even when the operating voltage is reduced, the threshold voltage of the transistor must be reduced in order to ensure the driving capability of the transistor.

For example, according to the above document, the threshold voltage of a transistor that operates at 1.5 V with a channel length of 0.25 μm is expected to be 0.35 V. According to a well-known scaling rule, the threshold voltage is proportional to the operating voltage. Therefore, if the operating voltage is 1 V, the threshold voltage is 0.2
It becomes about 4V.

[0007]

As the threshold voltage is reduced, the subthreshold current of a transistor that is turned off increases. For example, in FIG. 8, when the input IN is at the high level VHH, the PMOS transistor MP is off because both the gate and the source are at VHH, but if the threshold voltage of MP is small, a subthreshold current flows. At this time, since the NMOS transistor MN is on, the sub-threshold current of MP becomes the first power supply voltage V
The through current flows from HH to the second power supply voltage VLL.
However, since the ON resistance of MN is sufficiently small, the output OUT does not become high due to the subthreshold current of MP. Thus, the sub-threshold current of the transistor does not make the signal output operation of the static circuit unstable. In addition, the subthreshold current is generally smaller than the current for charging and discharging the load capacitance connected to the output terminal OUT, and has a small effect on the current consumption during operation.

However, it is described in the above-mentioned document that power consumption due to through current becomes a problem in an apparatus which operates on a battery and the standby state continues for a long time. Extended Abstracts of the 1991 International Conference on Solid State Devices and Materials (August 1991) No. 46
8 to 471 (Extended Abstracts of the 1991
International Conference on Solid State Devices a
According to nd Materials, pp. 468-471 (Aug. 1991), the minimum value of the threshold voltage of the transistor for the peripheral circuit of the battery-operated CMOS DRAM is 0.22 V or more, and the variation in the production is expected. And the value must be about 0.4 V or more. Therefore, since the threshold voltage cannot be scaled, it is impossible to reduce the operating voltage to about 1 V or less by conventional scaling.

In order to reduce the through current in the standby state, a method of inserting a switch in series with the transistors MN and MP and turning off the switch in the standby state to cut off the through current may be considered. However, in this case, when the switch is turned off, the output terminal OUT is in a floating state, and the output may be inverted due to a leak current or the like, and the operation becomes unstable.

The present invention has been made to solve the above problems. That is, an object of the present invention is to provide a semiconductor circuit which has a small delay time in operation, has a high speed, does not flow through current in a standby state, consumes low power, and maintains a stable output even in a standby state.

[0011]

A feature of the present invention to achieve the above object is that a switch is provided in a path of a through current in a logic circuit in which a through current flows between power supplies in a standby state in which an input does not change. In a standby state, the switch is turned off to cut off a current path flowing through the logic circuit, a level hold circuit is provided at an output terminal of the logic circuit, and the output of the logic circuit is output by the level hold circuit at least while the switch is off. Is to hold.

The delay time is less affected by the level hold circuit and is determined by the logic circuit. Even if a high-speed circuit having a large driving capability is used for the logic circuit, current does not flow through the logic circuit in the standby state, so that the current consumption is only the current flowing through the level hold circuit. Since the level hold circuit only holds the output, the driving capability may be small, and the current consumption can be reduced. Even when the switch is turned off, the output of the logic circuit is held by the level hold circuit, so that there is no possibility that the output is inverted and the operation is stable. Therefore, a semiconductor device that performs stable operation at high speed with low power consumption can be realized.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments.

FIG. 1 shows a conceptual embodiment of the present invention. The logic circuit LC is connected to the high-potential power supply line VHH and the low-potential power supply line VLL via the switches SWH and SWL.

A level hold circuit LH is connected to the output terminal OUT of the logic circuit LC. Switches SWH and S
WL is controlled by a control pulse CK, and is turned on and off at the same time.

The logic circuit LC is composed of logic gates and flip-flop circuits such as inverters, NAND circuits and NOR circuits, or a combination of a plurality of them. The level hold circuit LH can be constituted by a positive feedback circuit.

The operation of the logic circuit LC is performed by turning on the switches SWH and SWL. After the output OUT corresponding to the input IN of the logic circuit LC is determined, the switches SWH and S
WL is turned off, and VHH to V
The current path to LL is cut off, and the output of the logic circuit LC is held by the level hold circuit LH.

The delay time of the circuit is the level hold circuit L
Since the gate input capacitance of H is small, the level hold circuit LH has almost no effect and the logic circuit LC
Is determined by the delay time. On the other hand, a high-speed operation with a short delay time can be performed by using a circuit having a large driving capability for the logic circuit LC. Further, in the standby state, no current flows through the logic circuit LC, so that the consumed current is only the current flowing through the level hold circuit LH. Since the level hold circuit LH has a small driving capability, the current consumption can be reduced. Moreover, since the output OUT of the logic circuit LC is maintained by the level hold circuit LH, there is no possibility of malfunction. Therefore, a circuit that performs stable operation at high speed with low power consumption can be realized.

Hereinafter, specific embodiments of the present invention will be described in more detail.

FIG. 2 shows an embodiment in which the present invention is applied to a CMOS inverter. NMOS transistors MN1 and P
The MOS transistor MP1 operates as the switches SWL and SWH in FIG. 1, respectively. In order to reduce the leakage current when the logic circuit LC is turned off, the threshold voltages of the transistors MN1 and MP1 are set higher than the threshold voltages of the MOS transistors forming the logic circuit LC. Further, the channel width / channel length of the transistors MN1 and MP1 is set to a value larger than the channel width / channel length of the MOS transistors forming the logic circuit LC so that the ON resistance does not increase. The control pulse CK is input to the gate of the NMOS transistor MN1, and the control pulse CKB is input to the gate of the PMOS transistor MP1. CKB is a complementary signal of the opposite phase of CK.

An NMOS transistor MN as a logic circuit
2 and a CMOS inverter INV composed of a PMOS transistor MP2 are connected in series to MN1 and MP1 as switches. Further, in order to increase the driving capability at low voltage operation, the transistor MN of the CMOS inverter INV is used.
2. The threshold voltage of MP2 is reduced.

The output terminal OUT of the inverter INV is connected to a level hold circuit LH composed of NMOS transistors MN3 and MN4 and PMOS transistors MP3 and MP4. In order to reduce the through current while holding the output OUT, the threshold voltages of the transistors MN3, MN4, MP3 and MP4 of the level hold circuit LH are made larger than those of the MOS transistors forming the inverter INV, and the channel width / Reduce channel length and power consumption. Numerical examples of the power supply voltage and the threshold voltage will be described. VLL is set to the ground potential 0V, and VHH is set to the external power supply voltage 1V. The threshold voltage of the NMOS transistor is 0.2 V for MN2, and 0.4 V for MN1, MN3 and MN4. The threshold voltage of the PMOS transistor is -0.2 V for MP2, and -0.4 V for MP1, MP3 and MP4.

The operation of the semiconductor circuit shown in FIG. 2 will be described with reference to the timing chart shown in FIG. First, prior to the level change of the input signal IN, the control pulse CK is raised to VHH,
KB is reduced to VLL, and switch transistor MN
1, MP1 is turned on, and the inverter INV is connected to the power supply VH
H and the ground potential VLL. When the input signal IN is V
By rising from LL to VHH, the inverter INV
Is turned off, MN2 is turned on, and the output OUT becomes V
Discharged from HH to VLL. At this time, the transistor M
N2 starts conducting in the saturation region, and the value of the current flowing through MN2 is determined by the voltage between the gate (input terminal IN) and the source (node NL). Switch transistor MN1 is connected to node N
Since it is provided between L and VLL, the potential at the node NL temporarily rises due to the ON resistance of MN1 and the current flowing from MN2. However, since the gate of MN1 is at VHH, the on-resistance can be designed to be sufficiently small even if the threshold voltage is large, and the effect on the delay time can be reduced.

When the output OUT is inverted from VHH to VLL, the level hold circuit LH turns off MN4 and turns on MP4 so as to keep the output OUT at VHH. Therefore, when MN2 is turned on, a through current flows from VHH to VLL through MP4 and MN2. However, the influence on delay time and current consumption can be reduced by designing the driving capability of MP4 smaller than that of MN2. it can.

Since the driving capability of the inverter is larger than that of the level hold circuit LH, the input IN
In response to the rise of the output OUT, the output OUT decreases, the MN3 of the level hold circuit LH turns off, the MP3 turns on, the node NLH in the level hold circuit inverts from VLL to VHH, the MN4 turns on, and the MP4 When turned off, the level hold circuit LH operates to keep the output OUT at VLL, and no through current flows.

The MP2 of the inverter INV is off because both the gate and the source are VHH. However, since the threshold voltage is small, a leak current is large and a through current flows through the inverter INV in this state. Then, the control pulse CK is lowered to VLL, and CKB is changed to VHH.
, The switch transistors MN1 and MP1 are turned off, and the inverter INV is connected to the power supply VHH and the ground potential V
Separate from LL. At this time, the gates and sources of MN1 and MP1 are equipotential, and the threshold voltage is large, so that MN1 and MP1 are completely turned off. However, the output OUT can be kept at VHH by the positive feedback operation of the level hold circuit LH. At this time, since the NMOS transistor MN2 is on, the node NL is connected to the VL by the level hold circuit LH.
L is maintained. On the other hand, due to the leakage current of the PMOS transistor MP2 from the node NH to the output terminal OUT, the voltage of the node NH starts to decrease under the influence of the low-level output of the level hold circuit LH. Therefore, the source potential of MP2 falls below the gate potential and is completely turned off. As a result, the through current of the inverter INV does not flow in the standby state. Then, before the input signal IN changes, the control pulse CK is again raised to VHH, CKB is lowered to VLL, the switch transistors MN1 and MP1 are turned on, and the node NH is set to VHH. Input IN changes from VHH to VLL
, The output OUT is inverted from VLL to VHH, contrary to the previous operation.

It is desirable that the level hold circuit LH quickly follows the output OUT so that the period during which a through current flows through the inverter INV and the level hold circuit LH is shortened. Therefore, the inverter INV and the level hold circuit LH are arranged close to each other to reduce wiring delay.

As is clear from the embodiment described with reference to FIGS. 2 and 3, the MOS transistor M used as a switch
If the threshold voltages of N1 and MP1 are set to about 0.4 V or more which is conventionally required to reduce the sub-threshold current, the through current in the standby state is not increased, and
The threshold voltages of the MOS transistors MN2 and MP2 in the logic circuit can be reduced. Even if the operating voltage is lowered to 1 V or less, the MOS transistors MN2, MP
The driving capability can be ensured by setting the threshold voltage of No. 2 to 0.25 V or less. Therefore, it is possible to realize low power consumption due to the low voltage. In addition, the performance can be improved by scaling the elements based on the conventional scaling rule. Moreover, since the configuration is the same as that of the conventional CMOS logic circuit except that a switch and a level hold circuit are loaded, the same design method as that of the conventional CMOS logic circuit can be used.

FIG. 4 shows another embodiment in which the present invention is applied to a CMOS inverter chain. An inverter chain can be realized by connecting the configuration in which two switches and a level hold circuit are provided to the one-stage inverter shown in FIG. 2 in multiple stages. However, in this embodiment, the switch and the level hold circuit are shared by a plurality of inverters. This is an example in which the number of elements and the area are reduced. Here, the case of a four-stage inverter chain is taken as an example, but the same applies to the case of other stages. Four inverters INV1, INV2, INV3,
INV4 is connected in series. Last stage inverter INV
4 is connected to the level hold circuit LH. Each inverter is composed of one PMOS transistor and one NMOS transistor having the same threshold value and channel width / channel length as INV in FIG. On the other hand, the transistor size (channel width / channel length) of each inverter may be the same or different. As is often used as a driver, the channel width is set to INV between certain stages with the same channel length.
1, INV2, INV3, and INV4 can be increased in this order. The source of the PMOS transistor of each inverter is connected to the node NH, and the source of the NMOS transistor of each inverter is connected to the node NL. Node N
The switch SWL is provided between the power supply LLL and the low-level power supply VLL.
Switch S between node NH and high level power supply VHH
WH is provided. The switches SWL and SWH are controlled by a control pulse CK, and are turned on and off at the same time. As shown in FIG. 2, the switch SWL is an NMOS transistor, and SWH is a PMO having a gate to which a complementary signal of CK is input.
It is realized by an S transistor.

The operation of the inverter chain is based on the switch S
This is performed by turning on WL and SWH. For example, when the input IN is inverted from low level VLL to high level VHH, the node N1 is inverted from VHH to VLL by the inverter INV1, the node N2 is inverted from VLL to VHH by INV2, and the node N3 is inverted from VHH to VLL by INV3.
And the output terminal OUT is inverted from VLL to VHH by INV4. When OUT is determined to be VHH, the level hold circuit LH operates to maintain OUT at VHH. In the standby state, the switches SWL and SWH are turned off to change VHH to VLL through the inverter.
Block the current path to

When the present invention is applied to an inverter chain, a level hold circuit may be provided only at its output terminal by treating the inverter chain as one logic circuit as in this embodiment. Further, the switches SWL and SWH can be shared by a plurality of inverters. The size of the switches SWL and SWH is determined by the size of the peak current flowing. The peak of the sum of the currents flowing through the plurality of inverters is smaller than the sum of the peak currents of the inverters. For example, when an inverter chain is configured with an interstage ratio of 3, the peak of the current sum is substantially equal to the peak current of the final stage. Therefore, when a switch is shared by a plurality of inverters, the area of the switch is smaller than when a switch is provided for each inverter.

FIG. 5 shows another embodiment in which the present invention is applied to an inverter chain. Although the case of a four-stage inverter chain is taken as an example similarly to FIG. 4, the case of other stages is similarly configured. Four inverters INV1, INV
V2, INV3, and INV4 are connected in series. Level hold circuits LH3 and LH4 are connected to a node N3 which is an output terminal of the inverter INV3 and an input terminal of the INV4 and an output terminal OUT of the INV4, respectively. Each inverter is composed of one PMOS transistor and one NMOS transistor, similarly to INV in FIG. Odd-numbered inverters INV1 and INV3 are connected to nodes NL1 and N
At H1, even-numbered inverters INV2 and INV4 are connected to nodes NL2 and NH2. Nodes NL1, N
Switches SWL1 and SWL2 are connected between L2 and the low-level power supply VLL, respectively, and switches SWH1 and SWL are connected between the nodes NH1 and NH2 and the high-level power supply VHH, respectively.
WH2 is provided. Switches SWL1, SWL2 and S
WH1 and SWH2 are controlled by a control pulse CK, and are turned on and off at the same time.

The operation of the inverter is determined by the switches SWL1,
SWL2, SWH1 and SWH2 are turned on. For example, when the input IN is inverted from the low level VLL to the high level VHH, the node N1 changes from VHH to VLL,
2 from VLL to VHH, and node N3 from VHH to VL
L, the output terminal OUT changes from VLL to VH by INV4.
H is sequentially inverted. When N3 is determined to be VLL, the level hold circuit LH1 operates to keep N3 at VLL. When OUT is determined to be VHH, the level hold circuit LH operates to maintain OUT at VHH. In the standby state, the switches SWL1, SWL2, SWH1,
By turning off SWH2, the current path from VHH to VLL via the inverter is cut off. At this time,
Since the node N3 is kept at the low level VLL by the level hold circuit LH3, the node NL1 is also connected to the inverter IN
It is kept at VLL through V3. Further, the inverter I
Node N1 is maintained at VLL through NV1. Similarly, when the output terminal OUT is kept at the high level VHH by the level hold circuit LH4, the nodes NH2 and N2 are also kept at VHH. Therefore, nodes N1, N2, N3 connecting the inverters are maintained at either VHH or VLL.

As described above, two sets of switches are provided, the odd-numbered inverter and the even-numbered inverter are connected to different switches, and one of the output terminals of the odd-numbered inverter and one of the even-numbered inverters are connected. By connecting a level hold circuit to the output terminal, the nodes N1, N2, and N3 between the inverters are all maintained at either the high level or the low level. Even if the standby state continues for a long time, the input of the inverter does not reach the intermediate level, so that the inverter operates stably, and there is no possibility that the information is inverted or a through current flows when the switch is turned on.

Although the present invention has been described with reference to the embodiment in which the present invention is applied to a CMOS inverter or an inverter chain, a switch and a level hold circuit are added to a logic circuit to perform high-speed stable operation with low power consumption. Without departing from the spirit of the invention, the invention is not limited to the embodiments described above.

For example, FIG. 6 shows another embodiment in which the present invention is applied to a CMOS inverter. In the embodiment shown in FIG. 2, the transistors MN1 and MP
2 is provided between the CMOS inverter INV and the power supplies VLL and VHH. In contrast, in this embodiment, the NMO
It is provided between the S transistor and the PMOS transistor.

Two NMOS transistors MN2, MN
One and two PMOS transistors MP1 and MP2 are connected in series between a low-level power supply VLL and a high-level power supply VHH. NMOS transistors MN1 and PMOS
The transistor MP1 operates as a switch. In order to reduce the leakage current when turned off, the threshold voltages of the transistors MN1 and MP1 are increased. NMO
A control pulse CK is applied to the gate of the S transistor MN1.
A control pulse CKB of a complementary signal of CK is input to the gate of the PMOS transistor MP1. The gates of the NMOS transistor MN2 and the PMOS transistor MP2 are connected to the input terminal IN, and operate as a CMOS inverter. The threshold voltage of the transistors MN1 and MP1 is reduced in order to increase the driving capability in the low-voltage operation.
The output terminal OUT is connected to a level hold circuit LH configured in the same manner as in FIG.

The operation is performed in the same manner as in the embodiment shown in FIG. The control pulse CK, CKB causes the transistor MN
1, MP1 is turned on, and transistors MN2, MP2
Are operated as CMOS inverters. For example, when the input IN is inverted from the low level VLL to the high level VHH, the transistor MN2 which has been turned off starts to conduct and operates in the saturation region. At this time, the current value of MN2 is determined by the voltage between the gate and the source. In this embodiment, since the transistor MN1 is provided between MN2 and the output terminal OUT, the on-resistance of the switch transistor MN1 is connected to the drain of the logic transistor MN2.
Therefore, the influence of the ON resistance of MN1 on the current value of MN2 is small. After the output OUT is determined, the transistor M
N1 and MP1 are turned off to prevent a through current, and the output OUT is maintained by the level hold circuit LH.

When a switch is inserted on the output terminal side of a logic circuit as in this embodiment, the switch cannot be shared by a plurality of logic gates, but the influence of the on-resistance of the switch is small. When the same transistor is used as the switch, the delay time is shorter than when the switch is provided on the power supply side of the logic circuit as in the embodiment shown in FIG. Alternatively, if the delay time is designed to be the same, the channel width / channel length of the transistor used as a switch can be reduced, and the area can be reduced.

FIG. 7 shows another example of the configuration of the level hold circuit LH. This level hold circuit LH is connected to the NMOS transistors MN3, MN4 and P in the embodiment shown in FIG.
A case will be described in which the level hold circuit LH including the MOS transistors MP3 and MP4 is used instead of the level hold circuit LH.

The level hold circuit LH shown in FIG. 7 includes three NMOS transistors MN3, MN4, M
It comprises N5 and PMOS transistors MP3, MP4, MP5. In order to reduce the leakage current in the standby state,
The threshold voltage of each transistor is increased. For example,
The NMOS transistor is set to 0.4V, and the PMOS transistor is set to -0.4V. MN3 and MP3 constitute an inverter, and MN4, MN5, MP4 and MP5 constitute a switching inverter. The control pulse CKB is input to the gate of MN5, and the control pulse CK is input to the gate of MP5.

The operation timing is the same as that in the case where the level hold circuit LH shown in FIG. 2 is used, and is as shown in FIG. Raise the control pulse CK to a high level VHH,
CKB is lowered to the low level VLL to operate the inverter INV. At this time, in the level hold circuit LH, the transistors MN5 and MP5 are turned off. Therefore, output O
When the UT is inverted, no through current flows through the inverter INV and the level hold circuit LH, so that the delay time and the current consumption can be reduced. In the standby state, the control pulse CK is lowered to the low level VLL, the CKB is raised to the high level VHH, and the inverter INV is switched to the power supplies VLL and VHH.
Disconnect from At this time, in the level hold circuit, the transistors MN5 and MP5 are turned on, and the output OUT is held by positive feedback.

As described above, when the level hold circuit is constituted by the combination of the inverter and the switching inverter, the number of transistors increases by two. However, there is no competition between the logic circuit and the level hold circuit, and the delay time and current consumption are reduced. I can do it. Further, the driving capability of the level hold circuit may be increased, and even if the leakage at the output terminal is large, there is no possibility that the output fluctuates and stable operation can be performed.

[0044]

As is clear from the embodiments described above,
A switch is provided in the path of the through current for a logic circuit in which a through current may flow between the power supplies in the standby state in which the input does not change. In the standby state, the switch is turned off to interrupt the current path flowing through the logic circuit. By providing a level hold circuit at the output terminal of the logic circuit and holding the output of the logic circuit with the level hold circuit at least during the period when the switch is off, a semiconductor circuit that performs stable operation at high speed with low power consumption is realized. it can.

[Brief description of the drawings]

FIG. 1 is a diagram showing a conceptual embodiment of the present invention.

FIG. 2 is a circuit diagram of an embodiment in which the present invention is applied to a CMOS inverter.

FIG. 3 is an operation timing chart of an embodiment in which the present invention is applied to a CMOS inverter.

FIG. 4 is a diagram showing an embodiment in which the present invention is applied to an inverter chain.

FIG. 5 is a diagram showing another embodiment in which the present invention is applied to an inverter chain.

FIG. 6 is a diagram showing another embodiment in which the present invention is applied to a CMOS inverter.

FIG. 7 is a circuit diagram of another configuration example of the level hold circuit according to the present invention.

FIG. 8 is a diagram showing a conventional CMOS inverter.

[Explanation of symbols]

LC: logic circuit, SWL, SWH, SWL1, SWL
2, SWH1, SWH2 ... switch, LH, LH3, L
H4: Level hold circuit, VHH: High-level power supply,
VLL: low-level power supply, CK: control pulse, CKB:
Control pulse which is a complementary signal of CK, IN input, OUT
... Output, INV, INV1, INV2, INV3, IN
V4: Inverter, MN, MN1, MN2, MN3, M
N4, MN5 ... NMOS transistors, MP, MP1,
MP2, MP3, MP4, MP5... PMOS transistors.

Claims (2)

[Claims] A logic circuit capable of outputting a first-level potential or a second-level potential to its output terminal in response to a change in an operating state in which an input changes, and allowing a through current to flow in a standby state in which the input does not change. A switch provided in a path of the through current; and a switch in the standby state, wherein the switch is turned off to cut off the path. 2. The logic circuit according to claim 1, wherein said logic circuit is divided into two circuits centering on said output terminal, wherein a first circuit is located on a first operating potential point side, and a second circuit is located on said first operating potential point. A second operating potential point which is a lower potential, wherein the switch is a first switch between the output terminal and the first circuit, and a second switch between the output terminal and the second circuit. 2. A switch according to claim 1, further comprising a switch.
The semiconductor circuit according to the above.