JP2003264457A - Semiconductor integrated circuit having power reduction mechanism - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high speed/low power consumption semiconductor integrated circuit. <P>SOLUTION: The semiconductor integrated circuit is provided with a first inverter circuit (L<SB>41</SB>), latch circuits (L<SB>42</SB>, L<SB>43</SB>) to be connected with the first inverter circuit (L<SB>41</SB>) and a control circuit means (SC) to be connected with the first inverter circuit (L<SB>41</SB>). The control circuit means (SC) is connected with the first inverter circuit (L<SB>41</SB>), is supplied with a control signal, makes comparatively large current flow to the first inverter circuit (L<SB>41</SB>) by setting the control signal to be supplied to the control circuit means (SC) to a first state, and limits the current that flows to the first inverter circuit (SC) to a value smaller than the comparatively large current by setting the control signal to be supplied to the control circuit means (SC) to a second state different from the first state. The latch circuits (L<SB>42</SB>, L<SB>43</SB>) output a signal at a first level or a second level on the basis of a signal outputted by the first inverter circuit (L<SB>41</SB>) when the control signal is at the first state and outputs the signal at the first level when the control signal is at the second state. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit composed of fine MOS transistors, and more particularly to a circuit suitable for high speed / low power operation.

[0002]

2. Description of the Related Art As described in Non-Patent Document 1,
Since the breakdown voltage of a MOS transistor is reduced as it is miniaturized, its operating voltage must be lowered.
In particular, in a semiconductor device used in a battery-operated portable device or the like, the operating voltage can be further reduced to reduce power consumption.

In this case, in order to maintain high-speed operation, it is necessary to reduce the threshold voltage (V _T ) of the MOS transistor in proportion to the decrease in operating voltage. This is because the operating speed is governed by the effective gate voltage of the MOS transistor, that is, the value obtained by subtracting V _T from the operating voltage, and the higher this value, the higher the speed. For example, according to the above document, the standard value of the threshold voltage of a transistor operating at 1.5 V with a channel length of 0.25 μm is expected to be 0.35 V. According to a well-known scaling rule, if the operating voltage is 1V, the standard value of the threshold voltage is about 0.24V. However, when V _{T is set} to about 0.4 V or less, as described below, due to the subthreshold characteristic (tailing characteristic) of the MOS transistor, it is no longer possible to completely turn off the transistor, and a direct current flows. Occurs. Therefore, in the operation of 1.5 V or less, this current poses a serious problem in practical use.

The conventional CMOS inverter shown in FIG. 49 will be described. Ideally, the N-channel MOS transistor M _N is turned off when the input signal IN is at a low level (= V _SS ), and the P-channel MO transistor is when the input signal IN is at a high level (= V _CC ).
The S-transistor M _P is turned off and no current flows in any case. However, V of MOS transistor
_{When T} becomes low, the subthreshold characteristic cannot be ignored.

As shown in FIG. 50, the drain current I _DS in the subthreshold region is proportional to the exponential function of the gate-source voltage V _GS and is represented by the following equation.

[0006]

[Equation 1]

Where W is the channel width of the MOS transistor, I ₀ and W ₀ are the current value and channel width when defining V _T , and S is the tailing coefficient (the reciprocal of the slope of the V _GS -log I _DS characteristic). is there. Therefore, even if V _GS = 0, the subthreshold current

[0008]

[Equation 2]

Flows. Since the transistor in the off state in the CMOS inverter of FIG. 49 has V _GS = 0, the above current I _L flows from the high power supply voltage V _CC toward the low power supply voltage V _SS which is the ground potential in the non-operating state. Become.

[0010] The sub-threshold current, as shown in FIG. 50, 'Lowering the, I _L from I _L' V _T the threshold voltage from V _T exponentially increases in the.

As is clear from the above equation of Equation 2, in order to reduce the subthreshold current, V _T should be increased or S should be decreased. However, the former causes a decrease in speed due to a decrease in effective gate voltage. In particular, from the viewpoint of breakdown voltage, if the operating voltage is lowered along with the miniaturization, the speed decrease becomes remarkable, and the advantage of miniaturization cannot be utilized, which is not preferable. In addition, the latter is difficult for the following reasons as long as it is assumed to operate at room temperature.

The tailing coefficient S is expressed as follows by the capacitance C _OX of the gate insulating film and the capacitance C _D of the depletion layer under the gate.

[0013]

[Equation 3]

Here, k is the Boltzmann constant, T is the absolute temperature, and q is the elementary charge. As is clear from the above equation, C _OX
S ≥ kT ln 10 / q regardless of whether C _D or C _D , and it is difficult to make it 60 mV or less at room temperature.

Due to the above-mentioned phenomenon, the substantial direct current of the semiconductor integrated circuit composed of a large number of MOS transistors remarkably increases. That is, in the original operating speed is constant, since V _T must also be smaller gradually lower the operation voltage becomes serious enough to low-voltage operation. In particular, at high temperature operation, since V _T is low and S is large, this problem becomes more serious. In the future downsizing era of computers and the like where low power consumption is important, the increase of the subthreshold current is an essential problem. In particular, battery 1 such as 0.9-1.6V
It is extremely important to deal with this increase in current even in electronic devices that are to be operated individually.

[Non-Patent Document 1] 1989 International Symposium OMBLS Technology, Systems and Applications, Proceedings of Technical Papers (1989
May) Pages 188 to 192 (1989 International
Symposium on VLSI Technology, Systems and Applicat
ions, Proceedings of Technical Papers, pp.188-192
(May 1989))

[0016]

The object of the present invention is to provide an MO.
It is to provide a semiconductor integrated circuit of high speed and low power even if the S transistor is miniaturized, and to realize an electronic device of low voltage operation such as battery drive with low current.

[0017]

In order to achieve the above object, in the present invention, a control circuit means for controlling the supply of a large current and a small current is inserted between the source of a MOS transistor and a power supply, and the control circuit means is used. Switch these currents accordingly
Supply to the OS transistor circuit. For example, a large current is supplied when high speed operation is required, and a small current is supplied when low power consumption is required.

Since high speed operation is required during normal operation, a large current is supplied from the current supply means to the MOS transistor circuit to enable high speed operation. At this time, MOS
Although a direct current flows through the transistor circuit as described above, it is acceptable because it is usually sufficiently smaller than the operating current, that is, the load charging / discharging current.

On the other hand, since low power consumption is required during standby, the supplied current is switched to a small current to suppress the subthreshold current. At this time, since the current is limited, the logic amplitude of the MOS transistor circuit is generally smaller than that at the time of supplying a large current, but it does not matter as long as the logic level can be guaranteed.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the present invention will be described in more detail below with reference to the drawings.

[Embodiment 1] First, FIG. 1 is a preferred embodiment for explaining the principle of the present invention.

FIG. 1A is a circuit diagram of an inverter according to an embodiment of the present invention. In the figure, L is a CMOS inverter, which is composed of a P-channel MOS transistor M _P and an N-channel MOS transistor M _N. As described later, the present invention can be applied to not only an inverter but also a logic gate or a logic gate group such as NAND and NOR. However, for simplicity, the case of an inverter will be described here. S
_C and S _S are switches, and R _C and R _S are resistors, and the feature of this embodiment is that switches S _C and S are provided between the power supply terminals V _CL and V _SL of the inverter L and the power supplies V _CC and V _SS , respectively. _{The S} and the resistors R _C and R _S are inserted in parallel, which realizes the reduction of the subthreshold current as described below.

During the time period when high speed operation is required, the switches S _C and S _S are turned on and V _CC and V _SS are directly connected to the inverter L.
(Hereinafter, referred to as high-speed operation mode). M _P , M _N
If the threshold voltage (V _T ) is set low, high speed operation can be achieved. At this time, a subthreshold current flows through the inverter L as described above, but this is not a problem because it is usually sufficiently smaller than the operating current, that is, the load charging / discharging current.

On the other hand, during a time period when low power consumption is required, the switches S _C and S _S are turned off, and power is supplied to the inverter through the resistors R _C and R _S (hereinafter referred to as low power consumption mode). . The voltage drop due to the subthreshold current flowing through the resistor causes V _{CL to} fall below V _CC and V _{SL to} rise above V _SS . As shown in FIG.
Due to this voltage drop, the subthreshold current is reduced by the following two mechanisms. The M _N when the input signal IN is at the low level (V _SS ) will be described, but the same applies to M _P when the input signal IN is at the high level (V _CC ).

[0025] (i) because the source potential V _SL rises, takes a back gate bias _{V BS = V SS -V SL =} -V M,
The threshold voltage rises from V _T0 to V _T1 . The increase in the threshold voltage is

[0026]

[Equation 4]

It is This reduces the subthreshold current from I _L0 to I _L1 . The rate of decrease is

[0028]

[Equation 5]

[0029] Here, K is a substrate effect coefficient.
For example, V _M = 0.3V, K = 0.4√V, S = 100mV / deca
de, if 2ψ = 0.64V, the subthreshold current is 21
%.

[0030] (ii) Since the source potential V _SL rises, the gate-source voltage _{V GS = V SS -V SL =} -V M is negative. As a result, the subthreshold current is further increased to I _L1.
To I _{L 2} . The rate of decrease is

[0031]

[Equation 6]

It is For example, V _M = 0.3V, S = 100m
If V / decade, the subthreshold current is 0.1%
Is reduced to.

Combining the effects of (i) and (ii),

[0034]

[Equation 7]

[0035] For example, if V _M = 0.3V, 0.02%
become. Where V _M is the equation

[0036]

[Equation 8]

Is the solution of

The MOS transistor M of the inverter L
The back gates of _P and M _N are the respective sources (V _CL ,
Although it may be connected to V _SL ), in order to obtain the effect of (i), it is preferable to connect to V _CC and V _SS as shown in FIG.

FIG. 3 shows the effect of reducing the subthreshold current.
Show. This section describes ultra-high-integrated LSI for future ultra-low voltage operation.
, And the threshold voltage when the back gate bias is 0
Pressure V _T0= 0.05 to 0.15V, the off-state transformer of the entire LSI
Only when the total sum of the channel width of the transistor W = 100 m
Is calculated. The larger the resistance, the more V_MIs big
And the effect will be greater. In extreme cases, the resistance is infinite
It is also possible to eliminate the large, that is, the resistance.

However, as shown in FIG. 1B, since the logical amplitude of the output signal OUT is smaller than the logical amplitude of the input signal IN, it is necessary to pay attention to the voltage level of the signal in the multi-stage connection. This will be described later.

Further, the present invention has a function of automatically compensating for variations in threshold voltage. That is, when the threshold voltage subthreshold current is large low voltage drop V _M due to resistance is increased, when the threshold voltage is high and the subthreshold current is small, V _M becomes smaller.
In either case, fluctuations in current are suppressed. As is clear from FIG. 3, the fluctuation of the subthreshold current is smaller as the resistance value is larger. For example, if the resistance value is set to 3 kΩ or more, the variation of the subthreshold current I _L can be suppressed within ± 20% even if the threshold voltage varies by ± 0.05V.

[Embodiment 2] Next, a specific method of realizing the switch and the resistance described in Embodiment 1 will be described. FIG. 4 shows an example in which both the switch and the resistor are realized by MOS transistors.

Switch MOS transistors M _C1 and M
_S1 is a MOS transistor having a large conductance, which corresponds to the switches S _C and S _S of FIG. 1, respectively. In the high speed operation mode, the signal φ _{C is set} to the low level and the signal φ _{S is set} to the high level to turn on M _C1 and M _S1 . φ _C ,
The voltage level of φ _S may be V _SS and V _CC , respectively,
In order to increase the conductance of M _C1 and M _S1 ,
φ _C may be lower than V _SS and φ _S may be higher than V _CC . The voltage for that is given from the outside of the chip or E
It may be generated by a well-known on-chip booster circuit in EPROM or DRAM.

In the low power consumption mode, conversely, by setting φ _C to a high level and φ _S to a low level, M _C1 , M
_S1 turns off. At this time, the current must be surely suppressed. For that purpose, there are the following two methods. The first method is to make φ _C higher than V _CC and φ _S lower than V _SS by an external voltage or an on-chip boost circuit. The second method is to use, as M _C1 and M _S1 , transistors having a higher threshold voltage (more enhancement) than that used in the inverter L. The first method has an advantage that a step for producing transistors having different threshold voltages is unnecessary. On the other hand, the second method is advantageous in terms of area because it does not require a terminal for receiving an external voltage or an on-chip booster circuit.

The MOS transistors M _C2 and M _S2 are MOS transistors having a small conductance and correspond to the resistors R _C and R _S of FIG. 1, respectively. The gates of these transistors are connected to V _SS and V _CC , respectively, and are always on. These transistors do not need to be turned off, so their threshold voltage can be low.

An N channel MOS transistor can be used as M _{C2 and a} P channel MOS transistor can be used as M _S2 . For example, M _C2 N-channel MO
Taking an S-transistor as an example, a resistor can be effectively realized by so-called diode connection in which the terminal having its gate and drain connected to each other is connected to the V _CC terminal and its source is connected to the V _CL terminal. By adjusting the channel width and the threshold voltage of the N-channel MOS transistor,
For example, during standby, the voltage of V _CL can be set to a voltage lower than V _{CC by} the threshold voltage of the N-channel MOS transistor, and the subthreshold current can be greatly reduced.

Next, the time zone to which the present invention is applied will be described. FIG. 5 shows an example of the timing of the signals φ _C and φ _S.

FIGS. 5A and 5B show a case where the present invention is applied to a memory LSI. The memory LSI is a chip enable signal CE which is a clock signal from the outside.
When (complementary signal) is at low level, it is in the operating state, and when it is at high level, it is in the standby state. In the case of FIG. 5A, the internal signal φ
_C becomes low level in synchronization with the fall of CE, and CE
It goes to a high level slightly after the rise of ￣. Internal signal φ
_S is the opposite. Therefore, in the figure, the time zone a is in the high-speed operation mode, and the time zone b is in the low power consumption mode. Generally, in a memory device using a large number of memory LSIs, a small number of LSIs are in an operating state, and most LSIs are in a standby state. Therefore, by reducing the power consumption of the LSI in the standby state by using the present invention, it greatly contributes to the reduction of the power consumption of the entire memory device. The reason for providing the delay from the rise of CE to the low power consumption mode is that the internal circuit of the LSI is reset during this period.

FIG. 5B shows an example in which the power consumption is further reduced. Here, the high speed operation mode is set only immediately after the change of CE. That is, immediately after CE goes low, data reading / writing is performed, and CE
Since the internal circuit is reset immediately after the high level, the high speed operation mode according to the present invention is set in these time zones, and the low power consumption mode according to the present invention is set in the other time zones. Although not listed here,
The high speed operation mode may be entered when the address signal changes.

FIG. 5C shows an example in which the present invention is applied to a microprocessor. In the normal operation state, the clock CL
K is applied. At this time, the signal φ _C is low level,
φ _S is at a high level, which is a high speed operation mode. When the microprocessor enters the standby state or the data holding state, the clock CLK is stopped and the signal BU goes high. In synchronization with this, φ _C becomes high level and φ _S becomes low level, and the low power consumption mode is set. As a result, the power consumption of the microprocessor is reduced, and it becomes possible to back up for a long time with a small capacity power source such as a battery.

FIG. 6 is an example of a device structure for realizing the circuit of FIG. Polysilicon 130 in this figure,
131, 132, and 133 are M _C2 , M _P , and
Corresponds to the gates of M _N and M _S2 (M _C1 and M _S1 are not listed here).

It should be noted that M _C2 and M _P share the same n-well 101 (connected to V _CC through n + diffusion layer 120). M _N and M _S2 likewise share a p-substrate (connected to V _SS ) 100. As can be seen, connecting the back gate of the MOS transistor to V _CC and V _SS not only achieves the effect of (i) above, but also in terms of layout area, compared to connecting it to the source. It is advantageous.

In the example shown here, the n-well is formed in the p-substrate, but conversely, the p-well may be formed in the n-substrate. Alternatively, ISC SCI, Digest of Technical Papers, 248.
Pages 249, February 1989 (ISSCC Digest of
A triple well structure as described in Technical Papers, pp.248-249, Feb.1989) may be used.

[Embodiment 3] FIG. 7 shows another method of realizing a switch and a resistor. The feature of this embodiment is that a current mirror circuit is used. That is, the MOS transistors M _C2 and M _C3 having the same threshold voltage form a so-called current mirror circuit sharing a gate and a source.
A current proportional to the current source I ₀ flows through _C2 , and its impedance is large. The same applies to M _S2 and M _S3 . Therefore, M _C2 and M _S2 can be regarded as high resistance.
The circuit CS including the current source I ₀ and M _C3 and M _S3 may be shared by a plurality of logic gates.

The current mirror circuit may be not only the circuit shown here but also other circuits. For example, a bipolar transistor may be used instead of the MOS transistor.

As described above, the method of realizing the switch and the resistor can be variously modified. In short, any means may be used as long as it allows a large current to flow during a time period when high speed operation is required and a small current during a time period when low power consumption is required. In the following drawings, for simplicity, the switches and resistors are used as shown in FIG.

[Embodiment 4] The back gate of the MOS transistor of the inverter is not limited to V _CC and V _SS , but may be connected to another power source, and its voltage may be variable. FIG. 8 shows an example thereof. Here, the back gates of M _P and M _N are connected to the power supplies V _WW and V _BB , respectively, and their back gate voltage values are changed during operation and during standby. As for V _BB, the time zone in which high-speed operation is required by shallow V _BB (or in extreme cases slightly positively) that enable high-speed operation by reducing the V _T of M _N. The time zone requiring low power consumption by increasing the V _T of M _N to deepen the V _BB, suppress the subthreshold current. As a result, the effect of (i) above is further enhanced. The V _BB has been described above,
V _WW is the same _except that the polarities of the voltages are reversed. In addition,
This type of back gate voltage generating circuit is disclosed in, for example, ISC SCI, Digest of Technical Papers, pages 254 to 255, 1985.
February (ISSCC Digest of Technical Papers, pp.254-25
5, Feb. 1985).

FIG. 9 shows a device for realizing the circuit of FIG.
It is an example of a chair structure. Here, the above-mentioned Mie well structure
N-well 105 (P-channel MOS transistor
The back gate of the transistor is via the n + diffusion layer 120.
V_WW, P-well 103 (N-channel MOS transistor
Back gate of the transistor V) via the p + diffusion layer 127. _BB
It is connected to the.

This triple well structure has the advantage that the back gate voltage can be set for each circuit because both P-channel and N-channel can be placed in independent wells for each circuit. For example, when a circuit in the operating state and a circuit in the standby state coexist in one LSI, the back gate voltage of the former can be made shallow and the back gate voltage of the latter can be made deep.

[Embodiment 5] Next, the case of an inverter array in which inverters are connected in multiple stages will be described. For simplicity,
First, the principle will be described in the case of two stages.

FIG. 10A is a circuit diagram when the CMOS inverters L ₁ and L ₂ are connected. Switches S _Ci and S _Si and resistors R _Ci and R _Si (i
= 1, 2) has been inserted.

In the high speed operation mode, all four switches are turned on and V _CC and V _SS are directly applied to the inverters L ₁ and L ₂ . If the threshold voltage (V _T ) of the MOS transistor of the inverter is set low, high speed operation can be achieved. On the other hand, in the low power consumption mode, all the four switches are turned off and power is supplied to the inverter through the resistors. Due to the voltage drop caused by the subthreshold current flowing through the resistor, V _CL1 and V _CL2 are lower than V _CC , and V _SL1 and V _SL2 are higher than V _SS .

The first stage inverter L ₁ is shown in FIG.
Similar to the case, the subthreshold current is reduced by the mechanisms (i) and (ii). However, as shown in FIG. 10B, the logical amplitude of the output N ₁ of L ₁ is smaller than the logical amplitude of the input signal IN. That is, IN is at a low level (= V
_{When SS} ), the voltage level of N ₁ becomes V _CL1 , and when IN is at a high level (= V _CC ), the voltage level of N ₁ becomes V _SL1 .
Since this becomes the input of the second stage inverter L ₂ , in order to reduce the subthreshold current of L ₂ , V _CC > V _CL1
It is desirable to set the resistance values such that> V _CL2 and V _SS <V _SL1 <V _SL2 . As a result, L ₂
The subthreshold current is reduced by the mechanisms (i) and (ii). When V _CL1 = V _CL2 and V _SL1 = V _SL2 , the effect (i) can be obtained but the effect (ii) cannot be obtained.

[Embodiment 6] The same applies to the case of the multistage connection shown in FIG. 11A, where V _CC > V _CL1 > V _CL2 >...> V
_CLk , V _SS <V _SL1 <V _SL2 <... <V _SLk is preferable. However, as shown in FIG. 11B, since the logical amplitude becomes smaller for each stage, a level conversion circuit is appropriately inserted to recover the amplitude. In this example, a level conversion circuit LC is added after the k-stage inverter so that the logical amplitude of the output signal OUT becomes the same as that of the input signal IN. This kind of level conversion circuit is described, for example, in Symposium on VLS L.S.K., Digest of Technical Papers, pages 82 to 83, June 1992 (Symposium on VLSI Circ).
uits, Digest of Technical Papers, pp.82-83, June 1
992).

The level conversion circuit LC is unnecessary in high speed operation. Because all the switches are on, V _CL1 = V _CL2 = ... = V _CLk = V _CC , V _SL1 = V
_{This is because SL2} = ... = V _SLk = V _SS and there is no decrease in logic amplitude. Therefore, when operating at high speed, the switch S
Delays can be avoided by turning on _LC and bypassing the level translation circuit.

[Embodiment 7] FIG. 12A shows another example of a multistage connected inverter array. In this example, the switch S _C ,
S _S and resistors R _C and R _S are shared by all the inverters L _{1 to} L _k, and the voltages V _CL and V _SL are common to L _{1 to} L _k . Therefore, as described in the explanation of FIG.
The effect of reducing the subthreshold current by the mechanism of (i) can be obtained, but the effect by (ii) cannot be obtained. Therefore, the effect of reducing the subthreshold current is smaller than that in the previous embodiment.

However, on the other hand, there is an advantage that the layout area of the switch and the resistor can be saved. In addition, FIG.
As shown in (b), the voltage levels of all signals (including input / output signals) are the same, and there is the feature that there is no decrease in logic amplitude as in the previous embodiment. Therefore, there is an advantage that a level conversion circuit is unnecessary and logic such as NAND and NOR can be easily assembled.

[Embodiment 8] Next, the case where the present invention is applied to a general combinational logic circuit will be described.

For example, consider the combinational logic circuit shown in FIG. To apply the present invention to this, first, the logic gates are divided into groups as shown in FIG. In this example, 15 logic gates L _{1 to} L ₁₅ are divided into three groups G ₁ , G ₂ and G _3.
It is divided into In grouping, the output signals of the logic gates included in the i-th group are input only to the logic gates of the (i + 1) th and subsequent groups.

Next, as shown in FIG. 14, a switch and a resistor are inserted between each group and the power source. The logic amplitude of the output signal of the logic gate is 1 as in the case of FIG.
Since each stage becomes smaller, the level conversion circuit groups GC ₁ and GC ₂ are inserted to restore the amplitude as shown in FIG.
Although not shown, the level conversion circuit groups GC ₁ and GC ₂ may be bypassed during high speed operation as in the case of FIG.

One of the characteristics of this embodiment is that the logic gates included in the same group share the resistance with the switch. In the example of FIG. 13, the three inverters included in the group G ₁ include the switches S _C1 and S _S1 and the resistor R 1.
_C1 and R _S1 are shared.

Another feature of this embodiment is that the groups before and after the level conversion circuit share the switch and the resistance. That is, the groups G ₁ and G _{k + 1} include the switches S _C1 , S _S1 and the resistors R _C1 , R _S1 and the groups G ₂ and G _k , respectively.
_{k + 2} includes switches S _C2 , S _S2 and resistors R _C2 , R _S2 , ...
.., groups G _k and G _2k share switches S _Ck , S _Sk and resistors R _Ck , R _Sk , respectively.

By thus sharing the switch and the resistance with a plurality of logic gates, it is possible to reduce the number of the switch and the resistance as a whole LSI and save the layout area.

[Embodiment 9] FIG. 15 shows another embodiment of the present invention. The embodiment of FIG. 15 differs from the previous embodiments in that voltage limiters (step-down circuit, step-up circuit) VC ₁ , V
That is, C ₂ , ..., VC _k , VS ₁ , VS ₂ , ..., VS _k are used.

When low power consumption is required, the switches T _{C1 to} T _Ck and T _{S1 to} T _Sk are switched to the illustrated side, and power is supplied to the logic gate group by the voltage limiter. The voltage limiters VC ₁ , VC ₂ , ..., VC _k operate as a step-down circuit on the power supply voltage V _CC side, and are lower than V _CC and are almost stabilized internal voltages V _CL1 , V _CL2 , ..., V _CLk. Occurs respectively. On the other hand, VS ₁ , VS ₂ , ..., VS _k are connected to the ground V _SS.
It operates as a booster circuit on the side and generates internal voltages V _SL1 , V _SL2 , ..., V _SLk that are higher than V _SS and are almost stabilized. The generated voltage is V _CC as in the previous embodiment.
＞ V _CL1 ＞ V _CL2 ＞ …… ＞ V _CLk , V _SS <V _SL1 <V _SL2 <
...... <V _SLk is better. A voltage limiter of this type is disclosed in Japanese Patent Laid-Open No. 2-246516.

On the contrary, when a high speed operation is required, the switch is switched to the side opposite to that shown in the drawing, and V _CC , V
_{Apply SS} directly to the group of logic gates to enable high speed operation. At this time, the voltage limiter is not necessary, so the operation may be stopped.

[Embodiments 10 and 11] In the above embodiments, circuits having no feedback such as inverter trains and combinational logic circuits were used, but the present invention can be applied to circuits having feedback. As an example, a case of a latch circuit shown in FIG. 16A in which two NAND gates are combined will be described.

A circuit diagram is shown in FIG. 2 NA
Switches S _C1 , S _S1 , S _C2 , S _S2 and resistors R _C1 , R _S1 , R _C2 , R _S2 are inserted between the ND gates L ₁ and L ₂ and the power supply Vcc and the ground Vss, respectively. V _CL1 ,
V _CL2 falls _below V _CC , V _{SL 1} and V _SL2 rise above V _SS , and the mechanism (i) reduces the subthreshold current.

FIG. 17 shows four M's used to latch information in order to further reduce the subthreshold current.
The threshold voltage V _T of the OS transistors M _P12 , M _P22 , M _N12 , and M _N22 is set to the other MOS transistors M _P11 , M _P21 ,
In this example, the threshold voltage is higher (more enhanced) than that of M _N11 and M _N21 . Another MO to which the input signal is applied
Since the threshold voltage V _T of the S transistors M _P11 , M _P21 , M _N11 and M _N21 remains low, high speed operation is possible.
In this case, the switch and the resistor on the V _SS side are unnecessary. This is because the high threshold voltage V _SS side transistors M _N12 , M
_This is because the current can be reliably suppressed by _N22 .

[Embodiments 12 and 13] In the embodiments so far, the subthreshold current can be reduced regardless of whether the input signal is at a low level or a high level. But the actual L
In SI, the time zone in which the subthreshold current reduction is required, for example, the level of a specific signal in a standby state is often known in advance. In such a case, the subthreshold current can be reduced with a simpler circuit.

FIG. 18 shows the input signal IN in the standby state.
Is an example of a circuit of an inverter array when it is known to be at a low level (“L”). Since IN is low, nodes N ₁ , N ₃ , N ₅ , ... Are high, N ₂ , N ₄ , N ₆ ,.
... becomes low level, M _P2 , M _P4 , ... Of the P channel MOS transistors are off, and M _N1 , M _N3 , ... Of the N channel MOS transistors are off. It is sufficient to insert the switches and resistors only in the sources of these off-state transistors. The subthreshold current flows because it is a transistor in the off state.

As shown in FIG. 19, the switch and the resistor may be shared by a plurality of inverters.

Although these embodiments have the restriction that the level of the input signal must be known, they have the advantage that the subthreshold current can be reduced with a simple circuit. As is clear from comparing FIGS. 18 and 19 with FIG. 11, the number of switches and resistors is reduced, and the level conversion circuit becomes unnecessary.

[Embodiments 14 and 15] If the level of the input signal in the standby state is known not only in the inverter but also in the logic gates such as NAND and NOR, the subthreshold current can be reduced by a simpler circuit. it can.

FIG. 20 shows an example of a 2-input NAND gate, and FIG. 21 shows an example of a 2-input NOR gate. Two input signals IN ₁
When IN and IN ₂ are both low level or both are high level, these gates are substantially equivalent to the inverter, and therefore the method described with reference to FIGS. 18 and 19 can be applied. The problem is when one input is low level (“L”) and the other input is high level (“H”) as shown.

In the case of the NAND gate of FIG. 20, the P-channel MOS transistor M _P12 and the N-channel MOS transistor M _N11 are off, but the output OUT is at a high level, so that the subthreshold current flows in M.
It is _N11 . Therefore, it suffices to insert a switch and a resistor on the V _SS side. On the contrary, in the case of the NOR gate in FIG. 21, it is the P-channel MOS transistor M _P14 that the subthreshold current flows. Therefore, it suffices to insert a switch and a resistor on the V _CC side.

20 and 21 show an example in which the present invention is applied to a 2-input logic gate, the same can be applied to a 3-input or higher logic gate. Of course, the switch and the resistor may be shared with other logic gates.

[Embodiment 16] FIG. 22 shows an example of a circuit in the clock inverter when it is known that the clock CLK ₁ is at a low level and the clock CLK ₂ is at a high level in the standby state. In this case, the MOS transistors M _P16 , M
_Since both _N16 are off, the output OUT will be high impedance and its voltage level will be determined by other circuitry (not shown) connected to OUT. Since the subthreshold current flows in which of the MOS transistors M _P16 and M _N16 depends on the voltage level, in this case, a switch and a resistor may be inserted on both the V _CC side and the V _SS side as shown in the figure.

[Embodiment 17] Even in the case of a general combinational logic circuit, if the level of the input signal is known in advance, the subthreshold current can be reduced by a simpler circuit. The combinational logic circuit shown in FIG. 13 will be described as an example.

FIG. 23 shows an example of the circuit configuration when the inputs IN _{1 to} IN ₆ of this circuit are all known to be low level.
For the inverters L _{1 to} L ₃ , L ₅ and L ₆ , switches and resistors are inserted on the V _SS side of L _{1 to} L ₃ and the V _CC side of L ₅ and L ₆ as in FIGS. 18 and 19. . The NOR gate L ₇ is substantially equivalent to an inverter because all the input signals are low level. Therefore, it suffices to insert a switch and a resistor on the V _SS side. Since one of the input signals of the NOR gate L ₄ is at a low level and the other is at a high level, a switch and a resistor are inserted on the V _CC side as in the case of FIG. 8 NANs
Of the D gates, only L ₁₂ has all three input signals at high levels and is equivalent to an inverter. Therefore, a switch and a resistor are inserted on the V _CC side. In other NAND gates, low level and high level input signals coexist, so that a switch and a resistor may be inserted on the V _SS side as in FIG.

As is apparent from the above description, a switch and a resistor may be inserted on the side of V _SS for the logic gate whose output is at the high level, and on the side of V _CC for the logic gate whose output is at the low level. . As shown in FIG. 23, the layout area can be saved by sharing these switches and resistors among a plurality of logic gates.

[Embodiment 18] Even for a circuit having feedback, if the signal level is known in advance, the subthreshold current can be reduced by a simpler circuit. FIG. 24 shows an example applied to the latch of FIG. 16 (a).

In a latch of this type, in the standby state, both the input signals IN ₁ and IN ₂ are normally at a high level, one of the output signals OUT ₁ and OUT ₂ is at a low level, and the other is at a high level. Holds 1-bit information. Figure 2
4 is an example of a circuit configuration when it is known that OUT ₁ is low level and OUT ₂ is high level. NAND gate L
₁ is equivalent to an inverter because the two input signals are both at high level, and a switch and a resistor are inserted on the V _CC side as in FIGS. 18 and 19. NAND gate L ₂ is
Since one of the input signals is at the low level and the other is at the high level, a switch and a resistor may be inserted on the V _SS side as in the case of FIG. Of course, these switches and resistors may be shared with other logic gates.

[Embodiment 19] FIG. 25 is an example in which the present invention is applied to a known data output buffer in a memory LSI or the like. In the standby state, the output enable signal OE is at low level, the outputs of the NAND gates L ₂₁ and L ₂₂ are at high level, and the output of the inverter L ₂₃ is at low level. Therefore, the two MOS transistors M _P20 and M _N20 forming the output stage L ₂₄ are both off, and the output DOUT has a high impedance.

FIG. 23 shows the logic gates L _{21 to} L ₂₃ .
In accordance with the policy described in the above description, the switch and the resistor may be inserted on the V _SS side or the V _CC side. For the output stage L ₂₄ , switches and resistors may be inserted on both the V _CC side and the V _SS side, as in the case of the clock inverter of FIG.

[Embodiment 20] FIG. 26 is an example in which the present invention is applied to a well-known data input buffer in a memory LSI or the like. In the figure, SB is a signal that goes high in the standby state. The outputs of the inverters L ₃₁ and L ₃₂ can be used for controlling the switches as φ _S and φ _C , respectively, as shown in FIGS. 4 and 7. L ₃₃ is a NAND gate, the inputs of which are φ _S and the data input signal D _IN . Since φ _S is at a low level in the standby state, D _IN
Regardless of the above, the output of L ₃₃ is high, and thus the output of the output d _IN of the inverter L ₃₄ is low. on the other hand,
In the operating state, SB is at a low level, so d _IN follows D _IN .

For the NAND gate L ₃₃ and the inverter L ₃₄ , the subthreshold current can be reduced by inserting a switch and a resistor on the V _SS side and the VCC side, respectively. This method cannot be used for the inverters L ₃₁ and L ₃₂ , but the subthreshold current can be reduced by increasing the threshold voltage of the MOS transistor. Since switching between the standby state and the operating state does not often require high speed, a MOS transistor having a high threshold voltage may be used.

Although the data input buffer has been described above, the same applies to the input buffers for address signals and other signals.

The embodiments of FIGS. 18 to 25 have the advantage that the subthreshold current can be reduced by a simple circuit, but are applied when the signal level in the time zone where the subthreshold current reduction is required, for example, in the standby state is not known. There is a constraint that you cannot do it. Therefore, at this time, L
It is desirable to have as many levels of nodes in the SI as established. As a means for this, by using a circuit such as the input buffer in FIG. 26, the level of the signal d _{IN at} this time can be fixed at a low level. In addition to this, as a method of determining this level, there is also a method of defining a specification that "the data input terminal D _IN is set to a low level (or a high level) in the standby state".

The embodiment of FIGS. 18 to 26 is a memory LSI.
It is suitable to be applied to. This is because, in the memory LSI, there are relatively many nodes whose high level or low level is known in the standby state, and the levels of most nodes can be fixed by using the input buffer of FIG. .

In a random logic LSI such as a microprocessor, the output of an internal register is fixed, or logic such as a flip-flop circuit with a reset function is added to forcibly fix the voltage of a node in question. It is also effective to do. FIG. 35 shows a configuration example of a latch circuit whose output can be fixed. This circuit has a simple configuration in which an inverter in a normal latch circuit is replaced with a NAND circuit. As shown in FIG. 36, while φ _S is at a high level, it operates as a normal latch circuit, and while φ _S is at a low level (sleep mode), the level of output signal Q is fixed at a high level. Here, the sleep mode is a mode in which the operation of the entire LSI or the circuit block unit is stopped in order to reduce current consumption. By setting φt to a low level and φb to a high level during the sleep mode, the subthreshold current of the latch circuit itself can be reduced. When this latch circuit is used, the node N ₄₁ is forcibly set to the high level when φ _S is set to the low level, and the information in the register is erased in the sleep mode. However, there is no problem in a method of saving necessary information in the CPU in the main memory and resuming from the reset state after the sleep mode, for example, a resume function of putting the notebook computer in a standby state when there is no input for a certain time. . FIG. 37 shows another example of the configuration of the latch circuit that can forcibly fix the output. As shown in FIG. 38, this circuit also has φ
_{While S} is at a high level, it operates as a normal latch circuit, and while φ _S is at a low level, the level of the output signal Q is fixed at a high level. Since this latch circuit does not affect the node N ₄₁ even when φ _S becomes low level, it can retain information even during the sleep mode. After the sleep mode is released, the state before the sleep mode can be resumed as it is, and the sleep mode can be set even while the CPU is executing the task. Therefore, it is suitable for returning from the sleep mode in a relatively short time.

The embodiments of FIGS. 25 and 26 can be used not only as an input / output circuit for an external terminal of an LSI chip but also as a driver / receiver for an internal bus of a microprocessor, for example.

[Embodiment 21] Up to now, the present invention has been applied to CMO.
Although the embodiment applied to the S circuit has been described, the present invention can also be applied to a circuit composed of a single-polarity MOS transistor. FIG. 27 shows an example of a circuit composed of only N-channel MOS transistors. In the figure, PC is a precharge signal, and IN ₁ and IN ₂ are input signals.

In the standby state, that is, in the precharge state,
PC is at high level, IN ₁ and IN ₂ are at low level, and the output OUT is precharged to high level (= V _CC -V _T ). In operation, after the PC goes low, IN
₁ and IN _{2 go} high or stay low. If at least one of IN ₁ and IN ₂ goes high, OUT goes low, and if both stay low, OUT remains high. That is, this circuit is a circuit that outputs NOR of IN ₁ and IN ₂ .

In this circuit, the transistors that are turned off during standby are M _N41 and M _N42 on the V _SS side, and a subthreshold current flows through these transistors. Therefore, to apply the present invention to this circuit, a switch and a resistor may be inserted on the V _SS side as shown in the figure. It is not necessary on the V _CC side.

In an LSI having a complicated operation such as a random logic LSI, for example, a logic (voltage) state of each node inside the chip in a standby state is obtained by using a design automation (DA) method. According to the result, the position where the above-mentioned switch and resistor are inserted can be automatically determined by DA.

As described above, the present invention is extremely effective in reducing the power consumption of a MOS transistor circuit and a semiconductor integrated circuit composed of the MOS transistor circuit. Recently, the demand for low power consumption of semiconductor integrated circuits is particularly strong, and for example, Nikkei Electronics September 2, 1991, No. 106.
Pages 111 to 111 describe a microprocessor system having a low power backup mode. In the backup mode, the power consumption is reduced by stopping the clock and stopping the power supply to unnecessary parts. However, even the reduction of the subthreshold current is not considered. Since these processor systems operate at 3.3-5V, sufficiently high threshold voltage transistors can be used so that the subthreshold current is small enough not to be a problem. However, in the future the operating voltage will drop to 2V or 1.5V,
If the threshold voltage has to be lowered, the conventional CMO
The method of using the S circuit can no longer reduce the excessive subthreshold current. If the present invention is applied to, for example, a resume circuit (power is supplied even in the backup mode), further lower power consumption can be realized.

In the above example, there are problems in that the logic amplitude decreases with an increase in the number of stages, and when the voltage level of the input signal is not known in advance, a slightly complicated design is required. FIG. 28 shows a solution to these problems. In the required time period until the logic output is determined, the switch is turned on as described above, and normal high speed operation is performed.
In other time zones, the switch is turned off to cut off the subthreshold current path of the logic circuit (the example of the CMOS inverter is shown). However, when the switch is turned off, the supply path of the power supply voltage is cut off, so that the output of the logic circuit becomes floating and the logic output becomes uncertain. Therefore, a kind of latch circuit (level hold circuit) that holds the voltage level at its output
Is the feature. If a transistor with a high threshold voltage is used in the level hold circuit, the subthreshold current of the level hold circuit becomes so small that it can be ignored, and the subthreshold current can be made small as a whole. The delay time is less affected by the level hold circuit and is determined by the logic circuit. Even if a high-speed circuit having a large driving capability is used as the logic circuit, current does not flow through the logic circuit in the standby state, so the consumption current is only the current flowing through the level hold circuit. Since the level hold circuit only holds the output, it may have a small driving ability and a small current consumption. Even if the switch is turned off, since the output of the logic circuit is held by the level hold circuit, there is no risk of the output being inverted, and stable operation is achieved. Therefore, it is possible to realize a semiconductor device with low power consumption and stable operation at high speed. According to the present invention, since the voltage level is always guaranteed to be a constant value by the level hold circuit, the logic amplitude does not decrease as the number of logic stages increases.
Moreover, it is effective regardless of the logic input.

This embodiment will be further described with reference to FIG. The logic circuit LC is connected to the high-potential power supply line VHH and the low-potential power supply line VLL via the switches SWH and SWL. Here, VHH and VLL can also correspond to V _CC and V _SS described above. The level hold circuit LH is connected to the output terminal OUT of the logic circuit LC. The switches SWH and SWL are
It is controlled by the control pulse CK and turned on and off at the same time. The logic circuit LC is composed of a logic gate such as an inverter, a NAND circuit, a NOR circuit, a flip-flop circuit, or a combination thereof. The level hold circuit LH can be composed of a positive feedback circuit.

The operation of the logic circuit LC is performed by turning on the switches SWH and SWL. After the output OUT according to the input IN of the logic circuit LC is determined, the switches SWH and S
Turn off WL to VHH through V via logic circuit LC
The current path to SS is cut off, and the output of the logic circuit LC is held by the level hold circuit LH.

The delay time of the circuit is little affected by the level hold circuit LH and is determined by the logic circuit LC. It is possible to perform a high-speed operation with a short delay time by using a circuit having a large driving capability for the logic circuit LC. For example, since no current flows through the logic circuit LC in the standby state, the current consumption is only the current flowing through the level hold circuit LH. Since the level hold circuit LH may have a small driving capability, the current consumption can be reduced. Moreover, since the output OUT of the logic circuit LC is maintained by the level hold circuit LH, there is no risk of malfunction. Therefore, it is possible to realize a circuit that operates stably at high speed with low power consumption.

FIG. 29 shows an embodiment in which the present invention is applied to a CMOS inverter. NMOS transistor MN1,
The PMOS transistor MP1 operates as the switches SWL and SWH in FIG. 28, respectively. In order to reduce the leakage current when turned off, the transistors MN1,
The threshold voltage of MP1 is made sufficiently large. Determine the channel width / channel length so that the on-resistance does not increase.
A control pulse C is applied to the gate of the NMOS transistor MN1.
K, and the control pulse CKB is input to the gate of the PMOS transistor MP1. CKB is a complementary signal of CK. The CMOS inverter INV composed of the NMOS transistor MN2 and the PMOS transistor MP2 is connected to the MN
1, connect to MP1. The threshold voltage of the transistors MN2 and MP2 is set to be small in order to increase the driving capability by the low voltage operation. A level hold circuit LH including NMOS transistors MN3 and MN4 and PMOS transistors MP3 and MP4 is connected to the output terminal OUT of the inverter INV. Transistors MN3, MN4, MP
3, the threshold voltage of MP4 is made sufficiently large, and the channel width / channel length is made sufficiently small. Numerical examples of power supply voltage and threshold voltage will be given. Set VLL to ground potential 0V and set VH
H is an external power supply voltage of 1V. The threshold voltage of the NMOS transistor is 0.2V for MN2 and 0.4V for MN1, MN3 and MN4. The threshold voltage of the PMOS transistor is -0.2V for MP2 and -0.4V for MP1, MP3 and MP4.

The operation will be described with reference to the timing chart shown in FIG. First, the control pulse CK is raised to VHH, and C
KB is lowered to VLL, the transistors MN1 and MP1 are turned on, and the inverter INV is connected to VHH and VLL. When the input signal IN rises from VLL to VHH, MP2 turns off and MN2 turns on, and the output OUT
Is discharged from VHH to VLL. Transistor MN2
Starts conducting in a saturation region, and the current value flowing through MN2 is determined by the voltage between the gate (input terminal IN) and the source (node NL). Since the transistor MN1 is provided between the node NL and VLL, the potential of the node NL temporarily rises due to the ON resistance of MN1 and the current flowing from MN2. However, since the gate of MN1 is at VHH, the ON resistance can be designed to be sufficiently small even if the threshold voltage is large, and the influence on the delay time can be reduced. Further, when the output OUT is inverted to VLL, the level hold circuit LH keeps the output OUT at VHH so that MN4 is turned off and MP4 is turned on. Therefore, when MN2 is turned on, a through current flows from VHH to VLL through MP4 and MN2, but by designing the driving capability of MP4 to be smaller than that of MN2, the influence on the delay time and current consumption is small. The output OUT goes down, turning off MN3.
P3 turns on, and the node NL in the level hold circuit
H reverses from VLL to VHH and MN4 turns on MP4
Is turned off, and the level hold circuit LH outputs the output OUT.
So as to keep VLL at VLL, no through current flows. MP2 is off because the gate and the source are both VHH, but the threshold voltage is small, so the leak current is large and the through current flows through the inverter INV. Then, the control pulse CK is lowered to VLL, CKB is raised to VHH, the transistors MN1 and MP1 are turned off, and the inverter INV is separated from VHH and VLL. At this time, the gates and sources of MN1 and MP1 have the same potential and the threshold voltage is large, so that they are completely turned off. The output OUT is kept at VHH by the positive feedback of the level hold circuit LH. At this time, since the NMOS transistor MN2 is on, the node NL is kept at VLL. On the other hand, node N
PMOS transistor MP2 from H to output terminal OUT
Due to the leak current of the node NH, the voltage of the node NH starts to drop. Then, MP2 has a source potential lower than the gate potential and is completely turned off. As a result, the through current of the inverter INV does not flow in the standby state. Then, the input signal IN
Control pulse CK to VHH before CK changes
B is lowered to VLL, the transistors MN1 and MP1 are turned on, and the node NH is set to VHH. Input IN is VH
By inverting from H to VLL, the output OUT becomes VL
Invert from L to VHH.

Inverter INV and level hold circuit L
It is desirable that the level hold circuit LH quickly follow the output OUT so that the period during which the through current flows through H becomes short. Therefore, the inverter INV and the level hold circuit LH are arranged close to each other to reduce the wiring delay.

As is apparent from this embodiment, when the threshold voltage of the MOS transistor used as a switch is set to about 0.4 V or more, which is conventionally required to reduce the subthreshold current, the standby state is set. The threshold voltage of the MOS transistor in the logic circuit can be reduced without increasing the through current. Operating voltage is 1V
Even if the voltage is lowered below, the driving capability can be secured by setting the threshold voltage of the MOS transistor to 0.25 V or less. Therefore, lower power consumption can be realized by lowering the voltage.
Further, based on the conventional scaling rule, performance improvement can be realized by scaling the element. Moreover, except for loading the switch and the level hold circuit, the conventional CM
Since the configuration is the same as that of the OS logic circuit, the same design method as the conventional one can be used.

FIG. 31 shows an embodiment in which the present invention is applied to a CMOS inverter chain. An inverter chain can be realized by connecting a configuration in which two switches and a level hold circuit are provided to the one-stage inverter shown in FIG. 29 in multiple stages, but in this embodiment, the switch and the level hold circuit are shared by a plurality of inverters. In this example, the number of elements and the area are reduced. Here, the case of a four-stage inverter chain is taken as an example, but the case of other numbers of stages is similarly configured. Four inverters INV1, INV2, INV3
INV4 is connected in series. Final stage inverter INV
The level hold circuit LH is connected to the output terminal OUT of No. 4. Each inverter has a PM like the INV in FIG.
It is composed of one OS transistor and one NMOS transistor. The transistor size of each inverter may be the same or different. As is often used as a driver, the channel length is made the same and the channel width is set to INV1, INV2, INV3, INV at certain stages.
It can be increased in the order of 4. The source of the PMOS transistor of each inverter is connected to the node NH and the NMO
The source of the S transistor is connected to the node NL. A switch SW is provided between the node NL and the low level power supply VLL.
A switch SWH is provided between the node NH and the high-level power supply VHH. The switches SWL and SWH are controlled by the control pulse CK, and are turned on and off at the same time.
As shown in FIG. 29, the switch SWL is realized by an NMOS transistor, and the SWH is realized by a PMOS transistor whose gate receives a complementary signal of CK.

The operation of the inverter chain is the switch S.
Perform by turning on WL and SWH. For example, when the input IN is inverted from the low level VLL to the high level VHH, the inverter INV1 inverts the node N1 from VHH to VLL, INV2 inverts the node N2 from VLL to VHH, and INV3 inverts the node N3 from VHH to VLL.
And the output terminal OUT is inverted from VLL to VHH by INV4. When OUT is set to VHH, the level hold circuit LH operates to keep OUT at VHH. In the standby state, by turning off the switches SWL and SWH, VHH to VLL via the inverter is turned on.
Cut off the current path to.

When the present invention is applied to the inverter chain, it is sufficient to provide the level hold circuit only at the output terminal by treating the inverter chain as one logic circuit as a whole as in the present embodiment. Further, the switches SWL and SWH can be shared by a plurality of inverters. The sizes of the switches SWL and SWH are determined by the size of the peak current that flows. The peak of the sum of the currents flowing through the plurality of inverters is smaller than the sum of the peak currents of the respective inverters. For example, when an inverter chain is configured with an interstage ratio of 3, the peak of the current sum is almost the same as the peak current of the final stage. Therefore, sharing the switch among a plurality of inverters requires a smaller switch area than a case where a switch is provided for each inverter.

FIG. 32 shows another embodiment in which the present invention is applied to an inverter chain. Similar to FIG. 31, the case of an inverter chain with four stages is taken as an example, but the case of other numbers of stages is similarly configured. 4 inverters INV1,
INV2, INV3, INV4 are connected in series. Level hold circuits LH3 and LH4 are connected to a node N3 which is an output terminal of the inverter INV3 and an input terminal of INV4 and an output terminal OUT of INV4, respectively. Each inverter is composed of one PMOS transistor and one NMOS transistor, similar to INV in FIG. The odd-numbered inverters INV1 and INV3 are connected to the node NL1.
And NH1 to even-numbered inverters INV2, INV
4 is connected to the nodes NL2 and NH2. Node NL
1, NL2 between the low level power supply VLL and the switches SWL1 and SWL2, and the high level power supply VHH between the nodes NH1 and NH2 and the switch SWH, respectively.
1, SWH2 are provided. Switches SWL1, SWL
2 and SWH1 and SWH2 are controlled by a control pulse CK and are turned on and off at the same time.

The operation of the inverter is the switch SWL1,
This is performed by turning on SWL2, SWH1, and SWH2. For example, when the input IN is inverted from the low level VLL to the high level VHH, the node N1 changes from VHH to VLL and the node N
2 from VLL to VHH, node N3 from VHH to VL
Output terminal OUT goes from VLL to VH by INV4
Invert to H sequentially. When N3 is determined to be VLL, the level hold circuit LH1 operates to keep N3 at VLL. When OUT is set to VHH, the level hold circuit LH operates to keep OUT at VHH. For example, in the standby state, the switches SWL1, SWL2, S
By turning off WH1 and SWH2, the current path from VHH to VLL via the inverter is cut off. At this time, since the node N3 is kept at the low level VLL by the level hold circuit LH3, the node NL1 is also kept at VLL through the inverter INV3. Further, the node N1 is kept at VLL through the inverter INV1. Similarly, the output terminal OUT has a level hold circuit LH.
By being kept at the high level VHH by 4, the nodes NH2 and N2 are also kept at VHH. Therefore, the node connecting the inverters is maintained at either VHH or VLL.

As described above, two sets of switches are provided, the odd-numbered inverters and the even-numbered inverters are connected to different switches, and any output terminal of the odd-numbered inverters and any one of the even-numbered inverters are connected. By connecting the level hold circuits to the output terminals, all the nodes N1, N2, N3 between the inverters are maintained at either the high level or the low level. Even if the standby state continues for a long time, the input of the inverter does not reach the intermediate level, so that the operation is stable, and there is no fear that information will be inverted or a through current will flow when the switch is turned on.

The present invention has been described above with reference to the embodiments applied to the CMOS inverters and the inverter chains. However, a book in which a switch and a level hold circuit are loaded in a logic circuit to perform stable operation at low power consumption and at high speed The present invention is not limited to the embodiments described above without departing from the spirit of the invention.

For example, another embodiment in which the present invention is applied to a CMOS inverter is shown in FIG. In the embodiment shown in FIG. 29, the transistor MN1, which operates as a switch,
MP2 is a CMOS inverter INV and power supplies VLL and VH
It is provided between H and. On the other hand, in this embodiment, N
It is provided between the MOS transistor and the PMOS transistor.

Two NMOS transistors MN2 and MN
One and two PMOS transistors MP1 and MP2 are connected in series between a low level power supply VLL and a high level power supply VHH. NMOS transistors MN1 and PMOS
The transistor MP1 operates as a switch. The threshold voltage of the transistors MN1 and MP1 is increased to reduce the leakage current when turned off. NMO
A control pulse CK is applied to the gate of the S transistor MN1,
The control pulse CKB of the complementary signal of CK is input to the gate of the PMOS transistor MP1. The gates of the NMOS transistor MN2 and the PMOS transistor MP2 are connected to the input terminal IN and operate as a CMOS inverter. The threshold voltage of the transistors MN1 and MP1 is set to be small in order to increase the driving capability in the low voltage operation.
The output terminal OUT is connected to the level hold circuit LH configured similarly to FIG.

The operation is performed in the same manner as the embodiment shown in FIG. Transistor MN by control pulse CK, CKB
1, MP1 is turned on to turn on the transistors MN2 and MP2
To operate as a CMOS inverter. For example, when the input IN is inverted from the low level VLL to the high level VHH, the transistor MN2, which has been off until then, starts conducting and operates in the saturation region. At this time, the current value of MN2 is determined by the gate-source voltage. In this embodiment, since the transistor MN1 is provided between the MN2 and the output terminal OUT, the ON resistance of MN1 is connected to the drain of MN2. Therefore, the influence of the on-resistance of MN1 on the current value of MN2 is small. After the output OUT is determined, the transistors MN1 and MP1 are turned off to prevent a shoot-through current, and the level hold circuit LH maintains the output OUT.

When the switch is inserted into the output terminal side of the logic circuit as in the present embodiment, the switch cannot be shared by a plurality of logic gates, but the influence of the ON resistance of the switch is small. When the transistors used as switches are the same, the delay time becomes shorter than when the switches are provided on the power supply side of the logic circuit as in the embodiment shown in FIG. Alternatively, if the delay time is designed to be the same, the transistor used as a switch can have a small channel width / channel length, and the area thereof can be reduced.

FIG. 34 shows another configuration example of the level hold circuit. This level hold circuit is used for the NMOS transistors MN3, MN4 and PMO in the embodiment shown in FIG.
A case in which the level hold circuit LH configured by the S transistors MP3 and MP4 is replaced and used will be described.

This level hold circuit has three NMOS transistors MN3, MN4, MN5 and PM respectively.
It is composed of OS transistors MP3, MP4 and MP5. The threshold voltage of each transistor is increased in order to reduce the leak current in the standby state. For example, NMOS
Transistor 0.4V, PMOS transistor-
It is set to 0.4V. MN3 and MP3 form an inverter, and MN4, MN5, MP4 and MP5 form a switching inverter. The control pulse CKB is input to the gate of MN5, and the control pulse CK is input to the gate of MP5. The operation timing is the same as in the case of using the level hold circuit LH shown in FIG. 29, and is as shown in FIG. The control pulse CK is raised to the high level VHH, CKB is lowered to the low level VLL, and the inverter IN
Operate V. At this time, the transistors MN5 and MP5 are turned off in the level hold circuit. Therefore, when the output OUT is inverted, a through current does not flow through the inverter INV and the level hold circuit, and the delay time and current consumption can be reduced. In the standby state, the control pulse CK is lowered to the low level VLL and CKB is changed to the high level VLL.
It is raised to HH to disconnect the inverter INV from the power supplies VLL and VHH. At this time, in the level hold circuit, the transistors MN5 and MP5 are turned on, and the output O
The UT is retained.

By thus configuring the level hold circuit with the combination of the inverter and the switching inverter, the number of transistors is increased by two, but the logic circuit and the level hold circuit do not conflict with each other, and the delay time and current consumption are small. Complete. Further, the drive capability of the level hold circuit may be increased, and stable operation can be performed without fear of fluctuation of the output even when the leak at the output terminal is large.

FIG. 39 shows an embodiment applied to a logic circuit which performs a logical operation with a two-phase clock. In a typical LSI such as a microprocessor, most of the logical operations in the chip are performed in synchronization with a two-phase clock.
The logic circuit is divided into two circuits LC1 and LC2, and latch circuits LT1 and LT2 controlled by clocks CK1b and CK2b are added to the respective outputs. In this embodiment, the latch circuits LT1 and LT2 function as a level hold circuit.
Here, LC1 and LC2 are combination logic circuits each including one logic gate or a plurality of logic gates. Since the two logic circuits LC1 and LC2 operate alternately in synchronization with the clock, the switches SWH1 and SWL1 and SWH2
And SWL2 are alternately turned on and off by a clock to cut off the subthreshold current of the logic circuit which does not operate. Using this embodiment, a low power LSI with a low operating voltage and a small subthreshold current can be realized.

The operation will be described with reference to the specific circuit example shown in FIG. 40 and the control clock timing shown in FIG. Here, for simplicity, one inverter is shown as each of the logic circuits LC1 and LC2. Further, although the level hold circuit shown in FIG. 34 is used as the latch circuits LT1 and LT2, the circuit shown in FIG. 29 may be used. The clocks CK1t and CK2t are alternately set to the high level without overlapping each other. Clocks CK1b and CK2
b is a signal obtained by inverting CK1t and CK2t. Here, the MO that constitutes the logic circuits LC1 and LC2.
High-speed operation is possible if the threshold voltage of the S transistor is kept low. On the other hand, the clock M is input to the gate.
The OS transistor must be able to cut off the subthreshold current when it is off. To do so, either increase the threshold voltage or set the high level of the clock to VHH.
Higher and lower levels lower than VLL.

In the operation mode, the logic circuit LC1 operates while CK1t is at the high level. At this time, CK2t
Is low level, the latch circuit LT2 holds information to be input to LC1. In addition, since the logic circuit LC2 does not have to operate, the transistors MP12 and M
Turn off N12 to shut off the subthreshold current. On the contrary, while CK2t is at the high level, LT2 retains information and LC2 operates, so that the subthreshold current of LC1 can be cut off. That is, always L
Since the current of either one of C1 and LC2 can be cut off,
The subthreshold current is half that of the conventional one.

In a recent microprocessor operating from 3.3V to 5V, in order to reduce the power consumption as described above, in a low power backup mode (sleep mode), application of a clock to an unnecessary circuit is stopped. It also reduces the charge / discharge current. In this embodiment, as shown in FIG. 41, the clocks CK1t and CK during the sleep mode are used.
By setting both 2t to a low level, the transistors MP11 and MN11, MP12 and MN12 are all turned off, and the through currents of both the logic circuits LC1 and LC2 are cut off. Therefore, the sleep mode is more effective in reducing the subthreshold current than the operation mode.

FIG. 42 shows another embodiment of the present invention, which is an example applied to a gate array. Since the gate array is a digital logic circuit, it is possible to reduce the subthreshold current by applying the embodiments already shown. However, in a gate array, as will be described below, when a logic circuit is configured, some gates are inactivated without being used. FIG. 42 (A) shows one circuit block of a gate array using a 2-input NAND as a basic cell.
An example of configuring the logic shown in (B) is shown. Broken line A00 in the figure
1, A002 and A003 are basic NAND cells. INN1 and OUT1 are the input and output of this logic circuit block, respectively. When configuring an inverter with NAND cells as shown in the figure, one of the inputs, A004 and A005, is set to high level (V
It is common practice to fix this to _CC ) and deactivate the corresponding gate. This passivated gate often accounts for tens of percent of the available gates, so in low voltage gate arrays with transistor threshold voltages scaled, the subthreshold current through the passivated gates. Cannot be ignored. As shown in the figure, the transistors MA01 and MA03 are connected to the second power supply line V _CL separated from V _CC through the transistor M _C and the resistor R _C.
If the source of is connected and φ _{C is set} to high level in the power saving mode and M _C is cut off, the transistor M
Since the gate and source of A01 and MA03 are reverse-biased and a deep cut-off state is set, the subthreshold current of the inactivating gate can be greatly reduced. However, regarding the active gate, as already described, during low power consumption time zones, for example, the logic state of each gate output during standby (high level: “H &# 34 or low level:“ L &# 34 ”in the figure) Corresponding to, the source of the P-channel transistor is V _CC or V
The source of the N-channel transistor is V _SL or V _SS to _CL
Needless to say, the leak current can be prevented by connecting them to each other. Note that for the inactive gate, it is not necessary to pass a current through the transistor even during operation, so other wiring having a higher impedance formed with the minimum wiring width may be used instead of V _CL. , The transistor M _C is not always necessary,
It is also possible to use only the resistance R _C.

FIG. 43 is a diagram showing another embodiment of the present invention, showing an example in which a sub-threshold current prevention according to the present invention is applied to an inactive gate in a gate array using a 2-input NOR as a basic cell. . This figure shows an example in which the logic shown in FIG. 43 (B) is configured by NOR cells. Broken line in the figure A01
1, A012 and A013 are basic NOR cells. When configuring an inverter with NOR cells, one of the inputs, A014 and A015
It is common practice to fix a LOW (V _SS ) and inactivate the corresponding gate. At this time, the transistor MA
If the sources of 11 and MA13 are connected to V _SL , these transistors can be put into a deep cut-off state according to the operation principle already described, and the subthreshold current can be prevented.

Further, as the size of the LSI chip increases, it is common that a test circuit for testing other circuit groups is built in the chip. This test circuit
The operation can be stopped during the normal operation other than the test. In this case, in order to reduce the subthreshold current of the test circuit, the embodiments described so far are effective.

Each of the embodiments described above is a single chip
An example applied to a microprocessor is shown below. First, we describe a microprocessor that has the power reduction mechanism used so far. In a conventional microprocessor, power is controlled by controlling the entire chip at once. For example, in the i386SL manufactured by Intel Corporation, since the internal circuit is completely static, the internal state is retained even if the input of the clock to the chip is stopped, and the operation can be resumed by restarting the input of the clock. As described above, by stopping the input of the clock, the operation of the entire chip is stopped, and the power of the entire system is reduced. However, this was possible only when the power supply voltage was as high as 3.3 V to 5 V as in the past. CMO
This is because the threshold voltage of the MOS transistors forming the S circuit can be as high as 0.4 to 0.5 V, and the subthreshold current can be made so small that it can be ignored. However, as described above, in a high-speed system that operates with a voltage of one battery such as a power supply voltage of 2 V or less or about 0.9 to 1.6 V, it is no longer possible to reduce the power consumption even if the clock is stopped. Generally, in an LSI composed of logic gates mainly composed of random gates, it is said that, out of a large number of logic gates in a chip, the number of logic gates in which the input voltage of the logic gate changes is about 20% of the whole. The input does not change in the other about 80% of the logic gates.
Fortunately, since the threshold voltage was high in the conventional CMOS circuit, the power of 80% of the logic gates could be almost ignored, and the entire chip could be made low in power. However, this can no longer be expected at the stop power supply voltage. Hereinafter, a microprocessor will be taken as an example of an electronic device in which the entire chip has low power in low power supply voltage operation.

FIG. 44 shows a single-chip microprocessor incorporating the power reduction mechanism of the present invention. As described below, the feature is that a mechanism for controlling active / standby for each unit is provided inside the chip. 600 is a single-chip microprocessor. A central processing unit (hereinafter abbreviated as CPU) 601 and a coprocessor A are provided on the microprocessor 600.
(Hereinafter, abbreviated as COPA) 602, coprocessor B (hereinafter, abbreviated as COPB) 603, local memory (hereinafter, abbreviated as COPA)
A LM (abbreviated as LM) 604 and a bus control unit (hereinafter, abbreviated as BUSC) 605 are incorporated. These units are connected by an internal bus 651 on the chip. The outside of the chip is connected to the external bus 652 via the BUSC 605. The external bus 652 has a main memory (hereinafter abbreviated as MS) 606, an input / output device (hereinafter,
607 and the like are abbreviated as IO. The CPG 606 is a clock generator, and each unit inside the chip operates in synchronization with a clock signal 653 generated from the CPG 606.

COPA602, COPB603, LM6
04 has two operating states, respectively. One of them is a sleep state. In this state, the operation of each unit is stopped and the consumed power is extremely small.
The other one is active. In this state, the unit is executing processing such as data read / write operation and arithmetic processing operation. Therefore, the power consumption is not kept extremely small. The logic circuits that make up these units are, for example, as shown in FIGS.
The circuits shown in FIGS. 39 to 41 are used. Thereby, power consumption in the sleep state can be reduced. Even in the active state, for example, using the circuits of FIGS.
Power can be reduced by finely controlling the activation state for each phase of the two-phase clock. MS
606 and IO607 also have an active / sleep state. Signal 65 output from microprocessor 600
4 and 655 are signals instructing that the MS 606 and the IO 607 are in the active state, respectively.

The COPA 602 and COPB 603 are basically the same type of unit, and execute the designated operation only when the program executed by the CPU has an instruction requesting the operation of COPA or COPB. It is active only at this time, and it is good to sleep during other periods. In a normal program, the frequency of this calculation request is not so high. It has a large number of register files and a dedicated arithmetic unit with a large number of transistors (sometimes several) inside, and is characterized by a large number of transistors as a whole.

Since the LM 604 stores the programs and data required by the CPU, it is frequently accessed. However, in the case where the cache memory is built in the CPU, the processing is performed by closing the inside of the CPU, so that the access frequency decreases and the sleep state period becomes long.

The CPU 601 is a part that executes instructions and processes data, and constantly executes programs (activation rate 100%). The inside of the CPU includes the basic parts of an ordinary processor such as general-purpose registers and arithmetic units. Sometimes it also includes cache memory. Instructions and data are L
It is stored in M604 or MS606. LM6
Reference numeral 04 is an on-chip memory that has a small capacity but can be accessed at high speed, and stores instructions and data that are frequently used by the CPU 601. Instructions and data that do not need to be accessed very often are stored in the MS 606, which has a large capacity but has a medium to low speed. The CPU 601 can directly access the LM 604 via the internal bus 651. On the other hand, access to MS606 is
Via an internal bus 651, a BUSC 605, and an external bus 652. The BUSC 605 includes an external bus buffer having a width of about 32 to 128 bits. It need only be active when the CPU accesses a memory or device outside the chip. When a program or data required by the CPU exists inside the chip, the sleep state may be set.

The COPA 602 is a coprocessor for executing multiplication, division, square root, and absolute value calculation, and incorporates a dedicated arithmetic unit that processes these operations at high speed. COPB6
Reference numeral 03 denotes a coprocessor that executes functional operations such as trigonometric functions and distance calculations, and has a built-in dedicated arithmetic unit that processes these operations at high speed. The CPU 601 activates an operation in each coprocessor by writing a command instructing the requested operation to the command registers CMDA 609 and CMDB 610 in the COPA 602 and COPB 603 via the internal bus 651. Each coprocessor is in a sleep state and consumes almost no power until the operation is started.

FIG. 45 is an internal block diagram of the COPA 602. Inside is two blocks ITFA700 and EXA70
It consists of 1. ITFA700 is a command register CM
It has a DA 609, a command decoder DEC 706, operand registers RA 702, RB 703, RC 704, and a control circuit CNT 705. EXA701 is multiplication,
It has a built-in dedicated computing unit that processes division, square root, and absolute value calculations at high speed, and a control circuit that controls it. The command sent from the CPU 601 via the internal bus 651 is held in the CMDA 609, the DEC 706 decodes the command, and the EXA 701 executes the operation instructed by the command. The commands are multiply, divide,
There are four types: square root and absolute value. As the operand for the operation, the source operand sent from the CPU 601 is stored in RA 702 and RB 703, and the operation result is EXA.
After the calculation is completed in 701, it is stored in RC 704 and the CPU 6
It is read from 01. The EXA 701 is in a sleep state when it is not performing a calculation. When the DEC 706 decodes the command, a signal that causes the EXA 701 to execute the operation instructed by the command is generated,
The EXA 701 starts the calculation. EXA7 during calculation
01 becomes active. After the calculation, EXA70
1 stores the result in RC 704 and clears CMDA 609 to zero. The DEC 706 detects that the content of the CMDA 609 is zero, and the SLEEP 707 signal is asserted, causing the EXA 701 to enter the sleep state. The CNT 705 has each register 609, 702, 70.
Controls operations such as read / write and zero clear for 3, 704. The ITFA 700 is always in an active state so that it can always receive commands from the CPU. The clock signal 653 generated from the CPG 606 is used by the ITFA 700. Further, the EXA clock signal 710 is output via the gate circuit 709, and this is used as the clock of the EXA 701. When SLEEP 707 is asserted, the gate circuit 709 stops the EXA clock 710 and E
The clock is no longer supplied to the XA 701. As a result, in the sleep state, the clock of the EXA 701 is also stopped. The SLEEP signal controls the switches of the circuits shown in FIGS. 18 to 26 or 28 to 32, and reduces the subthreshold current in the sleep state.

The inside of the EXA 701 includes a dedicated arithmetic unit, a register for holding an intermediate result of an operation, a register for holding an operation state, a latch for operation control, and the like. These registers and latches are, for example, shown in FIG.
5 or the circuit of FIG. 37 is used. In the case of the circuit of FIG. 35, once the sleep state is entered, the state inside the latch is destroyed. On the other hand, in the case of the circuit of FIG. 37, the state inside the latch is not destroyed even when the sleep state is entered. For this reason,
When the sleep state is once entered and then the active state is returned to, it is possible to restart the arithmetic operation stopped in the middle.

The COPB 603 is a coprocessor that executes functional operations such as trigonometric functions and distance calculations, but its internal structure and operation are the same as those of the COPA 602.

FIG. 46 shows the internal structure of the LM 604. M
The EM 901 is a memory unit that stores information such as instructions / data. The MCNT 902 receives an access request from the CPU 601, controls reading of data stored in the MEM 901, and writing of data to the MEM 901. When there is an access request from the CPU 601, the MCNT 902 asserts a signal ACT 903 that makes the MEM 901 active, and puts the MEM 901 into an operating state. ACT90 when there is no access request
The MEM 901 is in the sleep state because 3 is negated. With this ACT signal, for example, FIGS.
6 or the switches of the circuits shown in FIGS. 28 to 32 are controlled to reduce the subthreshold current in the sleep state. Note that the information is retained in the memory even in this state. The MCNT 902 is always in the active state so that the access request from the CPU can be always accepted.

When the CPU 601 accesses an instruction or data to the MS 606, the internal bus 651, the BUSC 60
5, via the external bus 652. BUSC 605 becomes active only at this time. BUSC 605 in FIG.
The internal structure of is shown. The BCNT 800 is a circuit that controls access to the external bus 652 in response to a request from the CPU 601. The OUTB 801 is a driver circuit that drives the external bus 652 when data is sent from the internal bus 651 to the external bus 652, and is active only at this time. INB 802 is from external bus 652 to internal bus 651
This is a driver circuit that drives the internal bus 651 when data is sent to and is active only at this time. B
CNT800 is CPU60 to MS60 outside the chip
6 and IO607 write request is received,
Assert ACTW 803 to activate OUTB 801. Conversely, when the BCNT 800 receives a read request from the MS 606 or IO 607 outside the chip from the CPU 601, it asserts ACTR 804 and INB
Activate 802. Other than these times, OUT
B801 and INB802 are in a sleep state. BCN
The T800 is always in the active state so that the access request to the outside of the chip can be always accepted. The BCNT 800 also outputs an active support signal 654 for the MS 606 and an active indication signal 655 for the IO 607. When the CPU 601 requests the BCNT 800 to access the MS 606, the BCNT
800 detects it and asserts signal 654, MS6
06 is activated. The signal 655 is also used for the same purpose.

For OUTB801, for example, the output buffer circuit shown in FIG. 25 is used, and the switches S _S and S _C are controlled according to the ACTW signal. Since OUTB drives a large load (external bus 652), MO with a large channel width is used.
Only as many S-transistors as bus widths (eg 64 bits) are needed, and the total channel width is very large. Therefore, reducing the subthreshold current of OUTB greatly contributes to reducing the current of the entire system.

The input buffer circuit of FIG. 26 is used for the INB 802, and the ACTR signal is supplied to the SB terminal. As a result, the internal bus 65 in the sleep state is
A voltage level of 1 can be established. Therefore, the units COPA, COP connected to this bus
The circuits of FIGS. 18 to 25 can be used for B and LM, and the subthreshold current of these units can be easily reduced.

A DRAM, for example, is used for the MS 606. As the DRAM, an ordinary DRAM may be used,
I E E Spectrum, pp. 43-49, October 1992 (IEEE Spectrum, pp.43-4
9, Oct. 1992) synchronous DRAM.
But it's okay. In the synchronous DRAM, since the clock supply to the inside of the chip can be controlled by the clock enable / disable signal, the current consumption can be effectively reduced by utilizing this signal. That is, in the sleep state, the supply of the clock to the inside of the chip is stopped. Further, by using the circuit of FIG. 26 as the input buffer of the synchronous DRAM and applying the clock enable / disable signal to the SB terminal, the subthreshold current of the internal circuit can be reduced.

FIG. 48 shows an operation example of the entire microprocessor 600. The horizontal axis represents the time, the diagonal lines each unit,
Indicates that each block is active. In this example, the CPU 601 issues a division command to the COPA 602 at time T1, and accordingly the COPA 602 executes division from T1 to T2, and at the time T2 the CPU 6 finishes the operation.
01 and goes to sleep again. Then CP
U601 issues a distance calculation command to COPB 603 at time T3, and accordingly COPB 603 causes T3 to T4.
Distance calculation is executed up to the end of calculation at time T4 by CPU6
01 and goes to sleep again. The LM 604 becomes active only when there is a data access request from the CPU 601. The BUSC 605 also becomes active only when the CPU 601 accesses the outside.
In this way, the power consumption of the microprocessor 600 can be significantly reduced by finely controlling the active / sleep state of each unit and each block inside the microprocessor 600.

Although the present embodiment is a case in which the present invention is applied to one chip, it is obvious that this can be extended to an embodiment of a computer system having a plurality of chips. For example, it is easy to apply the present invention to the case where each unit of 601 to 605 in FIG. 44 is configured by a different chip.

[0154]

As described above, according to the present invention,
It is possible to realize a high-speed and low-power-consumption MOS transistor circuit and a semiconductor integrated circuit configured by the MOS transistor circuit.

[Brief description of drawings]

FIG. 1 is a diagram showing an inverter according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a principle of reducing a subthreshold current according to the present invention.

FIG. 3 is a diagram showing a subthreshold current reduction effect according to the present invention.

FIG. 4 is a circuit diagram of an inverter according to a second embodiment of the present invention.

FIG. 5 is a diagram showing the timing of signals of the present invention.

FIG. 6 is a diagram showing a device structure of the present invention.

FIG. 7 is a circuit diagram of an inverter according to a third embodiment of the present invention.

FIG. 8 is a circuit diagram of an inverter according to a fourth embodiment of the present invention.

FIG. 9 is a diagram showing a device structure of the present invention.

FIG. 10 is a diagram showing an inverter array according to a fifth embodiment of the present invention.

FIG. 11 is a diagram showing an inverter array according to a sixth embodiment of the present invention.

FIG. 12 is a diagram showing an inverter array according to a seventh embodiment of the present invention.

FIG. 13 is a diagram showing an example of grouping of combinational logic circuits to which the present invention is applied.

FIG. 14 is a diagram showing a combinational logic circuit according to an eighth embodiment of the present invention.

FIG. 15 is a diagram showing a combinational logic circuit according to a ninth embodiment of the present invention.

FIG. 16 is a diagram showing a latch according to the tenth embodiment of the present invention.

FIG. 17 is a circuit diagram of a latch according to an eleventh embodiment of the present invention.

FIG. 18 is a circuit diagram of an inverter array according to a twelfth embodiment of the present invention.

FIG. 19 is a circuit diagram of an inverter array according to a thirteenth embodiment of the present invention.

FIG. 20 is a circuit diagram of a NAND gate according to Example 14 of the present invention.

FIG. 21 is a circuit diagram of a NOR gate according to Embodiment 15 of the present invention.

FIG. 22 is a circuit diagram of a clock inverter according to a sixteenth embodiment of the present invention.

FIG. 23 is a circuit diagram of a combinational logic circuit according to a seventeenth embodiment of the present invention.

FIG. 24 is a circuit diagram of a latch according to an eighteenth embodiment of the present invention.

FIG. 25 is a circuit diagram of an output buffer according to a nineteenth embodiment of the present invention.

FIG. 26 is a circuit diagram of an input buffer according to a twentieth embodiment of the present invention.

FIG. 27 is a circuit diagram of an NMOS dynamic circuit according to a working example 21 of the invention.

FIG. 28 shows a conceptual example.

FIG. 29 is a circuit diagram of an embodiment applied to a CMOS inverter.

FIG. 30 is an operation timing chart of the embodiment applied to the CMOS inverter.

FIG. 31 is a diagram showing an embodiment applied to an inverter chain.

FIG. 32 is a diagram showing another embodiment applied to an inverter chain.

FIG. 33 is a diagram showing another embodiment applied to a CMOS inverter.

FIG. 34 is a circuit diagram of another configuration example of the level hold circuit.

FIG. 35 is a circuit diagram of a latch circuit capable of fixing an output.

FIG. 36 is a timing diagram of the control clock.

FIG. 37 is a circuit diagram of a latch circuit that can fix an output.

FIG. 38 is a timing diagram of the control clock.

FIG. 39 is a diagram showing a two-phase clock logic circuit.

FIG. 40 is a circuit diagram of an inverter that operates with a two-phase clock.

FIG. 41 is a timing diagram of the control clock.

FIG. 42 is a diagram showing a gate array according to the present invention.

FIG. 43 is a diagram showing a gate array according to the present invention.

FIG. 44 is a block diagram of a single chip microprocessor according to the present invention.

FIG. 45 is an internal configuration diagram of a coprocessor.

FIG. 46 is an internal configuration diagram of a local memory.

FIG. 47 is an internal configuration diagram of a bus control unit.

FIG. 48 is an operation timing chart of the microprocessor.

FIG. 49 is a circuit diagram of a conventional CMOS inverter.

FIG. 50 is a diagram showing a subthreshold characteristic of a MOS transistor.

[Explanation of symbols]

L, L _{1 to} L _k ... Logic gate, G _{1 to} G _k ... Logic gate group, S _C , S _{C1 to} S _Ck , S _S , S _{S1 to} S _Sk ... switch,
R _C , R _{C1 to} R _Ck , R _S , R _{S1 to} R _Sk, ... Resistors.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI Theme Coat (reference) H03K 19/00 19/20 (72) Inventor Kiyoo Ito 1-280, Higashi Renegakubo, Kokubunji, Tokyo Inside the Central Research Laboratory (72) Inventor Ken Sakata 1-280, Higashi-Kengokubo, Kokubunji, Tokyo Inside Hitachi Central Research Laboratory (72) Inventor Masakazu Aoki 1-280, Higashi-Kengokubo, Kokubunji-shi, Tokyo Inside Central Research Center, Hitachi, Ltd. (72) Inventor Takayuki Kawahara 1-280, Higashi Koigokubo, Kokubunji, Tokyo 5F038 AV06 AV13 BB04 BG03 CA04 CD02 CD04 CD06 CD15 DF01 DF04 DF05 DF06 DF08 DT02 DT12 EZ09 EZ20 5A0748 AA01 AB01 AB04 AC03 AC10 BB14 BE02 BE03 BE09 5J042 BA19 CA14 CA24 CA27 DA02 5J056 AA03 BB17 CC03 DD13 DD29 EE04 EE11 FF01 FF08 FF09 FF10 KK02

Claims (5)

[Claims] 1. A first inverter circuit, a latch circuit connected to the first inverter circuit, and control circuit means connected to the first inverter circuit, wherein the first inverter circuit is a first MOS circuit. The transistor and its source / drain path are connected to the first operating potential point and the second
A source / drain path of the first MOS transistor and a second MOS transistor connected in series between the source / drain path of the first MOS transistor and the source / drain path of the second MOS transistor; The control circuit means is configured to obtain an output signal from an output node that is a common connection point with the drain path, and the control circuit means is connected to either one of the first or second MOS transistor and is supplied with a control signal.
Setting the control signal supplied to the control circuit means to the first state allows a relatively large current to flow through one source of the first or second MOS transistor and supplies the control signal to the control circuit means. By setting the control signal to a second state different from the first state, the current flowing through the one source of the first or second MOS transistor is limited to a value smaller than the relatively large current, The latch circuit, when the control signal is in the first state,
A first inverter circuit based on a signal output from the first inverter circuit;
A semiconductor integrated circuit, which outputs a level or second level signal, and outputs the first level signal when the control signal is in the second state. 2. The latch circuit according to claim 1, wherein the latch circuit includes a second inverter circuit and a NAND circuit, and a first input of the NAND circuit is an output of the first inverter circuit and a second inverter circuit. A semiconductor integrated circuit connected to an output, wherein the control signal is input to a second input of the NAND circuit, and an output of the NAND circuit becomes an output of the latch circuit. 3. The latch circuit according to claim 1, further comprising a second inverter circuit, a third inverter circuit, and a NAND circuit, wherein an input of the second inverter circuit is an output of the first inverter circuit. And an output of the third inverter circuit, an input of the third inverter circuit is connected to an output of the second inverter circuit, and a first input of the NAND circuit is connected to an output of the second inverter circuit. The control signal is input to a second input of the NAND circuit, and an output of the NAND circuit is an output of the latch circuit. 4. The semiconductor integrated circuit according to claim 1, wherein the first inverter circuit and the NAND circuit are included in a microprocessor. 5. A semiconductor integrated circuit having a latch circuit for always fixing an output to a first level in a sleep mode.