JP3641481B2 - Semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit composed of fine MOS transistors, and more particularly to a circuit suitable for high speed and low power operation.

  As described in Non-Patent Document 1, the breakdown voltage decreases as the MOS transistor is miniaturized, and thus the operating voltage must be lowered. In particular, in a semiconductor device used in a battery-operated portable device or the like, the operating voltage is further reduced in order to reduce power consumption.

In this case, in order to maintain high-speed operation, it is necessary to reduce the threshold voltage (V _T ) of the MOS transistor in accordance with the decrease in the operating voltage. This is because the operating speed is governed by the effective gate voltage of the MOS transistor, that is, the value obtained by subtracting V _T from the operating voltage, and the larger this value, the higher the speed. For example, according to the above document, the standard value of the threshold voltage of a transistor that operates at 1.5 V with a channel length of 0.25 μm is expected to be 0.35 V. According to a well-known scaling law, if the operating voltage is 1V, the standard value of the threshold voltage is about 0.24V. However, when the V _T below about 0.4V, as described below, by the sub-threshold characteristics of the MOS transistor (tailing characteristics), a phenomenon that transistor completely no longer able longer to turn off the DC current to flow Arise. Therefore, in an operation of 1.5 V or less, this current becomes a serious problem in practical use.

A conventional CMOS inverter shown in FIG. 49 will be described. Ideally, when the input signal IN is at a low level (= V _SS ), the N-channel MOS transistor _MN is turned off, and when IN is at a high level (= V _CC ), the P-channel MOS transistor _MP is turned off. In any case, no current flows. However, when the V _{T of} the MOS transistor is lowered, the subthreshold characteristic cannot be ignored.

ただし、ＷはＭＯＳトランジスタのチャネル幅、Ｉ₀、Ｗ₀はＶ_Tを定義する際の電流値およびチャネル幅、Ｓはテーリング係数（Ｖ_GS-log Ｉ_DS特性の傾きの逆数）である。したがって、Ｖ_GS＝０でもサブスレッショルド電流

が流れる。図４９のＣＭＯＳインバータでオフ状態のトランジスタはＶ_GS＝０であるから、非動作時において高電源電圧Ｖ_CCから接地電位である低電源電圧Ｖ_SSに向かって上記の電流Ｉ_Lが流れることになる。 As shown in FIG. 50, the drain current I _DS in the subthreshold region is proportional to an exponential function of the gate-source voltage V _GS, it is expressed by the following equation.

Where W is the channel width of the MOS transistor, I ₀ and W ₀ are the current value and channel width when defining V _T , and S is the tailing coefficient (the reciprocal of the slope of the V _GS -log I _DS characteristic). Therefore, even if V _GS = 0, the subthreshold current

Flows. Since the off-state transistor in the CMOS inverter of FIG. 49 has V _GS = 0, the current I _L flows from the high power supply voltage V _CC toward the low power supply voltage V _SS , which is the ground potential, when not operating. Become.

The subthreshold current, as shown in FIG. 50, 'Lowering the, I _L from I _L' V _T the threshold voltage from V _T exponentially increases in the.

As is clear from the above equation, in order to reduce the subthreshold current, V _T may be increased or S may be decreased. However, the former causes a decrease in speed due to a decrease in effective gate voltage. In particular, if the operating voltage is lowered along with miniaturization from the point of withstand voltage, the speed drop becomes remarkable, and the advantage of miniaturization cannot be utilized, which is not preferable. The latter is difficult for the following reasons as long as room temperature operation is assumed.

ここで、ｋはボルツマン定数、Ｔは絶対温度、ｑは素電荷である。上式から明らかなように、Ｃ_OXおよびＣ_Dの如何にかかわらずＳ≧ｋＴ ln 10／ｑであり、室温では60ｍＶ以下にすることは困難である。 Tailing factor S is the capacitance C _D of the depletion layer capacitance C _OX and under the gate of the gate insulating film is represented as follows.

Here, k is a Boltzmann constant, T is an absolute temperature, and q is an elementary charge. As is apparent from the above equation, S ≧ kT ln 10 / q regardless of C _OX and C _D , and it is difficult to make it 60 mV or less at room temperature.

Due to the phenomenon described above, the substantial direct current of a semiconductor integrated circuit composed of a large number of MOS transistors increases remarkably. That is, under a constant operating speed, V _T must be reduced as the operating voltage is lowered, so that the more serious the operation is, the lower the voltage is. In particular, during high temperature operation, V _T is low and S is large, so this problem becomes more serious. In the future of downsizing of computers and the like where low power consumption is important, this increase in subthreshold current is an essential problem. In particular, it is extremely important to cope with this increase in current even in an electronic device or the like that is desired to operate with one battery of 0.9 to 1.6V.

1989 International Symposium on VLSI Technology, Systems and Applications, Proceedings on VLSI Technology, Systems and Applications, Proceedings of Technical Papers (May 1989), pages 188-192 of Technical Papers, pp.188-192 (May 1989))

  An object of the present invention is to provide a high-speed and low-power semiconductor integrated circuit even if a MOS transistor is miniaturized, and to realize an electronic device operating at a low voltage such as battery driving with a low current.

  In order to achieve the above object, according to the present invention, a control circuit means for controlling a current supply of a large current and a small current is inserted between the source and the power source of the MOS transistor, and these currents are switched according to the application. Supply to transistor circuit. For example, a large current is supplied when high speed operation is required, and a small current is supplied when low power consumption is required.

  Since high-speed operation is required during normal operation, a large current is supplied from the current supply means to the MOS transistor circuit to enable high-speed operation. At this time, a direct current flows through the MOS transistor circuit as described above. However, the operating current, that is, the charging / discharging current of the load is usually sufficiently small, so that it does not matter.

  On the other hand, since low power consumption is required during standby, the supplied current is switched to a small current to suppress the subthreshold current. At this time, the current is limited, so that the logic amplitude of the MOS transistor circuit is generally smaller than that when a large current is supplied.

  As described above, according to the present invention, a high-speed and low-power consumption MOS transistor circuit and a semiconductor integrated circuit including the same can be realized.

  Hereinafter, specific embodiments of the present invention will be described in more detail with reference to the drawings.

[Example 1]
First, FIG. 1 shows a preferred embodiment for explaining the principle of the present invention.

FIG. 1A is a circuit diagram of an inverter according to an embodiment of the present invention. In the figure, L is a CMOS inverter, which consists of a P-channel MOS transistor _MP and an N-channel MOS transistor _MN . As will be described later, the present invention can be applied not only to an inverter but also to a logic gate or a group of logic gates such as NAND and NOR. Here, for simplicity, the case of an inverter will be described. S _C and S _S are switches, and R _C and R _S are resistors. The feature of this embodiment is that switches S _C , V _SL, and power supplies V _CC , V _SS are respectively connected between the power terminals V _CL , V _SL of the inverter L. This is that S _S and resistors R _C and R _S are inserted in parallel, and as a result, subthreshold current reduction is realized as described below.

In a time zone in which high speed operation is required, the switches S _C and S _S are turned on, and V _CC and V _SS are directly applied to the inverter L (hereinafter referred to as a high speed operation mode). If the threshold voltages (V _T ) of M _P and M _N are set low, high speed operation can be achieved. At this time, as described above, the sub-threshold current flows through the inverter L, but this is not a problem because it is usually sufficiently smaller than the operating current, that is, the charge / discharge current of the load.

On the other hand, in a time zone in which low power consumption is required, the switches S _C and S _S are turned off and power is supplied to the inverter through the resistors R _C and R _S (hereinafter referred to as a low power consumption mode). Due to the voltage drop caused by the subthreshold current flowing through the resistor, V _CL falls below V _CC and V _SL rises above V _SS . As shown in FIG. 2, due to this voltage drop, the subthreshold current is reduced by the following two mechanisms. Although the input signal IN is explained M _N in the case of a low level (V _SS), IN is also M _P in the case of high level (V _CC).

である。これにより、サブスレッショルド電流はＩ_L0からＩ_L1まで減少する。減少率は、

である。ここでＫは基板効果係数である。例えば、Ｖ_M＝0.3Ｖ、Ｋ＝0.4√Ｖ、Ｓ＝100ｍＶ／decade、２ψ＝0.64Ｖならば、サブスレッショルド電流は21％に低減される。 (i) Since the source potential V _SL rises, it takes back gate bias _{V BS = V SS -V SL =} -V M, the threshold voltage increases from V _T0 to V _T1. The increase in threshold voltage is

It is. As a result, the subthreshold current decreases from I _L0 to I _L1 . Decrease rate is

It is. Here, K is a substrate effect coefficient. For example, if V _M = 0.3 V, K = 0.4√V, S = 100 mV / decade, 2ψ = 0.64 V, the subthreshold current is reduced to 21%.

である。例えば、Ｖ_M＝0.3Ｖ、Ｓ＝100ｍＶ／decadeならば、サブスレッショルド電流は０．１％に低減される。 (ii) Since the source potential V _SL rises, the gate-source voltage _{V GS = V SS -V SL =} -V M is negative. As a result, the subthreshold current further decreases from I _L1 to I _L2 . Decrease rate is

It is. For example, if V _M = 0.3 V and S = 100 mV / decade, the subthreshold current is reduced to 0.1%.

となる。例えば、Ｖ_M＝0.3Ｖならば0.02％になる。ここで、Ｖ_Mは方程式

の解である。 Combining the effects of (i) and (ii),

It becomes. For example, if V _M = 0.3V, it becomes 0.02%. Where V _M is the equation

Is the solution.

Note that the back gates of the MOS transistors M _P and M _N of the inverter L may be connected to their respective sources (V _CL , V _SL ), but in order to obtain the effect (i), FIG. Thus, it is preferable to connect to V _CC and V _SS .

FIG. 3 shows the effect of reducing the subthreshold current. Here, assuming an ultra-highly integrated LSI of ultra-low voltage operation in the future, the threshold voltage V _T0 = 0.05 to 0.15 V when the back gate bias is 0, and the total channel width W of the off-state transistors of the entire LSI = Calculated for the case of 100 m. V _M The larger the resistance is increased, the effect is large. In an extreme case, the resistance is infinite, that is, the resistance can be removed.

  However, as shown in FIG. 1B, since the logical amplitude of the output signal OUT is smaller than the logical amplitude of the input signal IN, attention must be paid to the voltage level of the signal in multistage connection. Will be described later.

The present invention also has an effect of automatically compensating for variations in threshold voltage. That is, when the threshold voltage subthreshold current is large low voltage drop V _M due to resistance is increased, when the threshold voltage is high and the subthreshold current is small, V _M becomes smaller. In either case, current fluctuation is suppressed. As is apparent from FIG. 3, the variation in the subthreshold current is smaller as the resistance value is larger. For example, if the resistance value is 3 kΩ or more, even if the threshold voltage varies by ± 0.05 V, the variation of the subthreshold current I _L can be suppressed to within ± 20%.

[Example 2]
Next, a specific method for realizing the switches and resistors described in the first embodiment will be described. FIG. 4 shows an example in which both the switch and the resistor are realized by MOS transistors.

The MOS transistors M _C1 and M _S1 for switching are MOS transistors having a large conductance, and correspond to the switches S _C and S _S in FIG. In the high-speed operation mode, M _C1 and M _S1 are turned on by setting the signal φ _C to a low level and φ _S to a high level. The voltage levels of φ _C and φ _S may be V _SS and V _CC , respectively, but in order to increase the conductance of M _C1 and M _S1 , φ _C is lower than V _SS and φ _S is higher than V _CC. May be higher. The voltage for this purpose may be applied from the outside of the chip or generated by an on-chip booster circuit well known for EEPROM and DRAM.

Conversely, in the low power consumption mode, by setting φ _C to a high level and φ _S to a low level, M _C1 and M _S1 are turned off. At this time, the current must be reliably suppressed. For this purpose, there are the following two methods. The first method is to make φ _C higher than V _CC and φ _S lower than V _SS by an external voltage or an on-chip booster circuit. The second method is to use transistors having higher threshold voltages (more enhanced) than those used for the inverter L as M _C1 and M _S1 . The first method has an advantage that a step for producing transistors having different threshold voltages is unnecessary. On the other hand, the second method is advantageous in terms of area because it does not require a terminal for receiving an external voltage or an on-chip booster circuit.

MOS transistors M _C2 and M _S2 are low conductance MOS transistors and correspond to the resistances R _C and R _S of FIG. These transistors have their gates connected to V _SS and V _CC , respectively, and are always on. Since these transistors need not be turned off, their threshold voltage can be low.

An N channel MOS transistor can be used as M _{C2 and a} P channel MOS transistor can be used as M _S2 . For example, taking an N _C2 N-channel MOS transistor as an example, a resistor having a gate and drain connected to each other is connected to a V _CC terminal, and its source is connected to a V _CL terminal. Can be realized. By adjusting the channel width and threshold voltage of the N-channel MOS transistor, for example, during standby, the voltage of V _CL can be set to a voltage that is lowered from V _{CC by} the threshold voltage of the N-channel MOS transistor, greatly increasing the subthreshold current. Can be reduced.

Next, the time zone to which the present invention is applied will be described. FIG. 5 shows an example of the timing of the signals φ _C and φ _S.

FIGS. 5A and 5B show a case where the present invention is applied to a memory LSI. The memory LSI is in an operating state when the chip enable signal CE (complementary signal), which is an external clock signal, is at a low level, and is in a standby state when it is at a high level. In the case of FIG. 5A, the internal signal φ _C becomes low level in synchronization with the falling edge of CEＣ and becomes high level with a slight delay from the rising edge of CE￣. The internal signal φ _S is the opposite. Accordingly, the time zone a in the figure is the high speed operation mode, and the time zone b is the low power consumption mode. In general, in a memory device using a large number of memory LSIs, a small number of LSIs are in an operating state, and a majority of LSIs are in a standby state. Therefore, if the LSI in the standby state is reduced in power consumption using the present invention, it greatly contributes to the reduction in power consumption of the entire memory device. The reason for providing a delay from the rise of CE to the low power consumption mode is that the internal circuit of the LSI is reset during this period.

  FIG. 5B shows an example of further reducing power consumption. Here, the high-speed operation mode is set only immediately after CE￣ changes. That is, data read / write is performed immediately after CE￣ becomes low level, and internal circuit is reset immediately after CE 高 becomes high level. The mode is set to the low power consumption mode according to the present invention in other time zones. Although not described here, the high-speed operation mode may be entered when the address signal changes.

FIG. 5C shows an example in which the present invention is applied to a microprocessor. In the normal operation state, the clock CLK is applied. At this time, the signal φ _C is at a low level and φ _S is at a high level, which is a high-speed operation mode. When the microprocessor enters a standby state or a data holding state, the clock CLK is stopped and the signal BU goes high. In synchronization with this, φ _C becomes high level, φ _S becomes low level, and a low power consumption mode is set. Thereby, the power consumption of the microprocessor is reduced, and it becomes possible to back up for a long time with a small-capacity power source such as a battery.

FIG. 6 is an example of a device structure for realizing the circuit of FIG. The polysilicons 130, 131, 132 and 133 in this figure correspond to the gates of M _C2 , M _P , M _N and M _S2 in FIG. 4 (M _C1 and M _S1 are not described here).

It should be noted that M _C2 and M _P share the same n-well 101 (connected to V _CC via the n + diffusion layer 120). M _N and M _S2 share a p-substrate (connected to V _SS ) 100 as well. As can be seen, connecting the back gate of the MOS transistor to V _CC and V _SS not only provides the effect of (i) described above, but also in terms of layout area compared to the case of connecting to the source. It is advantageous.

  In the example shown here, the n well is formed in the p substrate, but conversely, the p well may be formed in the n substrate. Alternatively, ISSC, Digest of Technical Papers, 248-249, February 1989 (ISSCC Digest of Technical Papers, pp.248-249, Feb.1989) A triple well structure as described in 1) may be used.

Example 3
FIG. 7 shows another method for realizing a switch and a resistor. The feature of this embodiment is that a current mirror circuit is used. That is, the MOS transistors M _C2 and M _C3 having the same threshold voltage form a so-called current mirror circuit sharing the gate and the source, and a current proportional to the current source I ₀ flows through M _C2 , and its impedance is large. The same applies to M _S2 and M _S3 . Therefore, M _C2 and M _S2 can be regarded as high resistance. The circuit CS composed of the current source I ₀ and M _C3 and M _S3 may be shared by a plurality of logic gates.

  The current mirror circuit is not limited to the circuit shown here, but may be other circuits. For example, a bipolar transistor may be used instead of the MOS transistor.

  As described above, the method of realizing the switch and the resistance can be variously modified. In short, any means may be used as long as it allows a large current to flow during a time zone requiring high-speed operation and a small current to flow during a time zone requiring low power consumption. In the following drawings, for the sake of simplicity, they are represented by switches and resistors as shown in FIG.

Example 4
The back gate of the MOS transistor of the inverter is not limited to V _CC and V _SS, and may be connected to another power source, or its voltage may be variable. An example is shown in FIG. Here, the back gates of M _P and M _N are connected to the power sources V _WW and V _BB , respectively, and their back gate voltage values are changed between during operation and during standby. As for V _BB, the time zone in which high-speed operation is required by shallow V _BB (or in extreme cases slightly positively) that enable high-speed operation by reducing the V _T of M _N. The time zone requiring low power consumption by increasing the V _T of M _N to deepen the V _BB, suppress the subthreshold current. Thereby, the effect of (i) is further increased. Although V _BB has been described above, V _WW is the same _except that the polarity of the voltage is reversed. Note that this type of back gate voltage generation circuit is disclosed in, for example, ISCS, Digest of Technical Papers, pages 254 to 255, February 1985 (ISSCC Digest of Technical Papers). , pp.254-255, Feb.1985).

FIG. 9 is an example of a device structure for realizing the circuit of FIG. Here, the above-described triple well structure is used, and n well 105 (P channel MOS transistor back gate) is connected to V _WW via n + diffusion layer 120, and p well 103 (N channel MOS transistor back gate) is connected. The p + diffusion layer 127 is connected to V _BB .

  This triple well structure has an advantage that a back gate voltage can be set for each circuit because both the P channel and the N channel can be placed in independent wells for each circuit. For example, when a circuit in an operation state and a circuit in a standby state coexist in one LSI, the former back gate voltage can be made shallower and the latter back gate voltage can be made deeper.

Example 5
Next, the case of an inverter train in which inverters are connected in multiple stages will be described. For simplicity, the principle will be described first in the case of two stages.

FIG. 10A is a circuit diagram when CMOS inverters L ₁ and L ₂ are connected. Switches S _Ci and S _Si and resistors R _Ci and R _Si (i = 1, 2) are inserted for each stage of the inverter.

In the high-speed operation mode, all four switches are turned on, and V _CC and V _SS are applied directly to the inverters L ₁ and L ₂ . If the threshold voltage (V _T ) of the inverter MOS transistor is set low, the inverter can be operated at high speed. On the other hand, in the low power consumption mode, all four switches are turned off and power is supplied to the inverter through resistors. Due to the voltage drop caused by the subthreshold current flowing through the resistor, V _CL1 and V _CL2 fall below V _CC , and V _SL1 and V _SL2 rise above V _SS .

For the first-stage inverter L ₁ , the subthreshold current is reduced by the mechanisms (i) and (ii) as in the case of FIG. However, as shown in FIG. 10B, the logical amplitude of the output N ₁ of L ₁ is smaller than the logical amplitude of the input signal IN. That is, when IN is at a low level (= V _SS ), the voltage level of N ₁ is V _CL1 , and when IN is at a high level (= V _CC ), the voltage level of N ₁ is V _SL1 . Since this is the input to the second-stage inverter L ₂ , the resistance value is reduced so that V _CC > V _CL1 > V _CL2 and V _SS <V _SL1 <V _SL2 in order to reduce the subthreshold current of L _2. It is desirable to set. As a result, the subthreshold current also decreases for L ₂ by the mechanisms (i) and (ii). When V _CL1 = V _CL2 and V _SL1 = V _SL2 , the effect (i) is obtained, but the effect (ii) is not obtained.

Example 6
In the case of the multi-stage connection shown in FIG. 11 (a), V _CC > V _CL1 > V _CL2 >......> V _CLk and V _SS <V _SL1 <V _SL2 <...... <V _SLk. It is good to do. However, as shown in FIG. 11 (b), the logic amplitude becomes smaller for each stage, so that the amplitude is restored by inserting a level conversion circuit as appropriate. In this example, a level conversion circuit LC is added after the k-stage inverter so that the logical amplitude of the output signal OUT is the same as that of the input signal IN. This type of level conversion circuit is described in, for example, Symposium on VLSI Circuits, Symposium on VLSI Circuits, Digest of Technical Papers, pages 82-83, June 1992. Digest of Technical Papers, pp.82-83, June 1992).

The level conversion circuit LC is not necessary at high speed operation. Because all the switches are on, V _CL1 = V _CL2 = …… = V _CLk = V _CC , V _SL1 = V _SL2 = …… = V _SLk = V _SS , and there is no decrease in logic amplitude Because. Therefore, during high-speed operation, the delay can be avoided by turning on the switch _SLC to bypass the level conversion circuit.

Example 7
FIG. 12A shows another example of a multistage connected inverter array. In this example, the switches S _C and S _S and the resistors R _C and R _S are shared by all the inverters L _{1 to} L _k, and the voltages V _CL and V _SL are common to L _{1 to} L _k . Therefore, as described in the explanation of FIG. 10, the subthreshold current reduction effect by the mechanism (i) can be obtained, but the effect by (ii) cannot be obtained. Therefore, the subthreshold current reduction effect is smaller than in the previous embodiment.

  However, there is an advantage that the layout area of the switch and the resistor can be saved. Further, as shown in FIG. 12B, all the signals (including the input / output signals) have the same voltage level, and there is a feature that there is no decrease in the logic amplitude as in the previous embodiment. Therefore, there is no need for a level conversion circuit, and there is an advantage that logic such as NAND and NOR can be easily assembled.

Example 8
Next, the case where the present invention is applied to a general combinational logic circuit will be described.

For example, consider the combinational logic circuit shown in FIG. To apply the present invention to this, first, the logic gates are grouped as shown in FIG. In this example, 15 logic gates L _{1 to} L ₁₅ are divided into _three groups G ₁ , G ₂ , and G ₃ . In grouping, the output signals of the logic gates included in the i-th group are input only to the logic gates of the (i + 1) -th and subsequent groups.

Next, as shown in FIG. 14, a switch and a resistor are inserted between each group and the power source. Since the logic amplitude of the output signal of the logic gate becomes smaller for each stage as in the case of FIG. 11, the level conversion circuit groups GC ₁ and GC ₂ are inserted to restore the amplitude as shown in FIG. Although not shown, the level conversion circuit groups GC ₁ and GC ₂ may be bypassed at the time of high-speed operation as in the case of FIG.

One of the features of this embodiment is that logic gates included in the same group share a resistance with a switch. In the example of FIG. 13, the three inverters included in the group G ₁ share the switches S _C1 and S _S1 and the resistors R _C1 and R _S1 .

Another feature of this embodiment is that the switch and the resistor are shared by the groups before and after the level conversion circuit. That is, the groups G ₁ and G _{k + 1} have switches S _C1 and S _S1 and resistors R _C1 and R _S1 , and the groups G ₂ and G _{k + 2} have switches S _C2 and S _S2 and resistors R _C2 and R _S2 . ... Groups G _k and G _2k share switches S _Ck and S _Sk and resistors R _Ck and R _Sk , respectively.

  Thus, by sharing switches and resistors with a plurality of logic gates, the number of switches and resistors can be reduced as a whole LSI, and the layout area can be saved.

Example 9
FIG. 15 shows another embodiment of the present invention. The embodiment of FIG. 15 is different from the preceding examples, a voltage limiter (step-down circuit, a boosting _{circuit) VC 1, VC 2, ......} , VC k, VS 1, VS 2, ......, a VS _k It is to use.

When low power consumption is required, the switches T _{C1 to} T _Ck and T _{S1 to} T _Sk are switched to the illustrated side, and power is supplied to the logic gate group by the voltage limiter. The voltage limiters VC ₁ , VC ₂ ,..., VC _k operate as a step-down circuit on the power supply voltage V _CC side, and are substantially lower than V _{CC and} stabilized by the internal voltages V _CL1 , V _{CL2 ,.} Are generated respectively. _{Meanwhile, VS 1, VS 2, ......} , VS k operates as a boost circuit ground V _SS side, the internal voltage V _SL1 which is substantially stabilized higher than V _SS, V _SL2, ......, a V _SLk Each occurs. Voltage generated is similar to the previous _{embodiment, V CC> V CL1> V} CL2>......> V CLk, V SS <V SL1 <V SL2 <...... < preferably set to V _SLk. This type of voltage limiter is disclosed in Japanese Patent Laid-Open No. 2-246516.

Conversely, when high speed operation is required, the switch is switched to the opposite side to that shown in the figure, and V _CC and V _SS are applied directly to the logic gate group to enable high speed operation. At this time, since the voltage limiter is not necessary, the operation may be stopped.

[Examples 10 and 11]
Although the embodiments so far have been circuits without feedback such as inverter trains and combinational logic circuits, the present invention can also be applied to circuits with feedback. As an example, a case of a latch circuit combining two NAND gates shown in FIG. 16A will be described.

FIG. 16B shows a circuit diagram. Switches S _C1 , S _S1 , S _C2 , S _S2 and resistors R _C1 , R _S1 , R _C2 , R _S2 are inserted between the _two NAND gates L ₁ , L ₂ and the power source Vcc and the ground Vss, respectively. ing. V _CL1 and V _CL2 drop _below V _CC , V _SL1 and V _SL2 rise above V _{SS, and the} subthreshold current is reduced by the mechanism (i).

17, in order to further reduce the subthreshold current, four MOS transistors used in the latch information _{M P12, M P22, M N12} , M threshold voltage V _T of the other MOS transistor M _P11 of _N22, In this example, the threshold voltages of M _P21 , M _N11 and M _N21 are higher (more enhanced). Since the threshold voltages V _T of the other MOS transistors M _P11 , M _P21 , M _N11 , and M _N21 to which the input signal is applied remain low, high speed operation is possible. In this case, a switch and a resistor on the V _SS side are unnecessary. This is because the current can be reliably suppressed by the V _SS side transistors M _N12 and M _{N22 having} a high threshold voltage.

[Examples 12 and 13]
In the embodiments so far, the subthreshold current can be reduced regardless of whether the input signal is at a low level or a high level. However, in an actual LSI, a time zone in which the subthreshold current needs to be reduced, for example, the level of a specific signal in a standby state is often known in advance. In such a case, the subthreshold current can be reduced with a simpler circuit.

FIG. 18 is a circuit example of the inverter train when the input signal IN in the standby state is known to be at a low level (“L”). Since IN is at a low level, nodes N ₁ , N ₃ , N ₅ ,... Are at a high level, N ₂ , N ₄ , N _{6 ,.} M _P4 ,... _Are off, and M _N1 , M _N3,. It is sufficient to insert the switch and resistor only at the source of these off-state transistors. This is because the subthreshold current flows because it is an off-state transistor.

  Further, as shown in FIG. 19, a switch and a resistor may be shared by a plurality of inverters.

  These embodiments have the advantage that the subthreshold current can be reduced with a simple circuit, although there is a restriction that the level of the input signal must be known. As apparent from comparing FIGS. 18 and 19 with FIG. 11, the number of switches and resistors is reduced, and the level conversion circuit is not required.

[Examples 14 and 15]
If not only the inverter but also the logic gates such as NAND and NOR know the level of the input signal in the standby state, the subthreshold current can be reduced with a simpler circuit.

FIG. 20 shows an example of a 2-input NAND gate, and FIG. 21 shows an example of a 2-input NOR gate. When the two input signals IN ₁ and IN ₂ are both at a low level or both are at a high level, these gates are substantially equivalent to inverters, and therefore the method described in FIGS. 18 and 19 can be applied. . The problem is when one input is at a low level (“L”) and the other input is at a high level (“H”) as shown in the figure.

In the case of the NAND gate of FIG. 20, the P-channel MOS transistor M _P12 and the N-channel MOS transistor M _N11 are off, but since the output OUT is at a high level, the subthreshold current flows through M _N11 . Therefore, a switch and a resistor may be inserted on the V _SS side. On the contrary, in the case of the NOR gate of FIG. 21, it is the P-channel MOS transistor M _P14 that the subthreshold current flows. Therefore, a switch and a resistor may be inserted on the V _CC side.

  20 and 21 are examples in which the present invention is applied to a two-input logic gate, but the same can be applied to a logic gate having three or more inputs. Of course, the switch and the resistor may be shared with other logic gates.

Example 16
FIG. 22 shows a circuit example of the clock inverter when it is known that the clock CLK ₁ is at a low level and CLK ₂ is at a high level in a standby state. In this case, since both the MOS transistors M _P16 and M _N16 are off, the output OUT has a high impedance, and its voltage level is determined by another circuit (not shown) connected to OUT. Since the sub-threshold current flows to which of the MOS transistors M _P16 and M _N16 depends on the voltage level, in this case, a switch and a resistor may be inserted on both the V _CC side and the V _SS side as shown in the figure.

Example 17
Even in the case of a general combinational logic circuit, if the level of the input signal is known in advance, the subthreshold current can be reduced with a simpler circuit. The combinational logic circuit shown in FIG. 13 will be described as an example.

FIG. 23 is a circuit configuration example in the case where all the inputs IN _{1 to} IN ₆ of this circuit are known to be at a low level. As for the inverters L _{1 to} L ₃ , L ₅ and L ₆ , switches and resistors are inserted on the V _SS side of L _{1 to} L ₃ and the V _CC side of L ₅ and L ₆ , as in FIGS. . NOR gate L _7, since both the input signal is low, is equivalent to a substantially inverter. Therefore, a switch and a resistor may be inserted on the V _SS side. NOR gate L ₄ are, one low-level input signal, since the other is high, as in FIG. 21, to insert a switch and resistor to V _CC side. Of the eight NAND gates, only L ₁₂ has all three input signals at a high level and is equivalent to an inverter. Therefore, a switch and a resistor are inserted on the V _CC side. Since other NAND gates have both low level and high level input signals, a switch and a resistor may be inserted on the V _SS side as in FIG.

As is clear from the above description, a switch and a resistor may be inserted on the V _SS side for a logic gate whose output is high and on the V _CC side for a logic gate whose output is low. As shown in FIG. 23, the layout area can be saved by sharing these switches and resistors by a plurality of logic gates.

Example 18
Even in a circuit with feedback, if the signal level is known in advance, the subthreshold current can be reduced with a simpler circuit. FIG. 24 shows an example applied to the latch of FIG.

In this type of latch, the input signals IN ₁ and IN ₂ are normally at a high level in a standby state, and one of the output signals OUT ₁ and OUT ₂ is at a low level and the other is at a high level. Information is retained. FIG. 24 shows a circuit configuration example when it is known that OUT ₁ is at a low level and OUT ₂ is at a high level. The NAND gate L ₁ is equivalent to an inverter because the two input signals are both at a high level, and a switch and a resistor are inserted on the V _CC side as in FIGS. NAND gate L _2, while the low level of the input signal, since the other is high, as in FIG. 20, may be inserted switch and resistor to V _SS side. Of course, these switches and resistors may be shared with other logic gates.

Example 19
FIG. 25 shows an example in which the present invention is applied to a well-known data output buffer such as a memory LSI. In the standby state, the output enable signal OE is the low level, the output is high level NAND gate L ₂₁ and L _22, an output of the inverter L ₂₃ is a low level. Thus, the output stage L ₂₄ 2 pieces of MOS transistors M _P20 and M _N20 constituting a are both off, the output DOUT is high impedance.

For logic gates L _{21 to} L ₂₃ , a switch and a resistor may be inserted on the V _SS side or the V _CC side in accordance with the policy described in the explanation of FIG. For the output stage L ₂₄ , as in the case of the clock inverter of FIG. 22, a switch and a resistor may be inserted on both the V _CC side and the V _SS side.

Example 20
FIG. 26 shows an example in which the present invention is applied to a well-known data input buffer such as a memory LSI. In the figure, SB is a signal that becomes high level in the standby state. The outputs of the inverters L ₃₁ and L ₃₂ can be used for controlling the switches as φ _S and φ _C , respectively, as shown in FIGS. L ₃₃ is a NAND gate whose inputs are the phi _S and the data input signal D _IN. Since φ _S is at a low level in the standby state, the output of L ₃₃ is at a high level regardless of D _IN , and therefore the output at the output d _IN of inverter L ₃₄ is at a low level. On the other hand, when the operating state, since SB is low, d _IN follows the D _IN.

For NAND gate L ₃₃ and the inverter L ₃₄ are each V _SS side, by inserting a switch and resistor to VCC side, it can be reduced subthreshold current. Although this method cannot be used for the inverters L ₃₁ and L ₃₂ , the subthreshold current can be reduced by increasing the threshold voltage of the MOS transistor. Since switching between the standby state and the operating state is often not required to be very fast, a MOS transistor having a high threshold voltage may be used.

  Although the data input buffer has been described above, the same applies to the input buffer for address signals and other signals.

Although the embodiments of FIGS. 18 to 25 have the advantage that the subthreshold current can be reduced with a simple circuit, the restriction that the subthreshold current cannot be applied unless the signal level in the standby state, for example, the standby state is known, is known. There is. Therefore, at this time, it is desirable to determine the levels of as many nodes as possible in the LSI. As means for this, by using a circuit such as the input buffer of FIG. 26, the level of the signal d _{IN at} this time can be determined to be low. As another method for determining this level, for example, there is a method of defining a specification that “the data input terminal _DIN is set to a low level (or a high level) in a standby state”.

  The embodiment of FIGS. 18 to 26 is suitable for application to a memory LSI. In the memory LSI, there are a relatively large number of nodes that are known to be at a high level or a low level in a standby state, and the levels of most nodes can be determined by using the input buffer of FIG. .

In a random logic LSI such as a microprocessor, the output of the internal register can be fixed, or logic such as a flip-flop circuit with a reset function can be added to forcibly fix the voltage at the problem node. It is valid. FIG. 35 shows a configuration example of a latch circuit that can fix the output. This circuit has a simple configuration in which an inverter in a normal latch circuit is simply replaced with a NAND circuit. As shown in FIG. 36, during phi _S is high normal to operate the latch circuit, phi _S is between low level (sleep mode) to determine the level of the output signal Q to the high level. Here, the sleep mode is a mode in which the entire LSI or circuit block unit operation is stopped in order to reduce current consumption. Note that if φt is set to a low level and φb is set to a high level during the sleep mode, the subthreshold current of the latch circuit itself can also be reduced. When this latch circuit is used, the node N ₄₁ is forced to be high when φ _S is low, so that the register information is erased in the sleep mode. However, there is no problem in the usage method that saves necessary information in the CPU to the main memory and resumes from the reset state after the sleep mode, for example, the resume function in the standby state when there is no input for a certain time on the notebook personal computer. . FIG. 37 shows another configuration example of a latch circuit capable of forcibly fixing the output. As shown in FIG. 38, this circuit also, during phi _S is high normal to operate the latch circuit, phi _S is between low levels to determine the level of the output signal Q to the high level. Since this latch circuit does not affect the node N ₄₁ even when φ _S goes low, information can be held even during the sleep mode. After the sleep mode is canceled, the state before the sleep mode can be resumed as it is, and the sleep mode can be set even while the CPU is executing the task. Therefore, it is suitable for the case of returning from the sleep mode in a relatively short time.

  25 and 26 can be used not only as an input / output circuit for an external terminal of an LSI chip but also as a driver / receiver for an internal bus of a microprocessor, for example.

Example 21
So far, the embodiment in which the present invention is applied to a CMOS circuit has been described. However, the present invention can also be applied to a circuit composed of a single polarity MOS transistor. FIG. 27 shows an example of a circuit composed of only N-channel MOS transistors. In the figure, PC is a precharge signal, and IN ₁ and IN ₂ are input signals.

In the standby state, that is, in the precharge state, PC is at a high level, IN ₁ and IN ₂ are at a low level, and the output OUT is precharged to a high level (= V _CC −V _T ). In operation, after PC goes low, IN ₁ and IN _{2 go} high or remain low. If at least one of IN ₁ and IN ₂ goes high, OUT goes low, and if both stay low, OUT stays high. In other words, this circuit outputs the NOR of IN ₁ and IN ₂ .

In this circuit, the transistors that are turned off during standby are M _N41 and _N42 on the V _SS side, and a subthreshold current flows through these transistors. Therefore, in order to apply the present invention to this circuit, a switch and a resistor may be inserted on the V _SS side as shown in the figure. It is not necessary on the V _CC side.

  In an LSI or the like that performs a complex operation such as a random logic LSI, for example, the logic (voltage) state of each node in the chip in the standby state is obtained using a design automation (DA) method, and the result is obtained. In response, the position where the switch and the resistor described above are inserted by DA can be automatically determined.

  As described above, the present invention is extremely effective for reducing the power consumption of a MOS transistor circuit and a semiconductor integrated circuit composed thereof. The demand for lower power consumption of semiconductor integrated circuits is particularly strong recently. For example, Nikkei Electronics, September 2, 1991, pages 106 to 111, describes a microprocessor system having a low power backup mode. Yes. In the backup mode, the power consumption is reduced by stopping the clock or stopping the supply of power to unnecessary portions. However, the reduction of the subthreshold current is not taken into consideration. Since these processor systems operate at 3.3-5V, transistors with a sufficiently high threshold voltage can be used, so the subthreshold current is small enough not to be a problem. However, if the operating voltage is lowered to 2V or 1.5V in the future and the threshold voltage has to be lowered, the excessive subthreshold current can no longer be reduced by the method using the conventional CMOS circuit. For example, if the present invention is applied to a resume circuit (power is supplied even in the backup mode), further reduction in power consumption can be realized.

  In the above example, there is a problem that the logic amplitude decreases with an increase in the number of stages, or a slightly complicated design is required when the voltage level of the input signal is not known in advance. FIG. 28 solves these problems. In the time zone required until the logic output is determined, the switch is turned on as described above to perform normal high-speed operation. In other time periods, the subthreshold current path of the logic circuit (shown as an example of a CMOS inverter) is cut off by turning off the switch. However, when the switch is turned off, the supply path for the power supply voltage is cut off, so that the output of the logic circuit becomes floating and the logic output is not fixed. Therefore, the output is provided with a kind of latch circuit (level hold circuit) that holds the voltage level. If a transistor having a high threshold voltage is used for the level hold circuit, the subthreshold current of the level hold circuit becomes so small that it can be ignored, and the subthreshold current can be reduced as a whole. The delay time is less influenced by the level hold circuit and is determined by the logic circuit. Even if a high-speed circuit having a large driving capability is used for the logic circuit, no current flows through the logic circuit in the standby state, so the current consumption is only the current flowing through the level hold circuit. Since the level hold circuit only holds the output, the drive capability may be small and the current consumption can be reduced. Even when the switch is turned off, the output of the logic circuit is held by the level hold circuit, so that there is no fear of the output being inverted and the operation is stable. Therefore, it is possible to realize a semiconductor device that operates stably at high speed with low power consumption. According to the present invention, the voltage level is always guaranteed to a constant value by the level hold circuit, so that the logic amplitude does not decrease as the number of logic stages increases. It is effective regardless of logical input.

This embodiment will be further described with reference to FIG. The logic circuit LC is connected to the high-potential power line VHH and the low-potential power line VLL via the switches SWH and SWL. Here, VHH and VLL can also correspond to V _CC and V _{SS described above} , respectively. A level hold circuit LH is connected to the output terminal OUT of the logic circuit LC. The switches SWH and SWL are controlled by a control pulse CK and are turned on and off at the same time. The logic circuit LC is composed of logic gates such as inverters, NAND circuits, and NOR circuits, flip-flop circuits, or combinations thereof. The level hold circuit LH can be configured by a positive feedback circuit.

  The operation of the logic circuit LC is performed with the switches SWH and SWL turned on. After the output OUT corresponding to the input IN of the logic circuit LC is determined, the switches SWH and SWL are turned off, the current path from VHH to VSS via the logic circuit LC is cut off, and the output of the logic circuit LC is level-held. It is held by the circuit LH.

  The circuit delay time is less affected by the level hold circuit LH and is determined by the logic circuit LC. A high-speed operation with a short delay time can be performed by using a circuit having a large driving capability for the logic circuit LC. For example, since no current flows through the logic circuit LC in the standby state, the consumption current is only the current flowing through the level hold circuit LH. Since the level hold circuit LH may have a small driving capability, the current consumption can be reduced. In addition, since the output OUT of the logic circuit LC is maintained by the level hold circuit LH, there is no risk of malfunction. Therefore, a circuit that operates stably at high speed with low power consumption can be realized.

  An embodiment in which the present invention is applied to a CMOS inverter is shown in FIG. The NMOS transistor MN1 and the PMOS transistor MP1 operate as the switches SWL and SWH in FIG. In order to reduce the leakage current when the transistor is turned off, the threshold voltages of the transistors MN1 and MP1 are sufficiently increased. The channel width / channel length is determined so as not to increase the on-resistance. A control pulse CK is input to the gate of the NMOS transistor MN1, and a control pulse CKB is input to the gate of the PMOS transistor MP1. CKB is a complementary signal of CK. A CMOS inverter INV composed of an NMOS transistor MN2 and a PMOS transistor MP2 is connected to MN1 and MP1. In order to increase the driving capability in the low voltage operation, the threshold voltages of the transistors MN2 and MP2 are decreased. A level hold circuit LH including NMOS transistors MN3 and MN4 and PMOS transistors MP3 and MP4 is connected to the output terminal OUT of the inverter INV. In order to reduce the through current while maintaining the output, the threshold voltages of the transistors MN3, MN4, MP3, and MP4 are sufficiently increased, and the channel width / channel length is sufficiently decreased. Take numerical examples of power supply voltage and threshold voltage. VLL is set to ground potential 0V, and VHH is set to external power supply voltage 1V. The threshold voltage of the NMOS transistor is 0.2V for MN2, and 0.4V for MN1, MN3, and MN4. The threshold voltage of the PMOS transistor is -0.2V for MP2, and -0.4V for MP1, MP3 and MP4.

  The operation will be described with reference to the timing chart shown in FIG. First, the control pulse CK is raised to VHH, CKB is lowered to VLL, the transistors MN1 and MP1 are turned on, and the inverter INV is connected to VHH and VLL. When the input signal IN rises from VLL to VHH, MP2 is turned off and MN2 is turned on, and the output OUT is discharged from VHH to VLL. The transistor MN2 starts to conduct in the saturation region, and a current value flowing through the MN2 is determined by a voltage between the gate (input terminal IN) and the source (node NL). Since the transistor MN1 is provided between the nodes NL and VLL, the potential of the node NL temporarily rises due to the ON resistance of the MN1 and the current flowing from the MN2. However, since the gate of MN1 is VHH, the on-resistance can be designed to be sufficiently small even if the threshold voltage is large, and the influence on the delay time can be reduced. Further, when the output OUT is inverted to VLL, the level hold circuit LH has the MN4 turned off and the MP4 turned on so as to keep the output OUT at VHH. Therefore, when MN2 is turned on, a through current flows from VHH to VLL through MP4 and MN2, but the influence on delay time and current consumption is small by designing the driving capacity of MP4 smaller than that of MN2. When the output OUT decreases, MN3 turns off and MP3 turns on, the node NLH in the level hold circuit is inverted from VLL to VHH, MN4 turns on and MP4 turns off, and the level hold circuit LH outputs the output OUT Is kept at VLL, and no through current flows. MP2 is off because the gate and source are both VHH, but the threshold voltage is small, so that the leakage current is large and the through current flows through the inverter INV. Then, the control pulse CK is lowered to VLL, CKB is raised to VHH, the transistors MN1 and MP1 are turned off, and the inverter INV is separated from VHH and VLL. At this time, MN1 and MP1 are completely turned off because their gates and sources are equipotential and the threshold voltage is large. The output OUT is kept at VHH by the positive feedback of the level hold circuit LH. At this time, since the NMOS transistor MN2 is on, the node NL is kept at VLL. On the other hand, the voltage at the node NH starts to decrease due to the leakage current of the PMOS transistor MP2 from the node NH to the output terminal OUT. Then, MP2 is completely turned off because the source potential is lower than the gate potential. As a result, the through current of the inverter INV does not flow in the standby state. Then, before the input signal IN changes, the control pulse CK is raised to VHH, CKB is lowered to VLL, the transistors MN1 and MP1 are turned on, and the node NH is set to VHH. When the input IN is inverted from VHH to VLL, the output OUT is inverted from VLL to VHH.

  It is desirable that the level hold circuit LH quickly follows the output OUT so that the period during which the through current flows through the inverter INV and the level hold circuit LH is shortened. Therefore, the inverter INV and the level hold circuit LH are arranged close to each other to reduce the wiring delay.

  As is clear from the present embodiment, when the threshold voltage of the MOS transistor used as a switch is set to about 0.4 V or more which has been conventionally required for reducing the subthreshold current, the through current in the standby state can be reduced. Without increasing, the threshold voltage of the MOS transistor in the logic circuit can be reduced. Even if the operating voltage is lowered to 1V or lower, the threshold voltage of the MOS transistor can be reduced to 0.25V or lower to ensure driving capability. Therefore, low power consumption can be realized by reducing the voltage. Moreover, based on the conventional scaling law, the performance improvement by scaling of an element is realizable. Moreover, since the configuration is the same as that of the conventional CMOS logic circuit except that the switch and the level hold circuit are loaded, the same design method as the conventional one can be used.

  FIG. 31 shows an embodiment in which the present invention is applied to a CMOS inverter chain. If a single stage inverter shown in FIG. 29 with two switches and a level hold circuit is connected in multiple stages, an inverter chain can be realized. In this embodiment, the switch and level hold circuit are shared by a plurality of inverters. This is an example in which the number of elements and the area are reduced. Here, the case of a four-stage inverter chain is taken as an example, but the configuration is the same for other stages. Four inverters INV1, INV2, INV3, INV4 are connected in series. The level hold circuit LH is connected to the output terminal OUT of the final stage inverter INV4. Each inverter is composed of one PMOS transistor and one NMOS transistor as in the case of INV in FIG. The transistor size of each inverter may be the same or different. As is often used as a driver, the channel length can be increased in the order of INV1, INV2, INV3, and INV4 between fixed stages with the same channel length. The source of the PMOS transistor of each inverter is connected to the node NH, and the source of the NMOS transistor is connected to the node NL. A switch SWL is provided between the node NL and the low-level power supply VLL, and a switch SWH is provided between the node NH and the high-level power supply VHH. The switches SWL and SWH are controlled by a control pulse CK and are turned on and off at the same time. As shown in FIG. 29, the switch SWL is realized by an NMOS transistor, and SWH is realized by a PMOS transistor in which a complementary signal of CK is inputted to the gate.

  The operation of the inverter chain is performed with the switches SWL and SWH turned on. For example, when the input IN is inverted from the low level VLL to the high level VHH, the inverter INV1 inverts the node N1 from VHH to VLL, INV2 inverts the node N2 from VLL to VHH, and INV3 inverts the node N3 from VHH to VLL. The output terminal OUT is inverted from VLL to VHH by INV4. When OUT is fixed at VHH, the level hold circuit LH operates to keep OUT at VHH. In the standby state, by turning off the switches SWL and SWH, the current path from VHH to VLL via the inverter is interrupted.

  When the present invention is applied to an inverter chain, it is only necessary to provide a level hold circuit only at its output terminal by treating the inverter chain as a single logic circuit as in this embodiment. Further, the switches SWL and SWH can be shared by a plurality of inverters. The magnitudes of the switches SWL and SWH are determined by the magnitude of the flowing peak current. The peak of the current sum flowing through the plurality of inverters is smaller than the sum of the peak currents of the inverters. For example, when an inverter chain is configured with an interstage ratio of 3, the peak of the current sum is substantially the same as the peak current of the final stage. Therefore, sharing the switch among a plurality of inverters requires a smaller switch area than when providing a switch for each inverter.

  FIG. 32 shows another embodiment in which the present invention is applied to an inverter chain. The case of a four-stage inverter chain is taken as an example in the same manner as in FIG. Four inverters INV1, INV2, INV3, INV4 are connected in series. Level hold circuits LH3 and LH4 are connected to an output terminal of the inverter INV3 and a node N3 which is an input terminal of INV4 and an output terminal OUT of INV4, respectively. Each inverter is composed of one PMOS transistor and one NMOS transistor as in the case of INV in FIG. The odd-numbered inverters INV1 and INV3 are connected to the nodes NL1 and NH1, and the even-numbered inverters INV2 and INV4 are connected to the nodes NL2 and NH2. Switches SWL1 and SWL2 are respectively provided between the nodes NL1 and NL2 and the low-level power supply VLL, and switches SWH1 and SWH2 are respectively provided between the nodes NH1 and NH2 and the high-level power supply VHH. The switches SWL1, SWL2 and SWH1, SWH2 are controlled by a control pulse CK and are turned on and off at the same time.

  The operation of the inverter is performed with the switches SWL1, SWL2, SWH1, and SWH2 turned on. For example, when the input IN is inverted from the low level VLL to the high level VHH, the node N1 is changed from VHH to VLL, the node N2 is changed from VLL to VHH, the node N3 is changed from VHH to VLL, and the output terminal OUT is changed from VLL to VHH by INV4. Invert sequentially. When N3 is fixed at VLL, the level hold circuit LH1 operates to keep N3 at VLL. When OUT is fixed at VHH, the level hold circuit LH operates to keep OUT at VHH. For example, in the standby state, by turning off the switches SWL1, SWL2, SWH1, and SWH2, the current path from VHH to VLL via the inverter is interrupted. At this time, since the node N3 is held at the low level VLL by the level hold circuit LH3, the node NL1 is also held at VLL through the inverter INV3. Further, the node N1 is kept at VLL through the inverter INV1. Similarly, when the output terminal OUT is held at the high level VHH by the level hold circuit LH4, the nodes NH2 and N2 are also held at VHH. Therefore, the node connecting the inverters is kept at either VHH or VLL.

  As described above, two sets of switches are provided, the odd-numbered inverters and the even-numbered inverters are connected to different switches, and either one of the output terminals of the odd-numbered inverters and one of the output terminals of the even-numbered inverters Further, by connecting the level hold circuits respectively, the nodes N1, N2, and N3 between the inverters are all kept at either the high level or the low level. Even if the standby state continues for a long time, the input of the inverter does not become an intermediate level, so that the inverter operates stably, and there is no possibility that information is inverted or a through current flows when the switch is turned on.

  Although the present invention has been described with reference to the embodiments in which the present invention is applied to a CMOS inverter and an inverter chain, the purpose of the present invention is to perform stable operation at high speed with low power consumption by loading a switch and a level hold circuit in a logic circuit. Unless it deviates from, it is not limited to the Example described so far.

  For example, another embodiment in which the present invention is applied to a CMOS inverter is shown in FIG. In the embodiment shown in FIG. 29, transistors MN1 and MP2 operating as switches are provided between the CMOS inverter INV and the power supplies VLL and VHH. In contrast, in this embodiment, it is provided between the NMOS transistor and the PMOS transistor.

  Two NMOS transistors MN2 and MN1 and two PMOS transistors MP1 and MP2 are connected in series between a low-level power supply VLL and a high-level power supply VHH. The NMOS transistor MN1 and the PMOS transistor MP1 operate as switches. In order to reduce the leakage current when the transistor is turned off, the threshold voltages of the transistors MN1 and MP1 are increased. A control pulse CK is input to the gate of the NMOS transistor MN1, and a control pulse CKB of a complementary signal of CK is input to the gate of the PMOS transistor MP1. The NMOS transistor MN2 and the PMOS transistor MP2 have gates connected to the input terminal IN and operate as CMOS inverters. In order to increase the driving capability in the low voltage operation, the threshold voltages of the transistors MN1 and MP1 are decreased. A level hold circuit LH configured in the same manner as in FIG. 29 is connected to the output terminal OUT.

  The operation is performed similarly to the embodiment shown in FIG. The transistors MN1 and MP1 are turned on by the control pulses CK and CKB, and the transistors MN2 and MP2 are operated as CMOS inverters. For example, when the input IN is inverted from the low level VLL to the high level VHH, the transistor MN2 that has been turned off until then starts to conduct and operates in the saturation region. At this time, the current value of MN2 is determined by the voltage between the gate and the source. In this embodiment, since the transistor MN1 is provided between MN2 and the output terminal OUT, the on-resistance of MN1 is connected to the drain of MN2. Therefore, the influence of the ON resistance of MN1 on the current value of MN2 is small. After the output OUT is determined, the transistors MN1 and MP1 are turned off to prevent a through current, and the output OUT is maintained by the level hold circuit LH.

  When a switch is inserted on the output terminal side of the logic circuit as in this embodiment, the switch cannot be shared by a plurality of logic gates, but the influence of the on-resistance of the switch is small. When the transistors used as the switches are the same, the delay time is shorter than when the switches are provided on the power supply side of the logic circuit as in the embodiment shown in FIG. Alternatively, if the delay time is designed to be the same, the channel width / channel length of a transistor used as a switch can be reduced, and the area can be reduced.

  FIG. 34 shows another configuration example of the level hold circuit. The case where this level hold circuit is used in place of the level hold circuit LH constituted by NMOS transistors MN3 and MN4 and PMOS transistors MP3 and MP4 in the embodiment shown in FIG. 29 will be described.

  This level hold circuit is composed of three NMOS transistors MN3, MN4, MN5 and PMOS transistors MP3, MP4, MP5, respectively. In order to reduce the leakage current in the standby state, the threshold voltage of each transistor is increased. For example, it is assumed that the NMOS transistor is 0.4V and the PMOS transistor is −0.4V. MN3 and MP3 constitute an inverter, and MN4, MN5, MP4 and MP5 constitute a switching inverter. A control pulse CKB is input to the gate of MN5, and a control pulse CK is input to the gate of MP5. The operation timing is the same as that when the level hold circuit LH shown in FIG. 29 is used, and is as shown in FIG. The control pulse CK is raised to the high level VHH and CKB is lowered to the low level VLL to operate the inverter INV. At this time, the transistors MN5 and MP5 are turned off by the level hold circuit. Therefore, when the output OUT is inverted, no through current flows through the inverter INV and the level hold circuit, and the delay time and current consumption can be reduced. In the standby state, the control pulse CK is lowered to the low level VLL, CKB is raised to the high level VHH, and the inverter INV is disconnected from the power sources VLL and VHH. At this time, in the level hold circuit, the transistors MN5 and MP5 are turned on, and the output OUT is held by positive feedback.

  Thus, by configuring the level hold circuit with a combination of an inverter and a switching inverter, two transistors are added, but the logic circuit and the level hold circuit do not compete with each other, and the delay time and current consumption can be reduced. In addition, the drive capability of the level hold circuit may be increased, and stable operation can be performed without the possibility of fluctuations in output even when the leak at the output terminal is large.

  FIG. 39 shows an embodiment applied to a logic circuit that performs a logic operation with a two-phase clock. In an LSI such as an ordinary microprocessor, most of the logic operations in a chip are often performed in synchronization with a two-phase clock. The logic circuit is divided into LC1 and LC2, and latch circuits LT1 and LT2 controlled by the clocks CK1b and CK2b are added to the respective outputs. In this embodiment, the latch circuits LT1 and LT2 serve as level hold circuits. Here, LC1 and LC2 are combinational logic circuits composed of one logic gate or a plurality of logic gates. Since the two logic circuits LC1 and LC2 operate alternately in synchronization with the clock, the switches SWH1 and SWL1, SWH2 and SWL2 are alternately turned on and off by the clock, and the subthreshold current of the logic circuit that does not operate is cut off. To do. If this embodiment is used, a low-power LSI with a low operating voltage and a small subthreshold current can be realized.

  The operation will be described using the specific circuit example shown in FIG. 40 and the control clock timing shown in FIG. Here, for the sake of simplicity, one inverter is shown as each of the logic circuits LC1 and LC2. Further, although the level hold circuit shown in FIG. 34 is used as the latch circuits LT1 and LT2, the circuit shown in FIG. 29 may be used. The clocks CK1t and CK2t alternately become high level without overlapping each other. The clocks CK1b and CK2b are signals obtained by inverting CK1t and CK2t, respectively. Here, if the threshold voltage of the MOS transistors constituting the logic circuits LC1 and LC2 is lowered, high speed operation is possible. On the other hand, a MOS transistor to which a clock is input to the gate must be able to cut off the subthreshold current when it is off. For this purpose, the threshold voltage is increased, or the high level of the clock is set higher than VHH and the low level is set lower than VLL.

  In the operation mode, the logic circuit LC1 operates while CK1t is at a high level. At this time, since CK2t is at a low level, the latch circuit LT2 holds information to be input to LC1. Since the logic circuit LC2 does not have to operate, the transistors MP12 and MN12 are turned off to cut off the subthreshold current. Conversely, while CK2t is at a high level, LT2 retains information and LC2 operates, so that the subthreshold current of LC1 can be cut off. That is, since either one of the currents LC1 and LC2 can always be cut off, the subthreshold current is half that of the conventional one.

  In recent microprocessors operating from 3.3V to 5V, in order to reduce the power as described above, the application of the clock to unnecessary circuits is stopped in the low power backup mode (sleep mode) and the charge / discharge current. Or reduce it. In this embodiment, as shown in FIG. 41, by setting both the clocks CK1t and CK2t to low level during the sleep mode, the transistors MP11 and MN11, MP12 and MN12 are all turned off, and the logic circuits LC1 and LC2 Both through currents are interrupted. Therefore, the effect of reducing the subthreshold current is even greater in the sleep mode than in the operation mode.

FIG. 42 is a diagram showing another embodiment of the present invention, which is an example applied to a gate array. Since the gate array is a digital logic circuit, it is possible to reduce the subthreshold current by applying the embodiment already shown. However, in general, in a gate array, as described below, when a logic circuit is configured, gates that are deactivated without being used are generated. FIG. 42 (A) shows an example in which the logic shown in (B) is configured in one circuit block of a gate array having a 2-input NAND as a basic cell. Broken lines A001, A002, and A003 in the figure are basic NAND cells. INN1 and OUT1 are the input and output of this logic circuit block, respectively. When an inverter is configured with NAND cells as shown in the figure, it is common practice to fix A004 or A005, which is one of the inputs, to a high level (V _CC ) and deactivate the corresponding gate. ing. This deactivated gate often occurs up to tens of percent of the available gate, so in a low voltage gate array with a scaled transistor threshold voltage, the subthreshold current flowing through the deactivated gate. Cannot be ignored. As shown in the figure, the transistor from V _CC M _C and resistor R _C to the second power supply line V _CL separated via connecting the source of transistor MA01, MA03, high levels phi _C in the power saving mode if the cut-off state M _C in the, transistors MA01, since inter MA03 gate-source is reversed biased deeper cut off, the sub-threshold current of the inactivation gate can be significantly reduced. However, for the active gate, as described above, the logical state of each gate output during a time period where low power consumption is required, for example, standby (high level: “H &# 34 or low level:“ L &# 34 ”in the figure) Correspondingly, if the source of the P channel transistor is connected to V _CC to V _CL and the source of the N channel transistor is connected to V _SL to V _SS , it is a matter of course that leakage current can be prevented. For the inactive gate, it is not necessary to pass a current through the transistor even during operation. Therefore, instead of _VCL , another wiring with a high impedance formed with a minimum wiring width may be used. On the other hand, the transistor M _C is not always necessary, and only the resistor R _C can be used.

FIG. 43 is a diagram showing another embodiment of the present invention, and shows an example in which sub-threshold current prevention according to the present invention is applied to an inactive gate in a gate array having a two-input NOR as a basic cell. This figure shows an example in which the logic shown in FIG. 43B is configured by NOR cells. Broken lines A011, A012, and A013 in the figure are basic NOR cells. When an inverter is constituted by a NOR cell, generally, A014 or A015, which is one of inputs, is fixed to LOW (V _SS ) and the corresponding gate is inactivated. In this case, by connecting the sources of the transistors MA11, MA13 to V _SL, it is possible to make these transistors in a deep cut-off state by the operation to previously described principles, it is possible to prevent the sub-threshold current.

  Further, as the LSI chip becomes larger, it is normal that a test circuit for testing another circuit group is built in the chip. The test circuit can be stopped during normal operation other than during testing. In this case, the embodiments described so far are effective in reducing the subthreshold current of the test circuit.

  An example in which each of the embodiments described above is applied to a single chip microprocessor will be described below. First, a microprocessor with a conventional power reduction mechanism will be described. In conventional microprocessors, power is controlled by controlling the entire chip at once. For example, in the Intel i386SL, the internal circuit is completely static, so that the internal state is maintained even if the clock input to the chip is stopped, and the operation can be resumed by restarting the clock input. Thus, by stopping the input of the clock, the operation of the entire chip is stopped, thereby reducing the power of the entire system. However, this was possible only when the power supply voltage was as high as 3.3 V to 5 V as in the prior art. This is because the threshold voltage of the MOS transistor constituting the CMOS circuit can be as high as about 0.4 to 0.5 V, so that the subthreshold current can be made small enough to be ignored. However, as described above, in a high-speed system that operates with a voltage of one battery such as a power supply voltage of 2 V or less or about 0.9 to 1.6 V, the power can no longer be reduced even if the clock is stopped. In general, in an LSI composed of logic gates mainly composed of random gates, it is said that the number of logic gates in which the input voltage of the logic gates changes among a large number of logic gates in a chip is about 20% of the total. In other 80% logic gates, the input does not change. Fortunately, since the threshold voltage was high in the conventional CMOS circuit, the power of this 80% logic gate was almost negligible, and the entire chip was made low power. However, this can no longer be expected at the power supply voltage. Hereinafter, a microprocessor will be taken as an example of an electronic device in which the entire chip has low power in low power supply voltage operation.

  FIG. 44 shows a single-chip microprocessor incorporating the power reduction mechanism of the present invention. As will be described below, a mechanism for controlling active / standby for each unit is provided within the chip. Reference numeral 600 denotes a single-chip microprocessor. On the microprocessor 600, there are a central processing unit (hereinafter abbreviated as CPU) 601, a coprocessor A (hereinafter abbreviated as COPA) 602, a coprocessor B (hereinafter abbreviated as COPB) 603, a local memory (hereinafter referred to as LM). 604 and a bus control unit (hereinafter abbreviated as BUSC) 605 are incorporated. Each of these units is connected by an internal bus 651 on the chip. Further, the outside of the chip is connected to the external bus 652 via the BUSC 605. A main memory (hereinafter abbreviated as MS) 606, an input / output device (hereinafter abbreviated as IO) 607, and the like are connected to the external bus 652. A CPG 606 is a clock generator, and each unit in the chip operates in synchronization with a clock signal 653 generated from the CPG 606.

  The COPA 602, COPB 603, and LM 604 each have two operating states. One of them is the sleep state. In this state, the operation of each unit is stopped, and the power consumed is extremely small. The other is active. In this state, the unit performs processing such as data read / write operation and arithmetic processing operation. For this reason, power consumption is not suppressed very small. As the logic circuit constituting each of these units, for example, circuits such as FIGS. 18 to 26, FIGS. 28 to 32, and FIGS. 39 to 41 are used. Thereby, power consumption in the sleep state can be reduced. Even in the active state, power can be reduced by finely controlling the activation state for each phase of the two-phase clock using, for example, the circuits of FIGS. MS 606 and IO 607 also have an active / sleep state. Signals 654 and 655 output from the microprocessor 600 are signals that instruct the MS 606 and the IO 607 to be in an active state, respectively.

  The COPA 602 and the COPB 603 are basically the same type of units, and execute a specified operation only when there is an instruction requesting an operation of COPA or COPB in a program executed by the CPU. It becomes active only at this time, and sleep may be performed during other periods. In a normal program, the frequency of this calculation request is not so high. It is characterized by having a large number of register files, dedicated arithmetic units with a large number of transistors (sometimes multiple), and a large number of transistors as a whole.

  The LM 604 is frequently accessed because it stores programs and data required by the CPU. However, in the case where a cache memory is built in the CPU, the processing is performed by closing the CPU, and thus the access frequency is lowered and the sleep period is extended.

  The CPU 601 executes instructions and processes data, and always executes a program (activation rate 100%). The CPU includes basic parts of a normal processor such as general-purpose registers and arithmetic units. Sometimes it includes a cache memory. Instructions and data are stored in the LM 604 or the MS 606. The LM 604 is a small-capacity on-chip memory that can be accessed at high speed, and stores instructions and data frequently used by the CPU 601. Instructions and data that do not need to be accessed so frequently are stored in the MS 606, which has a large capacity but a medium to low speed. The CPU 601 can directly access the LM 604 via the internal bus 651. On the other hand, access to the MS 606 is via the internal bus 651, BUSC 605, and external bus 652. The BUSC 605 includes an external bus buffer having a width of about 32 to 128 bits. It only needs to be active when the CPU accesses a memory or device outside the chip. When programs and data required by the CPU exist in the chip, the sleep state may be used.

  The COPA 602 is a coprocessor that performs multiplication, division, square root, and absolute value calculation, and includes a dedicated arithmetic unit that processes these operations at high speed. The COPB 603 is a coprocessor that executes functional operations such as trigonometric functions and distance calculations, and has a built-in dedicated arithmetic unit that processes these operations at high speed. The CPU 601 starts the operation of each coprocessor by writing a command instructing the requested operation to the command registers CMDA 609 and CMDB 610 in the COPA 602 and COPB 603 via the internal bus 651. Until the calculation is started, each coprocessor is in a sleep state and consumes little power.

  FIG. 45 is an internal configuration diagram of the COPA 602. The interior consists of two blocks ITFA 700 and EXA 701. The ITFA 700 has a command register CMDA609, a command decoder DEC706, operand registers RA702, RB703, RC704, and a control circuit CNT705. The EXA 701 includes a dedicated arithmetic unit that processes multiplication, division, square root, and absolute value calculation at high speed, and a control circuit that controls the dedicated arithmetic unit. The command sent from the CPU 601 via the internal bus 651 is held in the CMDA 609, the command is decoded by the DEC 706, and the EXA 701 is caused to execute the operation designated by the command. There are four types of commands: multiplication, division, square root, and absolute value. Source operands sent from the CPU 601 are stored in the RA 702 and RB 703 as operands for the calculation, and the calculation result is stored in the RC 704 after the calculation ends in the EXA 701 and read from the CPU 601. The EXA 701 is in a sleep state when not performing calculations. When the command is decoded by the DEC 706, a signal for causing the EXA 701 to execute the operation instructed by the command is generated, and the EXA 701 starts the operation. The EXA 701 is in an active state during the execution of the calculation. After completion of the calculation, EXA 701 stores the result in RC 704 and clears CMDA 609 to zero. When the DEC 706 detects that the content of the CMDA 609 is zero and the SLEEP 707 signal is asserted, the EXA 701 enters a sleep state. The CNT 705 controls operations such as read / write and zero clear for the registers 609, 702, 703, and 704. The ITFA 700 is always in an active state in order to always accept commands from the CPU. The clock signal 653 generated from the CPG 606 is used in the ITFA 700. Further, an EXA clock signal 710 is output via the gate circuit 709 and used as a clock for the EXA 701. When SLEEP 707 is asserted, the gate circuit 709 stops the EXA clock 710 so that the clock is not supplied to the EXA 701. Thereby, in the sleep state, the clock of the EXA 701 is also stopped. By this SLEEP signal, for example, the switches of the circuits of FIGS. 18 to 26 or FIGS. 28 to 32 are controlled, and the subthreshold current in the sleep state is reduced.

  The EXA 701 includes a dedicated arithmetic unit, a register for holding a result of the operation, a register for holding an operation state, a latch for operation control, and the like. For these registers and latches, for example, the circuits of FIGS. 35 and 37 are used. In the case of the circuit of FIG. 35, once the sleep state is entered, the state inside the latch is destroyed. On the other hand, in the case of the circuit of FIG. 37, the state inside the latch is not destroyed even when the sleep state is entered. For this reason, once the computer enters the sleep state and then returns to the active state, the arithmetic operation stopped halfway can be resumed.

  The COPB 603 is a coprocessor that executes function operations such as trigonometric functions and distance calculations, but the internal configuration and operation thereof are the same as those of the COPA 602.

  FIG. 46 shows the internal configuration of the LM604. The MEM 901 is a memory unit that stores information such as instructions / data. The MCNT 902 receives an access request from the CPU 601 and performs control to read data stored in the MEM 901 and write data to the MEM 901. When there is an access request from the CPU 601, the MCNT 902 asserts a signal ACT 903 that activates the MEM 901 to put the MEM 901 into an operating state. When there is no access request, the MEM 901 is in the sleep state because the ACT 903 is negated. By this ACT signal, for example, the switches of the circuits of FIGS. 18 to 26 or FIGS. 28 to 32 are controlled, and the subthreshold current in the sleep state is reduced. Even in this state, information is held in the memory. The MCNT 902 is always in an active state in order to always accept an access request from the CPU.

  When the CPU 601 accesses an instruction or data to the MS 606, it passes through the internal bus 651, BUSC 605, and external bus 652. The BUSC 605 becomes active only at this time. FIG. 47 shows the internal configuration of BUSC 605. The BCNT 800 is a circuit that controls access to the external bus 652 in response to a request from the CPU 601. OUTB 801 is a driver circuit that drives the external bus 652 when data flows from the internal bus 651 to the external bus 652, and becomes active only at this time. The INB 802 is a driver circuit that drives the internal bus 651 when data flows from the external bus 652 to the internal bus 651, and becomes active only at this time. When the BCNT 800 receives a write request from the CPU 601 to the MS 606 or the IO 607 outside the chip, the BCNT 800 asserts ACTW 803 to activate the OUTB 801. Conversely, when the BCNT 800 receives a read request from the MS 606 or the IO 607 outside the chip from the CPU 601, the BCNT 800 asserts ACTR 804 to activate the INB 802. Other than these times, OUTB 801 and INB 802 are in a sleep state. The BCNT 800 is always in an active state so that an access request to the outside of the chip can always be accepted. The BCNT 800 also outputs an active support signal 654 for the MS 606 and an active instruction signal 655 for the IO 607. When the CPU 601 makes an access request to the BCNT 800 to the MS 606, the BCNT 800 detects it and asserts the signal 654, and makes the MS 606 active. Signal 655 is also used for similar purposes.

For example, the output buffer circuit shown in FIG. 25 is used for OUTB 801, and switches S _S and S _C are controlled according to the ACTW signal. Since OUTB drives a large load (external bus 652), MOS transistors having a large channel width are required by the number of bus widths (for example, 64 bits), and the total channel width is very large. Therefore, reducing the sub-threshold current of OUTB greatly contributes to the current reduction of the entire system.

  For the INB 802, for example, the input buffer circuit of FIG. 26 is used, and the ACTR signal is supplied to the SB terminal. As a result, the voltage level of the internal bus 651 in the sleep state can be determined. Therefore, for example, the circuits of FIGS. 18 to 25 can be used for the units COPA, COPB, and LM connected to the bus, and the subthreshold current of these units can be easily reduced.

  For example, a DRAM is used for the MS 606. The DRAM may be a normal DRAM, but is described in IEE Spectrum, pages 43 to 49, October 1992 (IEEE Spectrum, pp.43-49, Oct.1992). A synchronous DRAM may be used. In the synchronous DRAM, the clock supply to the chip can be controlled by the clock enable / disable signal, and the current consumption can be effectively reduced by using this signal. That is, the supply of the clock to the chip is stopped in the sleep state. Further, the sub-threshold current of the internal circuit can be reduced by using the circuit of FIG. 26 as an input buffer of the synchronous DRAM and applying a clock enable / disable signal to the SB terminal.

  FIG. 48 shows an operation example of the entire microprocessor 600. The horizontal axis represents time, and the diagonal lines indicate the state in which each unit and each block is active. In this example, the CPU 601 issues a division command to the COPA 602 at time T1, and the COPA 602 executes division from T1 to T2 accordingly, reports the completion of calculation to the CPU 601 at time T2, and enters the sleep state again. Thereafter, the CPU 601 issues a distance calculation command to the COPB 603 at time T3, and the COPB 603 executes distance calculation from T3 to T4 accordingly, reports the completion of calculation to the CPU 601 at time T4, and enters the sleep state again. The LM 604 becomes active only when there is a data access request from the CPU 601. The BUSC 605 is also active only when the CPU 601 accesses the outside. As described above, the power consumption of the microprocessor 600 can be greatly reduced by finely controlling the active / sleep state of each unit and each block within the microprocessor 600.

  The present embodiment is a case where the present invention is applied inside one chip, but it is obvious that this embodiment can be extended to an embodiment of a computer system comprising a plurality of chips. For example, it is easy to apply the present invention in a case where each of the units 601 to 605 in FIG.

It is a figure which shows the inverter of Example 1 of this invention. It is a figure which shows the principle of the subthreshold current reduction by this invention. It is a figure which shows the subthreshold current reduction effect by this invention. It is a circuit diagram of the inverter of Example 2 of this invention. It is a figure which shows the timing of the signal of this invention. It is a figure which shows the device structure of this invention. It is a circuit diagram of the inverter of Example 3 of this invention. It is a circuit diagram of the inverter of Example 4 of this invention. It is a figure which shows the device structure of this invention. It is a figure which shows the inverter row | line of Example 5 of this invention. It is a figure which shows the inverter row | line of Example 6 of this invention. It is a figure which shows the inverter row | line of Example 7 of this invention. It is a figure which shows the example of grouping of the combinational logic circuit to which this invention is applied. It is a figure which shows the combinational logic circuit of Example 8 of this invention. It is a figure which shows the combinational logic circuit of Example 9 of this invention. It is a figure which shows the latch of Example 10 of this invention. It is a circuit diagram of the latch of Example 11 of this invention. It is a circuit diagram of the inverter row | line of Example 12 of this invention. It is a circuit diagram of the inverter row | line of Example 13 of this invention. It is a circuit diagram of the NAND gate of Example 14 of the present invention. It is a circuit diagram of the NOR gate of Example 15 of the present invention. It is a circuit diagram of the clock inverter of Example 16 of this invention. It is a circuit diagram of the combinational logic circuit of Example 17 of this invention. It is a circuit diagram of the latch of Example 18 of this invention. It is a circuit diagram of the output buffer of Example 19 of this invention. It is a circuit diagram of the input buffer of Example 20 of this invention. It is a circuit diagram of the NMOS dynamic circuit of Example 21 of the present invention. FIG. 6 illustrates a conceptual example. It is a circuit diagram of the Example applied to the CMOS inverter. It is an operation | movement timing diagram of the Example applied to the CMOS inverter. It is a figure which shows the Example applied to the inverter chain. It is a figure which shows another Example applied to the inverter chain. It is a figure which shows another Example applied to the CMOS inverter. It is a circuit diagram of another structural example of a level hold circuit. It is a circuit diagram of the latch circuit which can fix an output. It is a timing diagram of a control clock. It is a circuit diagram of the latch circuit which can fix an output. It is a timing diagram of a control clock. It is a figure which shows a two-phase clock logic circuit. It is a circuit diagram of the inverter which operate | moves with a two-phase clock. It is a timing diagram of a control clock. FIG. 3 is a diagram showing a gate array according to the present invention. FIG. 3 is a diagram showing a gate array according to the present invention. 1 is a block diagram of a single chip microprocessor according to the present invention. FIG. It is an internal block diagram of a coprocessor. It is an internal block diagram of a local memory. It is an internal block diagram of a bus control part. It is an operation | movement timing diagram of a microprocessor. It is a circuit diagram of a conventional CMOS inverter. It is a figure which shows the subthreshold characteristic of a MOS transistor.

Explanation of symbols

L, L _{1 to} L _k ... Logic gates G _{1 to} G _k .
S _C , S _{C1 to} S _Ck ,
S _S , S _{S1 to} S _Sk ...... Switches R _C , R _{C1 to} R _Ck , R _S , R _{S1 to} R _Sk ...... resistance

Claims (5)

A first processor;
A second processor including a command decoder and an arithmetic circuit including an arithmetic unit and a holding circuit;
The arithmetic unit includes a logic gate and a switch,
The logic gate includes a first conductivity type first MOS transistor and a second conductivity type second MOS transistor connected in series with a source / drain path of the first MOS transistor, and the source / drain of the first MOS transistor. Configured to obtain an output signal from an output node which is a common connection point between the path and the source / drain path of the second MOS transistor;
The switch includes a third MOS transistor of a first conductivity type, the drain of which is connected to the source of the first MOS transistor,
Setting the control signal supplied to the gate of the third MOS transistor to a first state, thereby turning on the third MOS transistor and allowing the logic gate to operate;
By setting the control signal to a second state different from the first state, the third MOS transistor is turned off to limit a subthreshold current flowing through the logic gate,
The command decoder of the second processor decodes a command from the first processor, causes the arithmetic circuit to execute an operation according to the command, and detects the end of the operation, thereby detecting the end of the second processor. The command decoder asserts the sleep signal,
When the sleep signal is asserted, the control signal is set to the second state, and the holding circuit holds the information. In claim 1,
2. The semiconductor integrated circuit device according to claim 1, wherein the holding circuit is a register for holding an intermediate result of an operation in the arithmetic circuit . In claim 1,
2. The semiconductor integrated circuit device according to claim 1, wherein the holding circuit is a latch for controlling an operation in the arithmetic circuit . In claim 1,
A semiconductor integrated circuit device, wherein a clock signal to the arithmetic circuit is stopped when a sleep signal is asserted to the arithmetic circuit. In any one of Claims 1 thru | or 4,
The holding circuit includes a first inverter circuit, a second inverter circuit, and a NAND circuit,
The input of the first inverter circuit is connected to the output of the logic gate and the output of the second inverter circuit,
The input of the second inverter circuit is connected to the output of the first inverter circuit,
A first input of the NAND circuit is connected to an output of the second inverter circuit;
The control signal is input to the second input of the NAND circuit,
The semiconductor integrated circuit device, wherein an output of the NAND circuit is an output of the register.

Images