JP2004266858A - Semiconductor integrated circuit having electric power reduction mechanism - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit with low power consumption at high speed. <P>SOLUTION: The semiconductor integrated circuit includes an arithmetic circuit (EXA) including registers, the registers maintaining their states even in a sleep state. Further, the semiconductor integrated circuit includes: logic gates connected to the registers; and a control circuit connected to the logic gates, each logic gate includes a first conduction type first MOS transistor and a second conduction type second MOS transistor connected in series, and a connecting point between them is used for an output node. The control circuit is connected to either of the MOS transistors, receives a control signal, allows a first current to flow through one source of the MOS transistors depending on a first state of the control signal, and limits a sub threshold current flowing through the one source of the MOS transistors to a value smaller than the first current according to a second state of the control signal. The semiconductor integrated circuit resumes an arithmetic operation stopped halfway when an active state is restored after the sleep state takes place. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit composed of fine MOS transistors, and more particularly to a circuit suitable for high-speed and low-power operation.

  As described in Non-Patent Document 1, as the breakdown voltage of a MOS transistor is reduced as it is miniaturized, the operating voltage has to be lowered. In particular, the operating voltage of a semiconductor device used in a battery-operated portable device or the like is further reduced in order to reduce power consumption.

In this case, in order to maintain the high-speed operation, it is necessary to lower the threshold voltage (V _T ) of the MOS transistor in accordance with the lowering of the operating voltage. This operating speed, the effective gate voltage of the MOS transistor, that is, ruled by a value obtained by subtracting the V _T from the operating voltage is because fast as this value is larger. For example, according to the above document, the standard value of the threshold voltage of a transistor that operates at 1.5 V with a channel length of 0.25 μm is expected to be 0.35 V. According to a well-known scaling rule, if the operating voltage is 1 V, the standard value of the threshold voltage is about 0.24 V. However, when the V _T below about 0.4V, as described below, by the sub-threshold characteristics of the MOS transistor (tailing characteristics), a phenomenon that transistor completely no longer able longer to turn off the DC current to flow Occurs. Therefore, in an operation of 1.5 V or less, this current becomes a serious problem in practical use.

The conventional CMOS inverter shown in FIG. 49 will be described. Ideally, when the input signal IN is at a low level (= V _SS ), the N-channel MOS transistor M _N is off, and when the input signal IN is at a high level (= V _CC ), the P-channel MOS transistor M _P is off. In any case, no current flows. However, when the V _T of the MOS transistor is lowered, it becomes impossible to ignore the subthreshold characteristic.

ただし、ＷはＭＯＳトランジスタのチャネル幅、Ｉ₀、Ｗ₀はＶ_Tを定義する際の電流値およびチャネル幅、Ｓはテーリング係数（Ｖ_GS-log Ｉ_DS特性の傾きの逆数）である。したがって、Ｖ_GS＝０でもサブスレッショルド電流

が流れる。図４９のＣＭＯＳインバータでオフ状態のトランジスタはＶ_GS＝０であるから、非動作時において高電源電圧Ｖ_CCから接地電位である低電源電圧Ｖ_SSに向かって上記の電流Ｉ_Lが流れることになる。 As shown in FIG. 50, the drain current I _DS in the sub-threshold region is proportional to the exponential function of the gate-source voltage V _GS and is expressed by the following equation.

However, W is the channel width of the MOS transistor, I _0, W ₀ is the current value and the channel width in defining the V _T, S is the tailing factor (inverse of the slope of V _GS -log I _DS characteristics). Therefore, even if V _GS = 0, the subthreshold current

Flows. Since the transistor in the off state in the CMOS inverter of FIG. 49 is a V _GS = 0, that at the time of non-operation is a ground potential from the high supply voltage V _CC toward the low supply voltage V _SS through the above current I _L Become.

The subthreshold current, as shown in FIG. 50, 'Lowering the, I _L from I _L' V _T the threshold voltage from V _T exponentially increases in the.

As is evident from the number 2 in the above equation, in order to reduce the subthreshold current can be reduced or S to increase the V _T. However, the former causes a reduction in speed due to a reduction in the effective gate voltage. In particular, if the operating voltage is reduced along with the miniaturization from the viewpoint of the withstand voltage, the speed drop becomes remarkable, and the advantage of the miniaturization cannot be utilized. The latter is difficult for the following reasons as long as it is operated at room temperature.

ここで、ｋはボルツマン定数、Ｔは絶対温度、ｑは素電荷である。上式から明らかなように、Ｃ_OXおよびＣ_Dの如何にかかわらずＳ≧ｋＴ ln 10／ｑであり、室温では60ｍＶ以下にすることは困難である。 Tailing factor S is the capacitance C _D of the depletion layer capacitance C _OX and under the gate of the gate insulating film is represented as follows.

Here, k is Boltzmann's constant, T is absolute temperature, and q is elementary charge. As is clear from the above formula, S ≧ kT ln 10 / q regardless of C _OX and C _D , and it is difficult to reduce the voltage to 60 mV or less at room temperature.

Due to the phenomena described above, the substantial DC current of a semiconductor integrated circuit composed of a large number of MOS transistors significantly increases. That is, in the original operating speed is constant, since V _T must also be smaller gradually lower the operation voltage becomes serious enough to low-voltage operation. In particular, at the time of high-temperature operation, since _VT is low and S is large, this problem becomes more serious. In the future era of downsizing of computers and the like where low power consumption is important, this increase in subthreshold current is an essential problem. In particular, it is extremely important to cope with this increase in current even in an electronic device or the like that is operated with one battery of 0.9 to 1.6 V.

1989 International Symposium on VLSI Technology, Systems and Applications, Proceedings of Technical Papers (May 1989), 188-192 of Technical Papers, pp.188-192 (May 1989))

  It is an object of the present invention to provide a high-speed and low-power semiconductor integrated circuit even when a MOS transistor is miniaturized, and realize a low-voltage electronic device such as a battery drive with a low current.

  In order to achieve the above object, according to the present invention, a control circuit means for controlling the supply of a large current and a small current is inserted between the source of a MOS transistor and a power supply, and these currents are switched according to the application and the MOS transistor is switched. Supply to transistor circuit. For example, a high current is supplied when high-speed operation is required, and a small current is supplied when low power consumption is required.

  Since high-speed operation is required during normal operation, a large current is supplied from the current supply means to the MOS transistor circuit to enable high-speed operation. At this time, although a DC current flows through the MOS transistor circuit as described above, it is usually sufficient because the DC current is sufficiently smaller than the operating current, that is, the charge / discharge current of the load.

  On the other hand, since low power consumption is required during standby, the supplied current is switched to a small current, and the subthreshold current is suppressed. At this time, since the current is limited, the logic amplitude of the MOS transistor circuit is generally smaller than that when a large current is supplied. However, any logic level can be used as long as the logic level can be guaranteed.

  As described above, according to the present invention, a MOS transistor circuit with high speed and low power consumption and a semiconductor integrated circuit configured with the same can be realized.

  Hereinafter, specific embodiments of the present invention will be described in more detail with reference to the drawings.

[Example 1]
First, FIG. 1 shows a preferred embodiment for explaining the principle of the present invention.

FIG. 1A is a circuit diagram of an inverter according to an embodiment of the present invention. In the figure, L is a CMOS inverter, which comprises a P-channel MOS transistor _MP and an N-channel MOS transistor _MN . As will be described later, the present invention can be applied not only to an inverter but also to a logic gate or a group of logic gates such as a NAND and a NOR. S _C and S _S are switches, R _C and R _S are resistors, and the feature of the present embodiment is that switches S _C , V S are respectively connected between the power supply terminals V _CL , V _SL of the inverter L and the power supplies V _CC , V _SS . That is, S _S and the resistances R _C and R _S are inserted in parallel, so that the sub-threshold current is reduced as described below.

During a time period when high-speed operation is required, the switches S _C and S _S are turned on, and V _CC and V _SS are applied directly to the inverter L (hereinafter, referred to as high-speed operation mode). M _P, by setting a low threshold voltage of M _N (V _T), can be operated at high speed. At this time, the sub-threshold current flows through the inverter L as described above. However, this is not a problem because it is usually sufficiently smaller than the operating current, that is, the charge / discharge current of the load.

On the other hand, during a time period when low power consumption is required, the switches S _C and S _S are turned off, and power is supplied to the inverter through the resistors R _C and R _S (hereinafter referred to as a low power consumption mode). The voltage drop due to the subthreshold current flowing through the resistor causes V _{CL to} drop below V _CC and V _{SL to} rise above V _SS . As shown in FIG. 2, this voltage drop reduces the subthreshold current by the following two mechanisms. Although the input signal IN is explained M _N in the case of a low level (V _SS), IN is also M _P in the case of high level (V _CC).

である。これにより、サブスレッショルド電流はＩ_L0からＩ_L1まで減少する。減少率は、

である。ここでＫは基板効果係数である。例えば、Ｖ_M＝0.3Ｖ、Ｋ＝0.4√Ｖ、Ｓ＝100ｍＶ／decade、２ψ＝0.64Ｖならば、サブスレッショルド電流は21％に低減される。 (i) Since the source potential V _SL rises, the back gate bias V _BS = V _SS -V _SL = -V _M is applied, and the threshold voltage rises from V _T0 to V _T1 . The rise in the threshold voltage is

It is. Thereby, the subthreshold current decreases from _IL0 to _IL1 . The rate of decrease is

It is. Here, K is a substrate effect coefficient. For _{example, V M = 0.3V, K =} 0.4√V, S = 100mV / decade, if 2ψ = 0.64V, subthreshold current is reduced to 21%.

である。例えば、Ｖ_M＝0.3Ｖ、Ｓ＝100ｍＶ／decadeならば、サブスレッショルド電流は０．１％に低減される。 (ii) Since the source potential V _SL rises, the gate-source voltage _{V GS = V SS -V SL =} -V M is negative. This further reduces the subthreshold current from I _L1 to I _L2 . The rate of decrease is

It is. For example, if V _M = 0.3 V and S = 100 mV / decade, the subthreshold current is reduced to 0.1%.

となる。例えば、Ｖ_M＝0.3Ｖならば0.02％になる。ここで、Ｖ_Mは方程式

の解である。 Combining the effects of (i) and (ii),

It becomes. For example, the V _M = 0.3V if 0.02%. Where V _M is the equation

Is the solution.

Incidentally, the back gates of the MOS transistors M _P and M _N of the inverter L may be connected to their respective sources (V _CL and V _SL ), but in order to obtain the effect (i), FIG. It is more desirable to connect to V _CC and V _SS as described above.

FIG. 3 shows a sub-threshold current reduction effect. Here, assuming a future ultra-high-integration LSI with ultra-low-voltage operation, a threshold voltage V _T0 = 0.05 to 0.15 V when the back gate bias is 0, and a total W of channel widths of off-state transistors of the entire LSI = 100m. V _M The larger the resistance is increased, the effect is large. In an extreme case, the resistance can be infinite, that is, the resistance can be eliminated.

  However, as shown in FIG. 1B, since the logical amplitude of the output signal OUT is smaller than the logical amplitude of the input signal IN, it is necessary to pay attention to the signal voltage level in the case of multi-stage connection. Will be described later.

Further, the present invention has an effect of automatically compensating for variations in the threshold voltage. That is, when the threshold voltage subthreshold current is large low voltage drop V _M due to resistance is increased, when the threshold voltage is high and the subthreshold current is small, V _M becomes smaller. In either case, the fluctuation of the current is suppressed. As is clear from FIG. 3, the fluctuation of the subthreshold current is smaller as the resistance value is larger. For example, if the resistance value more than 3 k [Omega, threshold voltage be varied ± 0.05 V, the variation of the sub-threshold current I _L is suppressed to within 20% ±.

[Example 2]
Next, a specific method of realizing the switch and the resistor described in the first embodiment will be described. FIG. 4 shows an example in which both the switch and the resistor are realized by MOS transistors.

The switching MOS transistors M _C1 and M _S1 are MOS transistors having a large conductance, and correspond to the switches S _C and S _S in FIG. 1, respectively. In the high-speed operation mode, M _C1 and M _S1 are turned on by setting the signal φ _C to a low level and setting the signal φ _S to a high level. The voltage levels of φ _C and φ _S may be V _SS and V _CC respectively. However, in order to increase the conductance of M _C1 and M _S1 , φ _C is lower than V _SS and φ _S is lower than V _CC. May be higher. The voltage for this may be supplied from outside the chip, or may be generated by an on-chip booster circuit known in EEPROM and DRAM.

Conversely, in the low power consumption mode, M _C1 and M _S1 are turned off by setting φ _C to a high level and φ _S to a low level. At this time, it must be ensured that the current can be suppressed. For that purpose, there are the following two methods. A first method is to make φ _C higher than V _CC and φ _S lower than V _SS by an external voltage or an on-chip booster circuit. A second method is to use, as M _C1 and M _S1 , transistors whose threshold voltages are higher (more enhanced) than those used in the inverter L. The first method has an advantage that a step for manufacturing transistors having different threshold voltages is unnecessary. On the other hand, the second method is advantageous in terms of area because a terminal for receiving an external voltage or an on-chip booster circuit is not required.

The MOS transistors M _C2 and M _S2 are MOS transistors having a small conductance, and correspond to the resistors R _C and R _S in FIG. 1, respectively. These transistors have their gates connected to V _SS and V _CC , respectively, and are always on. Since these transistors do not need to be turned off, their threshold voltages can be low.

Note that using the N-channel MOS transistor as M _C2, it is also possible to use a P-channel MOS transistor as M _S2. For example, taking an M _C2 N-channel MOS transistor as an example, a terminal whose gate and drain are connected to each other is connected to the V _CC terminal, and its source is connected to the V _CL terminal. Can be realized. By adjusting the channel width and the threshold voltage of the N-channel MOS transistor, for example, during standby, the voltage of V _CL can be set to a voltage lower than V _{CC by} the threshold voltage of the N-channel MOS transistor, and the sub-threshold current can be greatly reduced. Can be reduced.

Next, a time zone to which the present invention is applied will be described. FIG. 5 shows an example of the timing of the signals φ _C and φ _S.

FIGS. 5A and 5B show a case where the present invention is applied to a memory LSI. The memory LSI enters an operation state when a chip enable signal CE # (complementary signal), which is a clock signal from the outside, is at a low level, and enters a standby state when it is at a high level. In the case of FIG. 5A, the internal signal φ _C goes low in synchronization with the fall of CE #, and goes high slightly after the rise of CE #. The internal signal φ _S is the opposite. Accordingly, the time zone a in the figure is the high-speed operation mode, and the time zone b is the low power consumption mode. In general, in a memory device using a large number of memory LSIs, a small number of LSIs are in operation, and the majority of LSIs are in a standby state. Therefore, reducing the power consumption of the LSI in the standby state by using the present invention greatly contributes to the reduction of the power consumption of the entire memory device. The reason why a delay is provided between the rise of CE # and the transition to the low power consumption mode is that the internal circuit of the LSI is reset during this time.

  FIG. 5B shows an example in which power consumption is further reduced. Here, the high-speed operation mode is set only immediately after CE # changes. More specifically, data read / write is performed immediately after CE # goes low, and the internal circuit is reset immediately after CE # goes high. Mode, and the other time zones are the low power consumption mode according to the present invention. Although not described here, the high-speed operation mode may be set when the address signal changes.

FIG. 5C shows an example in which the present invention is applied to a microprocessor. In the normal operation state, the clock CLK is applied. At this time, the signal φ _C is at a low level, and the signal φ _S is at a high level, which is a high-speed operation mode. When the microprocessor enters the standby state or the data holding state, the clock CLK stops and the signal BU goes high. In synchronization with this, φ _C goes high, φ _S goes low, and the device enters the low power consumption mode. As a result, the power consumption of the microprocessor is reduced, and backup can be performed for a long time with a small-capacity power supply such as a battery.

FIG. 6 is an example of a device structure for realizing the circuit of FIG. Polysilicons 130, 131, 132, and 133 in this figure correspond to the gates of M _C2 , M _P , M _N , and M _S2 in FIG. 4, respectively (M _C1 and M _S1 are not described here).

Note that M _C2 and M _P share the same n-well 101 (connected to V _CC via n + diffusion layer 120). M _N and M _S2 also share a p-substrate (connected to V _SS ) 100 as well. As can be seen, connecting the back gate of the MOS transistor to V _cc and V _ss not only achieves the above-mentioned effect (i) but also reduces the layout area compared to the case where the back gate is connected to the source. It is advantageous.

  In the example shown here, the n-well is formed in the p-substrate, but the p-well may be formed in the n-substrate. Or, ISSC, Digest of Technical Papers, pages 248 to 249, February 1989 (ISSCC Digest of Technical Papers, pp.248-249, Feb. 1989). May be used.

[Example 3]
FIG. 7 shows another method of realizing the switch and the resistor. The feature of this embodiment is that a current mirror circuit is used. That is, the MOS transistors M _C2 and M _C3 having the same threshold voltage form a so-called current mirror circuit sharing the gate and the source. A current proportional to the current source I ₀ flows through M _C2 , and the impedance thereof is large. The same applies to _MS2 and _MS3 . Therefore, M _C2 and M _S2 can be regarded as high resistance. The circuit CS including the current source I ₀ and M _C3 and M _S3 may be shared by a plurality of logic gates.

  The current mirror circuit is not limited to the circuit shown here, but may be another circuit. For example, a bipolar transistor may be used instead of a MOS transistor.

  As described above, the method of realizing the switch and the resistor can have various modifications. In short, any means may be used as long as it allows a large current to flow during a time period when high-speed operation is required and a small current during a time period when low power consumption is required. In the following drawings, for simplicity, they are represented by switches and resistors as shown in FIG.

[Example 4]
The back gate of the MOS transistor of the inverter may be connected not only to V _cc and V _ss but also to another power supply, and its voltage may be made variable. FIG. 8 shows an example. Here, the back gates of M _P and M _N are connected to power supplies V _WW and V _BB , respectively, and their back gate voltage values are changed between during operation and during standby. As for V _BB, the time zone in which high-speed operation is required by shallow V _BB (or in extreme cases slightly positively) that enable high-speed operation by reducing the V _T of M _N. The time zone requiring low power consumption by increasing the V _T of M _N to deepen the V _BB, suppress the subthreshold current. As a result, the effect (i) is further enhanced. Although V _BB has been described above, V _WW is the same _except that the polarity of the voltage is reversed. This kind of back gate voltage generating circuit is described in, for example, ISSC, Digest of Technical Papers, pp. 254 to 255, February 1985 (ISSCC Digest of Technical Papers). , pp. 254-255, Feb. 1985).

FIG. 9 is an example of a device structure for realizing the circuit of FIG. Here, the above-described triple well structure is used. The n-well 105 (the back gate of the P-channel MOS transistor) is connected to _VWW via the n + diffusion layer 120, and the p-well 103 (the back gate of the N-channel MOS transistor) is connected. It is connected to V _BB via p + diffusion layer 127.

  This triple well structure has the advantage that the back gate voltage can be set for each circuit because both the P-channel and the N-channel can be placed in independent wells for each circuit. For example, when a circuit in an operating state and a circuit in a standby state are mixed in one LSI, the back gate voltage of the former can be made shallow and the back gate voltage of the latter can be made deep.

[Example 5]
Next, a case of an inverter array in which inverters are connected in multiple stages will be described. For simplicity, the principle will first be described in the case of two stages.

FIG. 10A is a circuit diagram when the CMOS inverters L ₁ and L ₂ are connected. Switches S _Ci and S _Si and resistors R _Ci and R _Si (i = 1, 2) are inserted for each inverter in each stage.

In the high-speed operation mode, all four switches are turned on, and V _CC and V _SS are applied directly to the inverters L ₁ and L ₂ . If the threshold voltage (V _T ) of the MOS transistor of the inverter is set low, high-speed operation can be performed. On the other hand, in the low power consumption mode, all four switches are turned off, and power is supplied to the inverter through a resistor. Due to the voltage drop caused by the flow of the subthreshold current through the resistor, V _CL1 and V _CL2 fall below V _CC , and V _SL1 and V _SL2 rise above V _SS .

The inverter L ₁ of the first stage, as in the case of FIG. 1, the subthreshold current decreases by a mechanism of the (i) (ii). However, as shown in FIG. 10 (b), the logical amplitude of the output N ₁ of L ₁ is smaller than the logical amplitude of the input signal IN. That, IN is the voltage level of the N ₁ is at a low level (= V _SS) becomes V _CL1, IN is the voltage level of the N ₁ is at high level (= V _CC) becomes V _SL1. Because this is the second stage of the input of the inverter L _2, for reducing the subthreshold current of L ₂ is a resistance value such that _{V CC> V CL1> V CL2} , V SS <V SL1 <V SL2 It is desirable to set. As a result, the sub-threshold current of L ₂ is also reduced by the mechanisms (i) and (ii). When V _CL1 = V _CL2 and V _SL1 = V _SL2 , the effect of (i) is obtained but the effect of (ii) is not obtained.

[Example 6]
The same as above when the multistage connection shown in FIG. _{11 (a), V CC>} V CL1> V CL2>......> V CLk, V SS <V SL1 <V SL2 < such that ...... <V _SLk Good to do. However, as shown in FIG. 11B, since the logical amplitude becomes smaller for each stage, an appropriate level conversion circuit is inserted to recover the amplitude. In this example, a level conversion circuit LC is added after the k-stage inverter so that the logical amplitude of the output signal OUT becomes the same as that of the input signal IN. This type of level conversion circuit is disclosed in, for example, Symposium on VLSI Circuits, Digest of Technical Papers, pp. 82-83, June 1992. Digest of Technical Papers, pp. 82-83, June 1992).

The level conversion circuit LC is unnecessary at the time of high-speed operation. Because all switches are on, V _CL1 = V _CL2 =... = V _CLk = V _CC , V _SL1 = V _SL2 =... = V _SLk = V _SS , and there is no decrease in logic amplitude. Because. Therefore, at the time of high-speed operation, the delay can be avoided by turning on the switch _SLC and bypassing the level conversion circuit.

[Example 7]
FIG. 12A shows another example of a multi-stage connected inverter array. In this example, the switches S _C and S _S and the resistances R _C and R _S are shared by all the inverters L _{1 to} L _k, and the voltages V _CL and V _SL are common to L _{1 to} L _k . Therefore, as described in the description of FIG. 10, the sub-threshold current reducing effect by the mechanism (i) can be obtained, but the effect by (ii) cannot be obtained. Therefore, the effect of reducing the sub-threshold current is smaller than in the previous embodiment.

  However, on the other hand, there is an advantage that the layout area of the switch and the resistor can be saved. Further, as shown in FIG. 12B, the voltage levels of all signals (including input / output signals) are the same, and there is a feature that the logic amplitude does not decrease as in the previous embodiment. Therefore, there is an advantage that a level conversion circuit is not required and that logic such as NAND and NOR can be easily assembled.

Example 8
Next, a case where the present invention is applied to a general combinational logic circuit will be described.

For example, consider the combinational logic circuit shown in FIG. To apply the present invention to this, first, logic gates are grouped as shown in FIG. In this example, 15 logic gates L _{1 to} L ₁₅ are divided into _three groups G ₁ , G ₂ and G ₃ . In the grouping, the output signals of the logic gates included in the i-th group are input only to the logic gates in the (i + 1) -th and subsequent groups.

Next, as shown in FIG. 14, a switch and a resistor are inserted between each group and the power supply. Since the logic amplitude of the output signal of the logic gate becomes smaller for each stage, as in the case of FIG. 11, the level conversion circuit groups GC ₁ and GC ₂ are inserted to recover the amplitude as shown in FIG. Although not shown, the level conversion circuit groups GC ₁ and GC ₂ may be bypassed during high-speed operation as in the case of FIG.

One of the features of this embodiment is that the logic gates included in the same group share a resistor with a switch. In the example of FIG. 13, three inverters included in the group G ₁ is shared with the switch S _C1, S _S1 a resistor R _C1, R _S1.

Another feature of this embodiment is that the group before and after the level conversion circuit shares a switch and a resistor. That is, the groups G ₁ and G _{k + 1} include the switches S _C1 and S _S1 and the resistors R _C1 and R _S1 , and the groups G ₂ and G _{k + 2} include the switches S _C2 and S _S2 and the resistors R _C2 and R _S2 , ..., Groups G _k and G _2k share switches S _Ck and S _Sk and resistors R _Ck and R _Sk , respectively.

  As described above, by sharing a switch and a resistor with a plurality of logic gates, the number of switches and resistors can be reduced as a whole LSI, and the layout area can be saved.

[Example 9]
FIG. 15 shows another embodiment of the present invention. The embodiment of FIG. 15 is different from the preceding examples, a voltage limiter (step-down circuit, a boosting _{circuit) VC 1, VC 2, ......} , VC k, VS 1, VS 2, ......, a VS _k It is used.

When low power consumption is required, switches T _{C1 to} T _Ck and T _{S1 to} T _Sk are switched to the illustrated side, and power is supplied to the logic gate group by a voltage limiter. Voltage limiter _{VC 1, VC 2, ......,} VC k , the power supply voltage V _CC side operates as a step-down circuit, the internal voltage V _CL1 that is substantially stabilized lower than V _CC, V _CL2, ......, V _CLk Respectively occur. _{Meanwhile, VS 1, VS 2, ......} , VS k operates as a boost circuit ground V _SS side, the internal voltage V _SL1 which is substantially stabilized higher than V _SS, V _SL2, ......, a V _SLk Each occurs. Voltage generated is similar to the previous _{embodiment, V CC> V CL1> V} CL2>......> V CLk, V SS <V SL1 <V SL2 <...... < preferably set to V _SLk. This type of voltage limiter is disclosed in Japanese Patent Application Laid-Open No. 2-246516.

Conversely, when high-speed operation is required, the switch is switched to the opposite side to that shown in the figure, and V _cc and V _ss are applied directly to the logic gate group to enable high-speed operation. In this case, since the voltage limiter is not required, the operation may be stopped.

[Examples 10 and 11]
Although the embodiments described so far are circuits without feedback, such as an inverter array and a combinational logic circuit, the present invention can also be applied to circuits with feedback. As an example, a case of a latch circuit combining two NAND gates shown in FIG.

FIG. 16B shows a circuit diagram. Switches S _C1 , S _S1 , S _C2 , S _S2 and resistors R _C1 , R _S1 , R _C2 , R _S2 are inserted between the _two NAND gates L ₁ , L ₂ and the power supply Vcc and the ground Vss, respectively. ing. V _CL1 and V _CL2 fall _below V _CC , V _SL1 and V _SL2 rise above V _SS , and the sub-threshold current is reduced by the mechanism (i).

FIG. 17 shows that the threshold voltage V _T of four MOS transistors M _P12 , M _P22 , M _N12 , and M _N22 used for latching information is further reduced by another MOS transistor M _P11 , in order to further reduce the subthreshold current. This is an example in which the threshold voltages of M _P21 , M _N11 , and M _N21 are higher (more enhanced). Since the threshold voltage V _T of the other MOS transistors M _P11 , M _P21 , M _N11 , M _N21 to which the input signal is applied remains low, high-speed operation is possible. In this case, a switch and a resistor on the _VSS side are unnecessary. This is because the current can be reliably suppressed by the V _SS side transistors M _N12 and M _{N22 having} a high threshold voltage.

[Examples 12 and 13]
In the embodiments described above, the subthreshold current can be reduced regardless of whether the input signal is at a low level or a high level. However, in an actual LSI, the time period during which the subthreshold current needs to be reduced, for example, the level of a specific signal in a standby state, is often known in advance. In such a case, the subthreshold current can be reduced with a simpler circuit.

FIG. 18 is a circuit example of an inverter array when it is known that the input signal IN in the standby state is at a low level (“L”). Since IN is at a low level, the nodes N ₁ , N ₃ , N ₅ ,... Are at a high level, N ₂ , N ₄ , N _{6 ,. Are} off, and among the N-channel MOS transistors, M _N1 , M _N3 ,... _Are off. The switches and resistors need only be inserted at the sources of these off transistors. The reason why the subthreshold current flows is that the transistor is in an off state.

  Further, as shown in FIG. 19, a switch and a resistor may be shared by a plurality of inverters.

  These embodiments have the limitation that the level of the input signal must be known, but have the advantage that the subthreshold current can be reduced with a simple circuit. As is apparent from a comparison of FIGS. 18 and 19 with FIG. 11, the number of switches and resistors is reduced, and a level conversion circuit becomes unnecessary.

[Examples 14 and 15]
If the level of the input signal in the standby state is known not only for the inverter but also for the logic gates such as NAND and NOR, the subthreshold current can be reduced with a simpler circuit.

FIG. 20 shows an example of a two-input NAND gate, and FIG. 21 shows an example of a two-input NOR gate. When the two input signals IN ₁ and IN ₂ are both at a low level or at a high level, these gates are substantially equivalent to an inverter, so that the method described with reference to FIGS. 18 and 19 can be applied. . The problem is when one input is low ("L") and the other input is high ("H") as shown.

In the case of the NAND gate of FIG. 20, although the P-channel MOS transistor M _P12 and the N-channel MOS transistor M _N11 are off, the output OUT is at a high level, so that the sub-threshold current flows through M _N11 . Therefore, a switch and a resistor may be inserted on the _VSS side. Conversely, in the case of the NOR gate shown in FIG. 21, it is the P-channel MOS transistor M _P14 through which the subthreshold current flows. Therefore, a switch and a resistor may be inserted on the V _CC side.

  20 and 21 show examples in which the present invention is applied to a two-input logic gate, but the same can be applied to a logic gate having three or more inputs. Also, the switch and the resistor may be shared with other logic gates.

[Example 16]
Figure 22 is the clock inverter, the clock CLK ₁ in the standby state is a circuit example in which known to be low, CLK ₂ is at the high level. In this case, since both the MOS transistors M _P16 and M _N16 are off, the output OUT has a high impedance, and its voltage level is determined by another circuit (not shown) connected to OUT. Since the voltage level determines which of the MOS transistors M _P16 and M _N16 the subthreshold current flows, in this case, a switch and a resistor may be inserted on both the V _CC side and the V _SS side as shown in the figure.

[Example 17]
Also in the case of a general combinational logic circuit, if the level of the input signal is known in advance, the subthreshold current can be reduced by a simpler circuit. Description will be made by taking the combinational logic circuit shown in FIG. 13 as an example.

FIG. 23 is an example of a circuit configuration in the case where all of the inputs IN _{1 to} IN ₆ of this circuit are known to be at a low level. As for the inverters L _{1 to} L ₃ , L ₅ and L ₆ , similarly to FIGS. 18 and 19, switches and resistors are inserted on the V _SS side of L _{1 to} L ₃ and the V _CC side of L ₅ and L _6. . NOR gate L _7, since both the input signal is low, is equivalent to a substantially inverter. Therefore, a switch and a resistor may be inserted on the _VSS side. NOR gate L ₄ are, one low-level input signal, since the other is high, as in FIG. 21, to insert a switch and resistor to V _CC side. Of the eight NAND gates, only L ₁₂ is a high-level all three input signals, since an inverter equivalent, inserting a switch and resistor to V _CC side. In other NAND gates, a low-level signal and a high-level signal are mixed in the input signal. Therefore, as in FIG. 20, a switch and a resistor may be inserted on the _VSS side.

As is apparent from the above description, a switch and a resistor may be inserted on the V _SS side for a logic gate having a high output level and on the V _CC side for a logic gate having a low output level. As shown in FIG. 23, the layout area can be saved by sharing these switches and resistors among a plurality of logic gates.

[Example 18]
Even for a circuit having feedback, if the signal level is known in advance, the subthreshold current can be reduced with a simpler circuit. FIG. 24 is an example applied to the latch of FIG.

In a latch of this type, normally, in a standby state, both the input signals IN ₁ and IN ₂ are at a high level, one of the output signals OUT ₁ and OUT ₂ is at a low level, and the other is at a high level, so that one bit is output. Holds information. Figure 24 is a circuit configuration example when OUT ₁ is known as a low level, OUT ₂ is at a high level. NAND gate L _1, since two input signals are both at a high level, an inverter equivalent, 18, similarly to FIG. 19, to insert a switch and resistor to V _CC side. NAND gate L _2, while the low level of the input signal, since the other is high, as in FIG. 20, may be inserted switch and resistor to V _SS side. Of course, these switches and resistors may be shared with other logic gates.

[Example 19]
FIG. 25 shows an example in which the present invention is applied to a well-known data output buffer such as a memory LSI. In the standby state, the output enable signal OE is the low level, the output is high level NAND gate L ₂₁ and L _22, an output of the inverter L ₂₃ is a low level. Therefore, the two MOS transistors M _P20 and M _N20 forming the output stage L ₂₄ are both off, and the output DOUT is high impedance.

The logic gate L ₂₁ ~L _23, in accordance with policies set forth in the description of Figure 23, the V _SS side or V _CC side may be inserted switch and a resistor. The output stage L _24, similarly to the case of the clock inverter of Figure 22, may be inserted switch and resistor V _CC side, both V _SS side.

[Example 20]
FIG. 26 shows an example in which the present invention is applied to a well-known data input buffer such as a memory LSI. In the figure, SB is a signal that goes high in the standby state. The output of the inverter L ₃₁ and L ₃₂ are, as shown in FIGS. 4 and 7, can be used to phi _S, switch control of the phi _C, respectively. L ₃₃ is a NAND gate whose inputs are the phi _S and the data input signal D _IN. Since φ _S is at the low level in the standby state, the output of L ₃₃ is at the high level regardless of D _IN , and therefore the output of the output d _IN of the inverter L ₃₄ is at the low level. On the other hand, in the operating state, d _IN follows D _IN because SB is at a low level.

For NAND gate L ₃₃ and the inverter L ₃₄ are each V _SS side, by inserting a switch and resistor to VCC side, it can be reduced subthreshold current. For inverter L ₃₁ and L ₃₂ is not used this approach, by increasing the threshold voltage of the MOS transistor, it can be reduced subthreshold current. Since switching between the standby state and the operation state does not often require a high speed, a MOS transistor having a high threshold voltage may be used.

  Although the data input buffer has been described above, the same applies to the input buffers for address signals and other signals.

The embodiments of FIGS. 18 to 25 have the advantage that the sub-threshold current can be reduced with a simple circuit, but cannot be applied unless the signal level in the standby state is known, for example, during the time period when the sub-threshold current reduction is required. There is. Therefore, at this time, it is desirable to determine the levels of as many nodes as possible in the LSI. As a means for achieving this, the level of the signal d _{IN at} this time can be determined to be low by using a circuit such as the input buffer in FIG. As another method for determining this level, for example, there is also a method of setting a specification that “the data input terminal D _IN is set to a low level (or a high level) in a standby state”.

  The embodiments of FIGS. 18 to 26 are suitable for application to a memory LSI. This is because, in the memory LSI, there are relatively many nodes that are known to be at the high level or the low level in the standby state, and the levels of most nodes can be determined by using the input buffer of FIG. .

In a random logic LSI such as a microprocessor, the output of an internal register may be fixed, or the logic of a flip-flop circuit with a reset function may be added to forcibly fix the voltage of a problematic node. It is valid. FIG. 35 shows a configuration example of a latch circuit capable of fixing an output. This circuit has a simple configuration in which an inverter in a normal latch circuit is replaced with a NAND circuit. As shown in FIG. 36, while φ _S is at a high level, the circuit operates as a normal latch circuit, and while φ _S is at a low level (sleep mode), the level of the output signal Q is fixed at a high level. Here, the sleep mode is a mode in which the operation of the entire LSI or a circuit block is stopped in order to reduce current consumption. If φt is set at a low level and φb is set at a high level during the sleep mode, the subthreshold current of the latch circuit itself can be reduced. When using the latch circuits, phi _S is because the node N ₄₁ by becoming to the low level is forced to high level, the information of the register is cleared by the sleep mode. However, there is no problem in a method of saving necessary information in the CPU to the main memory and resuming from the reset state after the sleep mode, for example, a resume function for setting a notebook computer to a standby state when there is no input for a predetermined time. . FIG. 37 shows another configuration example of the latch circuit that can forcibly fix the output. As shown in FIG. 38, this circuit also operates as a normal latch circuit while φ _S is at a high level, and fixes the level of output signal Q to a high level while φ _S is at a low level. The latch circuit, phi _{because S} does not affect the node N ₄₁ be in a low level, can hold also information during the sleep mode. After the sleep mode is released, the sleep mode can be resumed from the state before the sleep mode, and the sleep mode can be set even while the CPU is executing the task. Therefore, it is suitable when returning from the sleep mode in a relatively short time.

  25 and 26 can be used not only as an input / output circuit for external terminals of an LSI chip, but also as a driver / receiver for an internal bus of a microprocessor, for example.

[Example 21]
Although the embodiment in which the present invention is applied to a CMOS circuit has been described above, the present invention can also be applied to a circuit including a MOS transistor having a single polarity. FIG. 27 shows an example of a circuit including only N-channel MOS transistors. In the figure, PC is a precharge signal, and IN ₁ and IN ₂ are input signals.

Standby, i.e. in the precharge state, PC is high, IN ₁ and IN ₂ are at a low level, the output OUT is precharged to a high level (= V _CC -V _T). In operation, after the PC becomes low level, IN ₁ and IN ₂ remains at or low level becomes the high level. If at least one of the IN ₁ and IN ₂ are at a high level, OUT goes low, if you stay in both low and OUT remains high. That is, this circuit is a circuit that outputs NOR of IN ₁ and IN ₂ .

In this circuit, the transistors that are off during standby are M _N41 and N ₄₂ on the V _SS side, and a subthreshold current flows through these transistors. Therefore, to apply the present invention to this circuit, a switch and a resistor may be inserted on the _VSS side as shown in the figure. It is not needed on the V _CC side.

  In an LSI or the like that performs a complicated operation such as a random logic LSI, for example, the logic (voltage) state of each node in the chip in a standby state is obtained by using the design automation (DA) method, and the result is obtained. Accordingly, the position where the above-described switch and resistor are inserted can be automatically determined by DA.

  As described above, the present invention is extremely effective in reducing the power consumption of a MOS transistor circuit and a semiconductor integrated circuit constituted by the MOS transistor circuit. The demand for lowering the power consumption of semiconductor integrated circuits is particularly strong recently. For example, in Nikkei Electronics, September 2, 1991, pages 106 to 111, a microprocessor system having a low power backup mode is described. I have. In the backup mode, the clock is stopped or the power supply to unnecessary parts is stopped to reduce power consumption. However, reduction of the subthreshold current is not considered. Subthreshold currents are negligibly small because these processor systems operate at 3.3-5V and use transistors with sufficiently high threshold voltages. However, if the operating voltage is reduced to 2 V or 1.5 V in the future and the threshold voltage has to be reduced, the excessive sub-threshold current can no longer be reduced by using the conventional CMOS circuit. If the present invention is applied to, for example, a resume circuit (power is supplied even in the backup mode), further reduction in power consumption can be realized.

  In the above example, there are problems that the logic amplitude decreases with an increase in the number of stages, and that a somewhat complicated design is required when the voltage level of the input signal is not known in advance. FIG. 28 solves these problems. In the time period required for the logical output to be determined, the switch is turned on and the normal high-speed operation is performed as described above. In other time zones, the switch is turned off to cut off the subthreshold current path of the logic circuit (the example is a CMOS inverter). However, when the switch is turned off, the supply path of the power supply voltage is cut off, so that the output of the logic circuit becomes floating and the logic output is not determined. Therefore, a feature is that a kind of latch circuit (level hold circuit) for holding a voltage level is provided at the output. If a high threshold voltage transistor or the like is used for the level hold circuit, the sub-threshold current of the level hold circuit can be reduced to a negligible level, and the sub-threshold current can be reduced as a whole. The delay time is less affected by the level hold circuit and is determined by the logic circuit. Even when a high-speed circuit having a large driving capability is used for the logic circuit, current does not flow through the logic circuit in the standby state, so that the consumption current is only the current flowing through the level hold circuit. Since the level hold circuit only holds the output, the driving capability may be small, and the current consumption can be reduced. Even when the switch is turned off, the output of the logic circuit is held by the level hold circuit, so that there is no possibility that the output is inverted and the operation is stable. Therefore, a semiconductor device that performs stable operation at high speed with low power consumption can be realized. According to the present invention, the voltage level is always guaranteed to be a constant value by the level hold circuit, so that the logic amplitude does not decrease as the number of logic stages increases. In addition, it is effective regardless of the logic input.

This embodiment will be further described with reference to FIG. The logic circuit LC is connected to the high-potential power supply line VHH and the low-potential power supply line VLL via the switches SWH and SWL. Here, VHH and VLL can also correspond to V _CC and V _{SS described above} , respectively. The level hold circuit LH is connected to the output terminal OUT of the logic circuit LC. The switches SWH and SWL are controlled by a control pulse CK, and are turned on and off at the same time. The logic circuit LC is configured by logic gates and flip-flop circuits such as an inverter, a NAND circuit, and a NOR circuit, or a combination of a plurality of them. The level hold circuit LH can be constituted by a positive feedback circuit.

  The operation of the logic circuit LC is performed by turning on the switches SWH and SWL. After the output OUT corresponding to the input IN of the logic circuit LC is determined, the switches SWH and SWL are turned off, the current path from VHH to VSS via the logic circuit LC is cut off, and the output of the logic circuit LC is level-held. It is held by the circuit LH.

  The effect of the level hold circuit LH on the delay time of the circuit is small and is determined by the logic circuit LC. A high-speed operation with a short delay time can be performed by using a circuit having a large driving capability for the logic circuit LC. For example, in the standby state, no current flows through the logic circuit LC, so that the consumed current is only the current flowing through the level hold circuit LH. Since the level hold circuit LH may have a small driving capability, current consumption can be reduced. Moreover, since the output OUT of the logic circuit LC is maintained by the level hold circuit LH, there is no possibility of malfunction. Therefore, a circuit that performs stable operation at high speed with low power consumption can be realized.

  FIG. 29 shows an embodiment in which the present invention is applied to a CMOS inverter. The NMOS transistor MN1 and the PMOS transistor MP1 operate as switches SWL and SWH in FIG. 28, respectively. In order to reduce the leakage current when turned off, the threshold voltages of the transistors MN1 and MP1 are set sufficiently high. The channel width / channel length is determined so that the on-resistance does not increase. The control pulse CK is input to the gate of the NMOS transistor MN1, and the control pulse CKB is input to the gate of the PMOS transistor MP1. CKB is a complementary signal of CK. A CMOS inverter INV including an NMOS transistor MN2 and a PMOS transistor MP2 is connected to MN1 and MP1. The threshold voltage of the transistors MN2 and MP2 is reduced in order to increase the driving capability at low voltage operation. The output terminal OUT of the inverter INV is connected to a level hold circuit LH including NMOS transistors MN3 and MN4 and PMOS transistors MP3 and MP4. In order to reduce the through current while holding the output, the threshold voltages of the transistors MN3, MN4, MP3, and MP4 are made sufficiently large, and the channel width / channel length is made sufficiently small. Numerical examples of the power supply voltage and the threshold voltage will be described. VLL is set to the ground potential 0V, and VHH is set to the external power supply voltage 1V. The threshold voltage of the NMOS transistor is 0.2 V for MN2, and 0.4 V for MN1, MN3 and MN4. The threshold voltage of the PMOS transistor is -0.2V for MP2, and -0.4V for MP1, MP3 and MP4.

  The operation will be described with reference to the timing chart shown in FIG. First, the control pulse CK is raised to VHH, CKB is lowered to VLL, the transistors MN1 and MP1 are turned on, and the inverter INV is connected to VHH and VLL. When the input signal IN rises from VLL to VHH, MP2 turns off and MN2 turns on, and the output OUT is discharged from VHH to VLL. The transistor MN2 starts to conduct in the saturation region, and the value of the current flowing through MN2 is determined by the voltage between the gate (input terminal IN) and the source (node NL). Since the transistor MN1 is provided between the node NL and VLL, the potential of the node NL temporarily increases due to the on-resistance of MN1 and the current flowing from MN2. However, since the gate of MN1 is at VHH, the on-resistance can be designed to be sufficiently small even if the threshold voltage is large, and the effect on the delay time can be reduced. When the output OUT is inverted to VLL, the level hold circuit LH turns off MN4 and turns on MP4 so as to keep the output OUT at VHH. Therefore, when MN2 is turned on, a through current flows from VHH to VLL through MP4 and MN2. However, the influence on delay time and current consumption is small by designing the driving capability of MP4 smaller than that of MN2. When the output OUT falls, MN3 turns off and MP3 turns on, the node NLH in the level hold circuit is inverted from VLL to VHH, MN4 turns on and MP4 turns off, and the level hold circuit LH turns off the output OUT. Is maintained at VLL, and no through current flows. MP2 is off because both the gate and the source are VHH. However, since the threshold voltage is small, a large leak current flows through the inverter INV. Then, the control pulse CK is lowered to VLL, CKB is raised to VHH, the transistors MN1 and MP1 are turned off, and the inverter INV is separated from VHH and VLL. At this time, MN1 and MP1 are completely turned off because the gate and the source have the same potential and the threshold voltage is large. The output OUT is maintained at VHH by the positive feedback of the level hold circuit LH. At this time, since the NMOS transistor MN2 is on, the node NL is kept at VLL. On the other hand, the voltage of the node NH starts to decrease due to the leakage current of the PMOS transistor MP2 from the node NH to the output terminal OUT. Then, the source potential of MP2 falls below the gate potential and is completely turned off. As a result, the through current of the inverter INV does not flow in the standby state. Then, before the input signal IN changes, the control pulse CK is raised to VHH, CKB is lowered to VLL, the transistors MN1 and MP1 are turned on, and the node NH is set to VHH. When the input IN is inverted from VHH to VLL, the output OUT is inverted from VLL to VHH.

  It is desirable that the level hold circuit LH quickly follow the output OUT so that the period during which a through current flows through the inverter INV and the level hold circuit LH is shortened. Therefore, the inverter INV and the level hold circuit LH are arranged close to each other to reduce wiring delay.

  As is apparent from the present embodiment, when the threshold voltage of the MOS transistor used as a switch is set to about 0.4 V or more, which is conventionally required to reduce the sub-threshold current, the through current in the standby state is reduced. The threshold voltage of the MOS transistor in the logic circuit can be reduced without increasing the threshold voltage. Even if the operating voltage is lowered to 1 V or less, the driving capability can be ensured by setting the threshold voltage of the MOS transistor to 0.25 V or less. Therefore, lower power consumption due to lower voltage can be realized. In addition, the performance can be improved by scaling the elements based on the conventional scaling rule. In addition, since the configuration is the same as that of the conventional CMOS logic circuit except that a switch and a level hold circuit are loaded, the same design method as that of the conventional CMOS logic circuit can be used.

  FIG. 31 shows an embodiment in which the present invention is applied to a CMOS inverter chain. An inverter chain can be realized by connecting the configuration in which two switches and a level hold circuit are provided to the one-stage inverter shown in FIG. 29 in multiple stages. However, in this embodiment, the switch and the level hold circuit are shared by a plurality of inverters. In this example, the number of elements and the area are reduced. Here, the case of a four-stage inverter chain is taken as an example, but the case of other stages is similarly configured. Four inverters INV1, INV2, INV3, INV4 are connected in series. The level hold circuit LH is connected to the output terminal OUT of the final-stage inverter INV4. Each inverter is composed of one PMOS transistor and one NMOS transistor, similarly to INV in FIG. The transistor size of each inverter may be the same or different. As often used as a driver, the channel length can be made the same and the channel width can be increased in the order of INV1, INV2, INV3, and INV4 between certain stages. The source of the PMOS transistor of each inverter is connected to the node NH, and the source of the NMOS transistor is connected to the node NL. A switch SWL is provided between the node NL and the low-level power supply VLL, and a switch SWH is provided between the node NH and the high-level power supply VHH. The switches SWL and SWH are controlled by a control pulse CK, and are turned on and off at the same time. As shown in FIG. 29, the switch SWL is implemented by an NMOS transistor, and the switch SWH is implemented by a PMOS transistor whose gate receives a complementary signal of CK.

  The operation of the inverter chain is performed by turning on the switches SWL and SWH. For example, when the input IN is inverted from low level VLL to high level VHH, the node N1 is inverted from VHH to VLL by the inverter INV1, the node N2 is inverted from VLL to VHH by INV2, and the node N3 is changed from VHH to VLL by INV3. The output terminal OUT is inverted from VLL to VHH by INV4. When OUT is determined to be VHH, the level hold circuit LH operates to maintain OUT at VHH. In the standby state, the switches SWL and SWH are turned off to cut off the current path from VHH to VLL via the inverter.

  When the present invention is applied to an inverter chain, a level hold circuit may be provided only at its output terminal by treating the inverter chain as one logic circuit as in this embodiment. Further, the switches SWL and SWH can be shared by a plurality of inverters. The size of the switches SWL and SWH is determined by the size of the peak current flowing. The peak of the sum of the currents flowing through the plurality of inverters is smaller than the sum of the peak currents of the inverters. For example, when an inverter chain is configured with an interstage ratio of 3, the peak of the current sum is substantially equal to the peak current of the final stage. Therefore, when a switch is shared by a plurality of inverters, the area of the switch is smaller than when a switch is provided for each inverter.

  FIG. 32 shows another embodiment in which the present invention is applied to an inverter chain. Although the case of a four-stage inverter chain is taken as an example similarly to FIG. 31, the case of other stages is similarly configured. Four inverters INV1, INV2, INV3, INV4 are connected in series. Level hold circuits LH3 and LH4 are connected to a node N3 which is an output terminal of the inverter INV3 and an input terminal of the INV4 and an output terminal OUT of the INV4, respectively. Each inverter is composed of one PMOS transistor and one NMOS transistor, similarly to INV in FIG. Odd-numbered inverters INV1 and INV3 are connected to nodes NL1 and NH1, and even-numbered inverters INV2 and INV4 are connected to nodes NL2 and NH2. Switches SWL1 and SWL2 are provided between the nodes NL1 and NL2 and the low-level power supply VLL, and switches SWH1 and SWH2 are provided between the nodes NH1 and NH2 and the high-level power supply VHH, respectively. The switches SWL1 and SWL2 and the switches SWH1 and SWH2 are controlled by a control pulse CK, and are turned on and off at the same time.

  The operation of the inverter is performed by turning on the switches SWL1, SWL2, SWH1, and SWH2. For example, when the input IN is inverted from the low level VLL to the high level VHH, the node N1 changes from VHH to VLL, the node N2 changes from VLL to VHH, the node N3 changes from VHH to VLL, and the output terminal OUT changes from VLL to VHH by INV4. Invert sequentially. When N3 is determined to be VLL, the level hold circuit LH1 operates to keep N3 at VLL. When OUT is determined to be VHH, the level hold circuit LH operates to maintain OUT at VHH. For example, in the standby state, the switches SWL1, SWL2, SWH1, and SWH2 are turned off to cut off the current path from VHH to VLL via the inverter. At this time, since the node N3 is kept at the low level VLL by the level hold circuit LH3, the node NL1 is also kept at VLL through the inverter INV3. Further, the node N1 is kept at VLL through the inverter INV1. Similarly, when the output terminal OUT is kept at the high level VHH by the level hold circuit LH4, the nodes NH2 and N2 are also kept at VHH. Therefore, the node connecting the inverters is kept at either VHH or VLL.

  As described above, two sets of switches are provided, the odd-numbered inverter and the even-numbered inverter are connected to different switches, and one of the output terminals of the odd-numbered inverter and one of the output terminals of the even-numbered inverter are connected. By connecting a level hold circuit to each of the nodes, all the nodes N1, N2, N3 between the inverters are maintained at either the high level or the low level. Even if the standby state continues for a long time, the input of the inverter does not reach the intermediate level, so that the inverter operates stably and there is no possibility that the information is inverted or a through current flows when the switch is turned on.

  Although the present invention has been described with reference to the embodiment in which the present invention is applied to a CMOS inverter or an inverter chain, the gist of the present invention is to perform high-speed stable operation with low power consumption by loading a switch and a level hold circuit on a logic circuit. The present invention is not limited to the embodiments described so far, as long as they do not deviate from the above.

  For example, another embodiment in which the present invention is applied to a CMOS inverter is shown in FIG. In the embodiment shown in FIG. 29, the transistors MN1 and MP2 operating as switches are provided between the CMOS inverter INV and the power supplies VLL and VHH. On the other hand, in this embodiment, it is provided between the NMOS transistor and the PMOS transistor.

  Two NMOS transistors MN2 and MN1 and two PMOS transistors MP1 and MP2 are connected in series between a low-level power supply VLL and a high-level power supply VHH. The NMOS transistor MN1 and the PMOS transistor MP1 operate as switches. In order to reduce the leakage current when turned off, the threshold voltages of the transistors MN1 and MP1 are increased. The control pulse CK is input to the gate of the NMOS transistor MN1 and the control pulse CKB of the complementary signal of CK is input to the gate of the PMOS transistor MP1. The gates of the NMOS transistor MN2 and the PMOS transistor MP2 are connected to the input terminal IN, and operate as a CMOS inverter. In order to increase the driving capability at low voltage operation, the threshold voltages of the transistors MN1 and MP1 are reduced. The output terminal OUT is connected to a level hold circuit LH configured in the same manner as in FIG.

  The operation is performed in the same manner as in the embodiment shown in FIG. The transistors MN1 and MP1 are turned on by the control pulses CK and CKB, and the transistors MN2 and MP2 are operated as CMOS inverters. For example, when the input IN is inverted from the low level VLL to the high level VHH, the transistor MN2 which has been turned off starts to conduct and operates in the saturation region. At this time, the current value of MN2 is determined by the voltage between the gate and the source. In this embodiment, since the transistor MN1 is provided between MN2 and the output terminal OUT, the ON resistance of MN1 is connected to the drain of MN2. Therefore, the influence of the ON resistance of MN1 on the current value of MN2 is small. After the output OUT is determined, the transistors MN1 and MP1 are turned off to prevent a through current, and the output OUT is maintained by the level hold circuit LH.

  When a switch is inserted on the output terminal side of a logic circuit as in this embodiment, the switch cannot be shared by a plurality of logic gates, but the influence of the on-resistance of the switch is small. When the same transistor is used as the switch, the delay time is shorter than when the switch is provided on the power supply side of the logic circuit as in the embodiment shown in FIG. Alternatively, if the delay time is designed to be the same, the channel width / channel length of the transistor used as a switch can be reduced, and the area can be reduced.

  FIG. 34 shows another configuration example of the level hold circuit. A case where this level hold circuit is replaced with the level hold circuit LH including the NMOS transistors MN3 and MN4 and the PMOS transistors MP3 and MP4 in the embodiment shown in FIG. 29 will be described.

  This level hold circuit includes three NMOS transistors MN3, MN4, MN5 and PMOS transistors MP3, MP4, MP5. In order to reduce the leakage current in the standby state, the threshold voltage of each transistor is increased. For example, the NMOS transistor is set to 0.4V, and the PMOS transistor is set to -0.4V. MN3 and MP3 constitute an inverter, and MN4, MN5, MP4 and MP5 constitute a switching inverter. The control pulse CKB is input to the gate of MN5, and the control pulse CK is input to the gate of MP5. The operation timing is the same as that in the case where the level hold circuit LH shown in FIG. 29 is used, and is as shown in FIG. The control pulse CK is raised to the high level VHH, the CKB is lowered to the low level VLL, and the inverter INV is operated. At this time, the transistors MN5 and MP5 are turned off in the level hold circuit. Therefore, when the output OUT is inverted, no through current flows through the inverter INV and the level hold circuit, and the delay time and the current consumption can be reduced. In the standby state, the control pulse CK is lowered to the low level VLL, the CKB is raised to the high level VHH, and the inverter INV is disconnected from the power supplies VLL and VHH. At this time, in the level hold circuit, the transistors MN5 and MP5 are turned on, and the output OUT is held by positive feedback.

  By configuring the level hold circuit with a combination of an inverter and a switching inverter in this way, the number of transistors increases by two. However, the logic circuit and the level hold circuit do not compete with each other, and the delay time and current consumption can be reduced. In addition, the driving capability of the level hold circuit may be increased, and even if the leakage at the output terminal is large, there is no possibility that the output fluctuates and stable operation can be performed.

  FIG. 39 shows an embodiment applied to a logic circuit that performs a logic operation with a two-phase clock. In an ordinary LSI such as a microprocessor, most of the logic operations in a chip are often performed in synchronization with a two-phase clock. The logic circuit is divided into two circuits, LC1 and LC2, and latch circuits LT1 and LT2 controlled by clocks CK1b and CK2b are added to each output. In this embodiment, the latch circuits LT1 and LT2 play the role of a level hold circuit. Here, LC1 and LC2 are one logic gate or a combination logic circuit composed of a plurality of logic gates. Since the two logic circuits LC1 and LC2 operate alternately in synchronization with the clock, the switches SWH1 and SWL1 and the switches SWH2 and SWL2 are alternately turned on and off by the clock to cut off the subthreshold current of the logic circuit that does not operate. I do. By using this embodiment, a low-power LSI with a low operating voltage and a small subthreshold current can be realized.

  The operation will be described using a specific circuit example shown in FIG. 40 and the timing of the control clock shown in FIG. Here, for simplification, one inverter is shown as each of the logic circuits LC1 and LC2. Although the level hold circuit shown in FIG. 34 is used as the latch circuits LT1 and LT2, the circuit shown in FIG. 29 may be used. The clocks CK1t and CK2t alternately go high without overlapping each other. The clocks CK1b and CK2b are signals obtained by inverting CK1t and CK2t, respectively. Here, if the threshold voltages of the MOS transistors constituting the logic circuits LC1 and LC2 are lowered, high-speed operation is possible. On the other hand, the MOS transistor whose clock is input to the gate must be able to cut off the subthreshold current when it is off. To do so, the threshold voltage may be increased, or the high level of the clock may be higher than VHH and the low level may be lower than VLL.

  In the operation mode, the logic circuit LC1 operates while CK1t is at a high level. At this time, since CK2t is at a low level, the latch circuit LT2 holds information to be input to LC1. Further, since the logic circuit LC2 does not need to perform the operation, the transistors MP12 and MN12 are turned off to cut off the subthreshold current. Conversely, while CK2t is high, LT2 holds information and LC2 operates, so that the subthreshold current of LC1 can be cut off. That is, since either one of the currents LC1 and LC2 can always be cut off, the subthreshold current is reduced to half that of the conventional one.

  As described above, in recent microprocessors operating from 3.3 V to 5 V, in order to reduce power consumption, application of a clock to unnecessary circuits is stopped in a low power backup mode (sleep mode) or the like, and charge / discharge current is reduced. Or to reduce. In this embodiment, as shown in FIG. 41, by setting both the clocks CK1t and CK2t to the low level during the sleep mode, all the transistors MP11 and MN11, MP12 and MN12 are turned off, and the logic circuits LC1 and LC2 are turned off. Both shoot-through currents are interrupted. Therefore, the effect of reducing the sub-threshold current is greater in the sleep mode than in the operation mode.

FIG. 42 is a view showing another embodiment of the present invention, which is an example applied to a gate array. Since the gate array is a digital logic circuit, it is possible to reduce the subthreshold current by applying the embodiment described above. However, generally, in a gate array, as described below, when a logic circuit is formed, a gate which is not used and is inactivated is generated. FIG. 42A shows an example in which the logic shown in FIG. 42B is configured in one circuit block of a gate array using a two-input NAND as a basic cell. In the figure, broken lines A001, A002, and A003 are basic NAND cells. INN1 and OUT1 are the input and output of this logic circuit block, respectively. When an inverter is composed of NAND cells as shown in the figure, it is common practice to fix one of the inputs, A004 or A005, to a high level (V _CC ) and deactivate the corresponding gate. ing. Since this passivated gate often amounts to tens of percent of the available gate, in a low voltage gate array with a scaled transistor threshold voltage, the subthreshold current through the passivated gate is reduced. Cannot be ignored. As shown in the figure, the sources of the transistors MA01 and MA03 are connected to a second power supply line _VCL separated from V _CC via a transistor M _C and a resistor R _C , and φ _{C is set} to a high level in the power saving mode. if the cut-off state M _C in the, transistors MA01, since inter MA03 gate-source is reversed biased deeper cut off, the sub-threshold current of the inactivation gate can be significantly reduced. However, regarding the active gate, as described above, the logic state of each gate output during a time period during which low power consumption is required, for example, during standby (high level in the figure: “H &# 34” or low level: “L &# 34”) Accordingly, if the source of the P-channel transistor is connected to V _CC or V _CL and the source of the N-channel transistor is connected to V _SL or V _SS , the leakage current can of course be prevented. In addition, for the inactive gate, it is not necessary to supply a current to the transistor even during operation. Therefore, instead of V _CL , another high-impedance wiring formed with a minimum wiring width may be used. However, the transistor M _C is not always necessary, and only the resistor R _C can be used.

FIG. 43 is a diagram showing another embodiment of the present invention, in which an inactive gate in a gate array using a two-input NOR as a basic cell is provided with a subthreshold current prevention according to the present invention. This figure shows an example in which the logic shown in FIG. 43B is constituted by NOR cells. In the figure, broken lines A011, A012, and A013 are basic NOR cells. When configuring the inverter NOR cell fixes the one in which A014 and A015 of the input to LOW (V _SS), the corresponding gate can be inactivated it is generally performed. In this case, by connecting the sources of the transistors MA11, MA13 to V _SL, it is possible to make these transistors in a deep cut-off state by the operation to previously described principles, it is possible to prevent the sub-threshold current.

  In addition, as the size of the LSI chip increases, it is common for a test circuit for testing another circuit group to be built in the chip. This test circuit can be stopped during a normal operation other than the test. In this case, in order to reduce the subthreshold current of the test circuit, the embodiments described above are effective.

  An example in which each embodiment described above is applied to a single-chip microprocessor will be described below. First, a microprocessor with a conventional power reduction mechanism will be described. In a conventional microprocessor, power is controlled by controlling the entire chip at once. For example, in the Intel i386SL, since the internal circuit is completely static, the internal state is maintained even when the clock input to the chip is stopped, and the operation can be resumed by restarting the clock input again. As described above, by stopping the input of the clock, the operation of the entire chip is stopped, thereby trying to reduce the power of the entire system. However, this was possible only when the power supply voltage was as high as 3.3 V to 5 V as in the past. This is because the threshold voltage of the MOS transistor constituting the CMOS circuit can be as high as about 0.4 to 0.5 V, so that the subthreshold current can be made negligibly small. However, as described above, in a high-speed system that operates with a single battery voltage such as a power supply voltage of 2 V or less or about 0.9 to 1.6 V, it is no longer possible to reduce power even if the clock is stopped. Generally, in an LSI composed of logic gates mainly composed of random gates, it is said that the number of logic gates whose input voltage changes among a large number of logic gates in a chip is about 20% of the whole. The inputs of the other 80% of the logic gates do not change. Fortunately, the threshold voltage was high in the conventional CMOS circuit, so that the power of the 80% of the logic gates could be almost neglected and the whole chip could be reduced in power. However, this can no longer be expected at blackout voltages. Hereinafter, a microprocessor will be described as an example of an electronic device in which the entire chip has low power in a low power supply voltage operation.

  FIG. 44 shows a single-chip microprocessor incorporating the power reduction mechanism of the present invention. As described below, a feature is that a mechanism for controlling active / standby for each unit inside the chip is provided. Reference numeral 600 denotes a single-chip microprocessor. On this microprocessor 600, a central processing unit (hereinafter abbreviated as CPU) 601, a coprocessor A (hereinafter abbreviated as COPA) 602, a coprocessor B (hereinafter abbreviated as COPB) 603, a local memory (hereinafter abbreviated as LM) 604) and a bus control unit (hereinafter abbreviated as BUSC) 605. These units are connected by an internal bus 651 on the chip. The outside of the chip is connected to the external bus 652 via the BUSC 605. To the external bus 652, a main memory (hereinafter abbreviated as MS) 606, an input / output device (hereinafter abbreviated as IO) 607 and the like are connected. The CPG 606 is a clock generator, and each unit in the chip operates in synchronization with a clock signal 653 generated from the CPG 606.

  The COPA 602, COPB 603, and LM 604 each have two operating states. One of them is a sleep state. In this state, the operation of each unit is stopped, and the consumed power is extremely small. The other is in an active state. In this state, the unit is executing processes such as a data read / write operation and an arithmetic operation. For this reason, power consumption is not suppressed to an extremely small value. As the logic circuits constituting these units, for example, the circuits shown in FIGS. 18 to 26, FIGS. 28 to 32, and FIGS. 39 to 41 are used. Thereby, the power consumption in the sleep state can be reduced. Furthermore, even in the active state, the power can be reduced by finely controlling the activation state for each phase of the two-phase clock using the circuits in FIGS. MS 606 and IO 607 also have an active / sleep state. The signals 654 and 655 output from the microprocessor 600 are signals that indicate that the MS 606 and the IO 607 are in the active state, respectively.

  The COPA 602 and the COPB 603 are basically the same type of unit, and execute a specified operation only when a program executed by the CPU includes an instruction requesting a COPA or COPB operation. It becomes active only at this time, and may be sleep during other periods. In a normal program, the frequency of this operation request is not so high. Inside, there are a large number of register files and a dedicated arithmetic unit (sometimes a plurality of units) having a large number of transistors, and the feature is that the total number of transistors is large.

  The LM 604 has a high access frequency because programs and data required by the CPU are stored. However, in the case where a cache memory is built in the CPU, since the processing is performed by closing the CPU, the frequency of access is reduced and the period of the sleep state is prolonged.

  The CPU 601 executes instructions and processes data at all times, and always executes programs (activation rate 100%). The inside of the CPU includes basic parts of a normal processor such as general-purpose registers and arithmetic units. At times, it may include a cache memory. Instructions and data are stored in the LM 604 or the MS 606. The LM 604 is a small-capacity but on-chip memory that can be accessed at high speed, and stores instructions and data frequently used by the CPU 601. Instructions and data that do not need to be accessed so frequently are stored in the MS 606, which is a large-capacity but low-speed memory. The CPU 601 can directly access the LM 604 via the internal bus 651. On the other hand, access to the MS 606 is via the internal bus 651, BUSC 605, and external bus 652. The BUSC 605 includes an external bus buffer having a width of about 32 to 128 bits. It only needs to be active when the CPU accesses a memory or device outside the chip. When a program or data required by the CPU exists in the chip, the sleep state may be used.

  The COPA 602 is a coprocessor that executes multiplication, division, square root, and calculation of an absolute value, and has a dedicated arithmetic unit that performs these operations at high speed. The COPB 603 is a coprocessor that executes a function operation such as a trigonometric function and a distance calculation, and includes a dedicated arithmetic unit that processes these operations at high speed. The CPU 601 starts the operation of each coprocessor by writing a command instructing the requested operation to the command registers CMDA609 and CMDB610 in the COPA 602 and the COPB 603 via the internal bus 651. Until the start of the operation, each coprocessor is in a sleep state and consumes little power.

  FIG. 45 is an internal configuration diagram of the COPA 602. The inside is composed of two blocks ITFA700 and EXA701. The ITFA 700 has a command register CMDA609, a command decoder DEC706, operand registers RA702, RB703, RC704, and a control circuit CNT705. The EXA 701 incorporates a dedicated arithmetic unit for processing multiplication, division, square root, and calculation of absolute value at high speed, and a control circuit for controlling the arithmetic unit. The command sent from the CPU 601 via the internal bus 651 is held in the CMDA 609, the command is decoded by the DEC 706, and the EXA 701 executes the operation specified by the command. There are four types of commands: multiplication, division, square root, and absolute value. As operands for the operation, source operands sent from the CPU 601 are stored in RA 702 and RB 703, and the operation result is stored in the RC 704 after the operation is completed in the EXA 701, and is read out from the CPU 601. The EXA 701 is in a sleep state when not performing an operation. When the command is decoded by the DEC 706, a signal for causing the EXA 701 to execute the operation specified by the command is generated, and the EXA 701 starts the operation. During the execution of the calculation, the EXA 701 is in the active state. After the operation is completed, the EXA 701 stores the result in the RC 704 and clears the CMDA 609 to zero. The DEC 706 detects that the content of the CMDA 609 is zero, and when the SLEEP 707 signal is asserted, the EXA 701 enters a sleep state. The CNT 705 controls operations such as read / write and zero clear for each of the registers 609, 702, 703, 704. ITFA 700 is always in an active state in order to always receive a command from the CPU. The clock signal 653 generated from the CPG 606 is used in the ITFA 700. Further, an EXA clock signal 710 is output through the gate circuit 709 and is used as a clock of the EXA 701. When SLEEP 707 is asserted, the gate circuit 709 stops the EXA clock 710, and the clock is not supplied to the EXA 701. Thus, in the sleep state, the clock of the EXA 701 is also stopped. The SLEEP signal controls, for example, the switches of the circuits shown in FIGS. 18 to 26 or FIGS. 28 to 32, and reduces the subthreshold current in the sleep state.

  The EXA 701 includes a dedicated arithmetic unit, a register for holding an intermediate result of an operation, a register for holding an operation state, a latch for operation control, and the like. For these registers and latches, for example, the circuits shown in FIGS. 35 and 37 are used. In the case of the circuit of FIG. 35, once the sleep state is entered, the state inside the latch is destroyed. On the other hand, in the case of the circuit in FIG. 37, the state inside the latch is not destroyed even when the sleep state is entered. For this reason, after returning to the active state after entering the sleep state, the arithmetic operation that has been stopped halfway can be restarted.

  The COPB 603 is a coprocessor that executes a function operation such as a trigonometric function and a distance calculation, and has the same internal configuration and operation as the COPA 602.

  FIG. 46 shows the internal configuration of the LM 604. The MEM 901 is a memory unit for storing information such as instructions / data. The MCNT 902 receives an access request from the CPU 601 and controls reading data stored in the MEM 901 and writing data to the MEM 901. When there is an access request from the CPU 601, the MCNT 902 asserts a signal ACT 903 for setting the MEM 901 to an active state, and sets the MEM 901 to an operating state. When there is no access request, ACT 903 is negated and MEM 901 is in a sleep state. The ACT signal controls the switches of the circuits shown in FIGS. 18 to 26 or FIGS. 28 to 32, for example, and reduces the subthreshold current in the sleep state. In this state, information is held in the memory. The MCNT 902 is always in an active state in order to always be able to receive an access request from the CPU.

  When the CPU 601 accesses an instruction or data to the MS 606, the access is made via the internal bus 651, the BUSC 605, and the external bus 652. The BUSC 605 becomes active only at this time. FIG. 47 shows the internal configuration of the BUSC 605. The BCNT 800 is a circuit that controls access to the external bus 652 in response to a request from the CPU 601. OUTB 801 is a driver circuit that drives the external bus 652 when data flows from the internal bus 651 to the external bus 652, and becomes active only at this time. The INB 802 is a driver circuit that drives the internal bus 651 when data flows from the external bus 652 to the internal bus 651, and becomes active only at this time. Upon receiving a write request from the CPU 601 to the MS 606 or the IO 607 outside the chip, the BCNT 800 asserts ACTW 803 and activates OUTB 801. Conversely, upon receiving a read request from the MS 606 or IO 607 outside the chip from the CPU 601, the BCNT 800 asserts ACTR 804 to activate INB 802. Except for these times, OUTB 801 and INB 802 are in the sleep state. The BCNT 800 is always in an active state so that an access request to the outside of the chip can always be accepted. BCNT 800 also outputs an active support signal 654 for MS 606 and an active indication signal 655 for IO 607. When the CPU 601 requests the BCNT 800 to access the MS 606, the BCNT 800 detects the request and asserts the signal 654 to activate the MS 606. Signal 655 is used for a similar purpose.

For example, the output buffer circuit shown in FIG. 25 is used as the OUTB 801 and the switches S _S and S _C are controlled in accordance with the ACTW signal. Since OUTB drives a large load (external bus 652), it requires MOS transistors having a large channel width by the number of bus widths (for example, 64 bits), and the total of the channel widths is very large. Therefore, reducing the subthreshold current of OUTB greatly contributes to reducing the current of the entire system.

  For example, the input buffer circuit shown in FIG. 26 is used as the INB 802, and the ACTR signal is supplied to the SB terminal. Thus, the voltage level of internal bus 651 in the sleep state can be determined. Therefore, for example, the circuits shown in FIGS. 18 to 25 can be used for the units COPA, COPB, and LM connected to this bus, and the sub-threshold current of these units can be easily reduced.

  For example, a DRAM is used for the MS 606. The DRAM may be an ordinary DRAM, but is described in IEE Spectrum, pp. 43-49, October 1992 (IEEE Spectrum, pp. 43-49, Oct. 1992). May be used. In a synchronous DRAM, the supply of a clock to the inside of a chip can be controlled by a clock enable / disable signal, so that the current consumption can be effectively reduced by utilizing this signal. That is, in the sleep state, the supply of the clock to the inside of the chip is stopped. Further, the sub-threshold current of the internal circuit can be reduced by using the circuit of FIG. 26 as an input buffer of a synchronous DRAM and applying a clock enable / disable signal to the SB terminal.

  FIG. 48 shows an operation example of the entire microprocessor 600. The horizontal axis represents time, and the diagonal lines indicate states in which each unit and each block are active. In this example, the CPU 601 issues a division command to the COPA 602 at the time T1, and the COPA 602 executes division from T1 to T2 in accordance with the command, reports the completion of the operation to the CPU 601 at the time T2, and enters the sleep state again. Thereafter, the CPU 601 issues a distance calculation command to the COPB 603 at the time T3, and the COPB 603 executes the distance calculation from T3 to T4 according to the command, reports the end of the calculation to the CPU 601 at the time T4, and enters the sleep state again. The LM 604 becomes active only when there is a data access request from the CPU 601. The BUSC 605 is also activated only when the CPU 601 accesses the outside. As described above, the power consumption of the microprocessor 600 can be significantly reduced by finely controlling the active / sleep state of each unit and each block inside the microprocessor 600.

  Although the present embodiment is a case where the present invention is applied inside one chip, it is obvious that this is extended to an embodiment of a computer system including a plurality of chips. For example, it is easy to apply the present invention in a case where each of units 601 to 605 in FIG.

FIG. 2 is a diagram illustrating an inverter according to the first embodiment of the present invention. FIG. 4 is a diagram illustrating the principle of sub-threshold current reduction according to the present invention. FIG. 4 is a diagram showing a sub-threshold current reducing effect according to the present invention. FIG. 9 is a circuit diagram of an inverter according to a second embodiment of the present invention. FIG. 4 is a diagram illustrating timings of signals according to the present invention. FIG. 2 is a diagram showing a device structure of the present invention. FIG. 9 is a circuit diagram of an inverter according to a third embodiment of the present invention. FIG. 9 is a circuit diagram of an inverter according to a fourth embodiment of the present invention. FIG. 2 is a diagram showing a device structure of the present invention. It is a figure showing an inverter row of Example 5 of the present invention. FIG. 14 is a diagram illustrating an inverter array according to a sixth embodiment of the present invention. It is a figure showing an inverter row of Example 7 of the present invention. FIG. 9 is a diagram illustrating an example of grouping of combinational logic circuits to which the present invention is applied. FIG. 14 is a diagram illustrating a combinational logic circuit according to an eighth embodiment of the present invention. FIG. 19 is a diagram illustrating a combinational logic circuit according to a ninth embodiment of the present invention. It is a figure showing a latch of Example 10 of the present invention. It is a circuit diagram of the latch of Example 11 of this invention. It is a circuit diagram of the inverter row of Example 12 of the present invention. It is a circuit diagram of the inverter row of Example 13 of the present invention. FIG. 21 is a circuit diagram of a NAND gate according to a fourteenth embodiment of the present invention. FIG. 15 is a circuit diagram of a NOR gate according to Embodiment 15 of the present invention. It is a circuit diagram of the clock inverter of Example 16 of this invention. It is a circuit diagram of the combination logic circuit of the seventeenth embodiment of the present invention. It is a circuit diagram of the latch of Example 18 of this invention. FIG. 25 is a circuit diagram of an output buffer according to a nineteenth embodiment of the present invention. FIG. 21 is a circuit diagram of an input buffer according to Embodiment 20 of the present invention. FIG. 21 is a circuit diagram of an NMOS dynamic circuit according to Embodiment 21 of the present invention. It is a figure showing a conceptual example. It is a circuit diagram of an example applied to a CMOS inverter. FIG. 9 is an operation timing chart of the embodiment applied to the CMOS inverter. It is a figure showing an example applied to an inverter chain. FIG. 11 is a diagram illustrating another embodiment applied to an inverter chain. FIG. 14 is a diagram showing another embodiment applied to a CMOS inverter. FIG. 14 is a circuit diagram of another configuration example of the level hold circuit. FIG. 3 is a circuit diagram of a latch circuit that can fix an output. FIG. 4 is a timing chart of a control clock. FIG. 3 is a circuit diagram of a latch circuit that can fix an output. FIG. 4 is a timing chart of a control clock. FIG. 3 is a diagram illustrating a two-phase clock logic circuit. FIG. 3 is a circuit diagram of an inverter that operates with a two-phase clock. FIG. 4 is a timing chart of a control clock. FIG. 3 is a diagram showing a gate array according to the present invention. FIG. 3 is a diagram showing a gate array according to the present invention. FIG. 2 is a block diagram of a single-chip microprocessor according to the present invention. FIG. 2 is an internal configuration diagram of a coprocessor. FIG. 3 is an internal configuration diagram of a local memory. FIG. 3 is an internal configuration diagram of a bus control unit. FIG. 3 is an operation timing chart of the microprocessor. It is a circuit diagram of a conventional CMOS inverter. FIG. 4 is a diagram illustrating sub-threshold characteristics of a MOS transistor.

Explanation of reference numerals

L, L _{1 to} L _k ... Logic gates G _{1 to} G _k .
S _C , S _{C1 to} S _Ck ,
S _S , S _{S1 to} S _Sk ... Switches R _C , R _{C1 to} R _Ck , R _S , R _{S1 to} R _Sk.

Claims (3)

  A processor including an arithmetic circuit / control circuit including a register, wherein the register maintains its state even in a sleep state. In claim 1,
A logic gate connected to the register;
A control circuit connected to the logic gate,
The logic gate has a first conductivity type first MOS transistor and a second conductivity type second MOS transistor connected in series to a source / drain path of the first MOS transistor. An output signal is obtained from an output node that is a common connection point between the path and the source / drain path of the second MOS transistor;
The control circuit is connected to one of the first and second MOS transistors, is supplied with a control signal,
Setting the control signal supplied to the control circuit to a first state, thereby allowing a current of a first current value to flow to one source of the first or second MOS transistor;
By setting the control signal supplied to the control circuit to a second state different from the first state, a sub-threshold current flowing to the one source of the first or second MOS transistor is set to be smaller than the first current value. Processor to limit to small values. In claim 2,
The register has a first inverter circuit, a second inverter circuit, and a NAND circuit,
An input of the first inverter circuit is connected to an output of the logic gate and an output of the second inverter circuit,
An input of the second inverter circuit is connected to an output of the first inverter circuit,
A first input of the NAND circuit is connected to an output of the second inverter circuit;
A second input of the NAND circuit receives the control signal,
A processor wherein an output of the NAND circuit is an output of the register.

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