JP2001068991A - Level shift circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase a series of operation speed by suppressing the increase in a circuit area. SOLUTION: The level shift circuit is provided with an input terminal IN of a 1st high level VDD1 system, an output terminal out of a 2nd high level VDD2 system higher than the 1st high level, a 1st connection node N3 interconnecting one terminal of a 1st MOSTr and a gate of a 2nd MOSTr, and a 2nd connection node N2 interconnecting the one terminal of the 2nd MOSTr and a gate of the 1st MOSTr. Then 1st and 2nd PMOSTrs 32, 31 are connected in series between a power line of the 1st high level VDD1 and the 1st connection port N3, the 1st PMOSTr 32 is controlled by an input signal and the 2nd PMOSTr 31 is controlled by an output signal and a 1st inverter INV 30 of the 2nd high level VDD2 system connected to the 1st connection node N3 has a characteristic of inverting the input level of the 1st high level VDD1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shift circuit, and more particularly, to two different high potentials (VDD1 and V1).
The present invention relates to a level shift circuit used for a VDD2) system having a higher potential than DD1.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, an optimum power supply voltage is selected according to an application, so that each circuit has a different signal level. Therefore, a signal is transmitted and received by providing a level shift circuit between circuits using different power supply voltages.

FIG. 5 shows a conventional level shift circuit. In the figure, an input terminal IN for inputting an input signal which changes between a VSS level (ground level) and a VDD1 level,
Between the VSS terminal (ground level) and the output terminal OUT that outputs an output signal that transitions between the VDD2 level, VDD
A P-channel insulated gate field-effect transistor (hereinafter, referred to as a PMOS transistor) whose source is connected to a power supply line of VDD2, and a VDD1 inverter INV1 and an inverter INV2 that operates on D1, a VDD2 inverter INV3 and an inverter INV4 that operates on VDD2,
T) 21 and 22 and N-channel insulated gate field effect transistors (hereinafter referred to as NMOST) 11 and 12 each having a source connected to a ground potential (VSS level) line. Make up the circuit.

Here, the inverter INV1 and the inverter INV2 are circuits in which the input of the VDD1 level is inverted, and the inverter INV3 and the inverter INV4 are connected to the VDDV.
This circuit inverts the D2 level input.

The drain of the PMOST 21 and the NM
The connection node N2 to which the drain of OST11 is connected is P
A connection node N3 connected to the gate of the MOST22 and connected to the drain of the PMOST22 and the drain of the NMOST12 is connected to the gate of the PMOST21, and this connection node N3 is connected to the input of the inverter INV3.

An inverter INV1 and an inverter I
The connection node N1 between the inverter INV2 and the output terminal of the inverter INV2 is connected to the gate of the NMOST12.
11 gates.

When the input signal IN at the input terminal IN of the level shift circuit is at the VSS level (ground level), N
MOST11 is off, NMOST12 is on, connection node N3 is at VSS level, PMOST21 is on,
The connection node N2 is at the VDD2 level, the PMOST 22 is off, and the output signal OUT at the output terminal OUT of the level shift circuit is at the VSS level (ground level).

On the other hand, when the input signal IN at the input terminal IN of the level shift circuit is at the VDD1 level, the NMOS
T11 is turned on, NMOST12 is turned off, the connection node N2 is at the VSS level, PMOST22 is turned on, the connection node N3 is at the VDD2 level, PMOST21 is turned off, and the output signal OUT at the output terminal OUT of the level shift circuit is at the VDD2 level.

In a conventional level shift circuit as shown in FIG. 5, a PMOST is used to reduce current consumption.
The drive current of No. 22 was reduced to suppress the through current.

However, as a result of reducing the driving capability, the following problems have occurred.

FIG. 6 shows operation waveforms of FIG. Input signal I
When N rises from the state of 0 level (VSS level) (state of A) to the VDD1 level (state of B), N
The MOST11 transitions to the ON state, and the NMOST12 transitions to the OFF state. Thereafter, the PMOST 22 is turned on, but since the driving capability is small, the connection node N3 gradually turns to VD.
The voltage increases in the direction of D2.

When the output of the inverter INV3 exceeds the threshold voltage, the output is inverted and the output signal OV3 is inverted.
The UT is inverted from 0 level (VSS level) to VDD2 (state C from the latter half of B).

There has been a problem that the speed of these series of operations is reduced. Note that when the input signal IN falls, the NMOST11 changes to the off state and the NMOST12 changes to the on state (state D), and the output signal falls immediately, so there is no problem.

As described above, in the prior art shown in FIG. 5, since the driving capability of the PMOST 22 is reduced in order to suppress the through current, the rise of the voltage of the connection node N3 in the direction of VDD2 at the time of the rise of the signal is delayed. Has a problem that the speed of the operation is slow.

In order to solve this problem, a level shift circuit as shown in FIG. 7 is disclosed in Japanese Patent Laid-Open No. 5-343980.

In FIG. 7, NMOST 107, NMO
ST108, PMOST 105, PMOST 106, connection node N111, and connection node 110 form FIG.
NMOST11, NMOST12, PMOST21,
PMOST22, connection node N2 and connection node N3
A circuit similar to the circuit according to the above is formed.

In the circuit of FIG. 7, the PMOST 112 and the PMOST 113 for accelerating the rise time
The configuration is such that a signal change detection pulse generation circuit 102 which is added in parallel to the MOST 105 and the PMOST 106 and which generates the signal by catching the falling of the signal is added.

The signal change detection pulse generating circuit 102 includes a plurality of inverter circuits INV and a plurality of NOR circuits. For example, when the input signal IN rises, the connection node N111 falls.
From the connection node N125 for a moment.
The above-mentioned acceleration PMOS which generates a falling pulse
T113 is turned on, and the node N110 is set to a high VD
Increase to D2 level.

Thus, the output signal can be changed at a high speed in response to a change in the input signal, and the current consumption is suppressed.

However, this conventional technique has a new problem. That is, the acceleration transistor PMOST1
12 and PMOST 113 as well as their PM
The signal change detection pulse generation circuit 102 for controlling the OST must be configured using many inverter circuits INV and NOR circuits.

Therefore, the prior art shown in FIG. 7 has a problem that the circuit area increases. For example, when a level shifter circuit is applied to a liquid crystal driver or the like, several tens of the circuits are required, and the above-described conventional technology also affects the chip area.

[0022]

As described above, the conventional technique shown in FIG. 5 has a problem that the speed of a series of operations is reduced.

In addition, the conventional technique shown in FIG. 7 has a problem that the required circuit area increases greatly.

Accordingly, an object of the present invention is to provide an effective level shifter circuit that suppresses an increase in circuit area and increases the speed of a series of operations.

[0025]

SUMMARY OF THE INVENTION The present invention is characterized in that an input terminal (IN) for inputting an input signal (IN) that transitions between a first high potential (VDD1) and a low potential (VSS); 1
Output terminal (OUT) for outputting an output signal (OUT) that transitions between a second high potential (VDD2) higher than the high potential of the first MOST and a low potential (VSS), one end of the first MOST and the second M
A level converter having a first connection node (N3) for connecting a gate of the OST and a second connection node (N2) for connecting one end of the second MOST and a gate of the first MOST; In a level shift circuit including a first inverter (INV30) provided between a first connection node (N3) and the output terminal (OUT), the first high-potential power supply line (VDD1) And a first PMO between the first connection node (N3) and the first connection node (N3).
ST (32, 31) are connected in series, and the first PMO
ST (32) is controlled by the input signal, the second PMOST (31) is controlled by the output signal, and the first inverter (INV30) is connected to the second high potential (VDD2) power supply line. One end is connected to the first
In the level shift circuit having the characteristic that the input level of the high potential (VDD1) is inverted. Here, a second inverter (INV4) having one end connected to the second high potential (VDD2) may be provided between the first inverter (INV30) and the output terminal (OUT). it can. In addition, one end is connected between the second connection node (N2) and the input terminal (IN) at one end to the power supply line of the first high potential (VDD1), and the first high potential (VDD1) is connected to the first high potential (VDD1). Third and fourth inverters (INV2, INV1) whose input levels of VDD1) are inverted are connected in series, and the third and fourth inverters (INV2, INV2) are connected in series.
INV1), the first PMOST (3
2) can be controlled.

Another feature of the present invention is that the first high potential (VD
D1) and an input signal (I) transitioning between a low potential (VSS).
N), and an output signal (OUT) that transitions between a second high potential (VDD2) higher than the first high potential (VDD1) and a low potential (VSS). An output end (OUT), one end of the first MOST and the second end
Of the first connection node (N
3) and one end of the second MOST and the first MOT
A level converter having a second connection node (N2) for connecting the gate of ST, and a first and a second provided between the first connection node (N3) and the output terminal (OUT). In the level shift circuit including the inverters (INV30, INV4), a PMOST (32) and an NMOST (41) are connected between the first high-potential power supply line (VDD1) and the first connection node (N3). Connected in series, the PMOST (32) is controlled by the input signal, the NMOST is controlled by a signal between the first and second inverters (INV30, INV4), and the first inverter (INV30) One end is connected to the second high potential (VDD2) power supply line and the first
In the level shift circuit having the characteristic that the input level of the high potential (VDD1) is inverted. Here, one end is connected between the second connection node (N2) and the input terminal (IN) at one end to the power supply line of the first high potential (VDD1), and the first high potential is connected to the first high potential (VDD1). Third and fourth inverters (INV) in which the input level of (VDD1) is inverted.
, INV1) are connected in series, and the PMOST can be controlled by a signal between the third and fourth inverters (INV2, INV1).

In each of the above-described level shift circuits, the level conversion unit operates at the second high potential (VDD).
2) a pair of a series connection of a PMOST and an NMOST provided between the power supply line of 2) and the power supply line of the low potential (VSS). It can be a first and a second connection node.

As described above, in the present invention, the first PMOST controlled by the input signal IN and the second PMOST controlled by the output signal OUT are connected in series, or the PMOST controlled by the input signal IN is connected.
And NMOST controlled by a signal related to an output signal
Are connected in series, one end of the second PMOST or NMOST is connected to the connection node N3, and the threshold level of the inverter INV30 having the connection node N3 as an input is reduced, so that the charge-up of the connection node N3 is performed at high speed. This is a level shift circuit including a self-reset that operates, detects a change in the output signal OUT, and automatically controls the second PMOST or NMOST.

That is, the level shift circuit according to the present invention includes the pull-up transistor, so that when the input level rises to the first high potential level, the pull-up transistor is driven and the first high-level transistor is rapidly driven. The circuit is characterized in that the output level is quickly raised from the VSS level to a second high potential level higher than the first high potential level by charging up to the potential level.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a level shift circuit according to a first embodiment of the present invention.

An input terminal IN for inputting an input signal which changes between a VSS level (ground level) and a first high potential level VDD1 level, for example, + 2V (volt);
Between the VSS level (ground level) and the output terminal OUT that outputs an output signal that changes between the second high potential level VDD2 level, for example, +5 V (volts), VDD
1 and a series-connected body of the VDD1 system inverter INV1 and the inverter INV2 operating at VDD1 and V2 operating at VDD2.
DD2-type inverter INV30 and inverter INV
4 connected in series, PMOSTs 21 and 22 each having a source connected to a power supply line having a potential of VDD2, and NMOSTs 11 and 12 each having a source connected to a line having a ground potential (VSS level).

Further, a pull-up transistor P
The series connection of MOST32 and PMOST31 is VDD1
Potential power line and VDD2 inverter INV30
And is provided between the inputs.

Then, the drain of the PMOST 21 and the NM
A connection node (second connection node) N2 to which the drain of OST11 is connected is connected to the gate of PMOST22, and a connection node (first connection node) N3 to which the drain of PMOST22 and the drain of NMOST12 are connected.
Is connected to the gate of the PMOST21, and the connection node N3 is connected to the input of the inverter INV30.

That is, the series connection of the PMOST 32 and the PMOST 31 which are the pull-up transistors is VD
Both ends are connected to a power supply line of D1 potential and a connection node (first connection node) N3.

The inverter INV1 and the inverter I
The connection node N1 between the inverter INV2 and the output terminal of the inverter INV2 is connected to the gate of the NMOST12.
11 gates. Further, the connection node N
1 is connected to the gate of the PMOST 32 and the inverter I
The output of NV4, that is, the output terminal OUT of the circuit is a PMOS
It is connected to the gate of T31.

The source of the PMOST 32 is VDD1
Is connected to a power supply line of a potential, for example, a + 2V power supply.
The drain of the OST 32 is connected to one of the source and the drain of the PMOST 31, and the other of the source and the drain of the PMOST 31 is connected to the connection node N3.

Next, the inverter of FIG. 1 will be described with reference to FIG.

The inverter INV1 for waveform shaping shown in FIG. 2A comprises a series connection of a PMOST 51 and an NMOST 61, and is connected between the first high potential power supply VDD1 and the low potential power supply VSS. Similarly, the inverter INV2 shown in FIG. 2B includes a PMOST 52 and an NMOST6.
And two series-connected members, which are connected between the first high-potential power supply VDD1 and the low-potential power supply VSS. PMOST51
And PMOST52 have the same characteristics, NMOST61 and NMO
ST62 has the same characteristic, and the threshold voltage (Vth) <VDD1 is set so that the output of both the inverter INV1 and the inverter INV2 is inverted when the input is VDD1. VDD1 is + 2V and VSS is grounded (0V)
In this case, for example, Vth is +1 V.

The final-stage inverter IN shown in FIG.
V4 is composed of a series connection of a PMOST 54 and an NMOST 64, and includes a second high-potential power supply VDD2 and a low-potential power supply VS
It is connected between S. Vth <VDD2 so that the output is inverted when the input is VDD2. VDD
2 is + 5V and VSS is ground (0V), for example, Vt
h is + 2.5V.

However, the inverter INV30 shown in FIG. 2C is composed of a series connection of the PMOST 53 and the NMOST 63, and is connected between the second high-potential power supply VDD2 and the low-potential power supply VSS. Vth <VDD1 so that the output is inverted. When VDD2 is + 5V and VSS is ground (0V),
For example, Vth is + 1V. That is, it is the second high-potential VDD2-type inverter, but the first high-potential VDD
When 1 is input, it is inverted.

Such an inverter INV30 is provided by NM
It can be obtained by setting the size of each transistor so that the driving capability of the OST 63 is higher than the driving capability of the PMOST 53.

Next, the operation of the level shift circuit according to the first embodiment will be described with reference to FIG.

The input signal IN is at the VSS level (0 level)
In the case of, since the output of the inverter INV2 is at the VSS level, the NMOST11 is off. Also, since the output of the inverter INV1 is in the state of VDD1, NMO
ST12 is on, and connection node N3 is at the VSS level.

Since the connection node N3 is at the VSS level, the PMOST 21 is turned on, and the connection node N2 is in the state of VDD2. Further, since the connection node N3 is at the VSS level, the output signal OUT is at the VSS level. Since the output signal OUT is connected to the gate of the PMOST 31, the PMOST 31 is on. The above is the state of A in FIG.

When the signal IN rises to the VDD1 level from this state, the output of the inverter INV1 becomes VDD
1 level rapidly falls to VSS level, NMO
ST12 is turned off. The output of the inverter INV2 rapidly rises to the VDD2 level, and the NMOST11
Is turned on.

Further, the output of the inverter INV1 is VS
By going to the S level, the PMOST 32 rapidly turns on. At this time, since the output signal OUT is still at the VSS level, the PMOST 31 is in the ON state, and the connection node (first connection node) N3 rapidly passes through the PMOST 31 and rapidly transitions to the VDD1 level.
Although the MOST 22 changes to the ON state, these PMOs
In ST22, since the driving capability is generally reduced to suppress the through current, the node N3 changes from VDD1 level to VDD.
Charge up slowly to 2 levels.

However, the connection node N3 is connected to the PMOST32
Is immediately turned on to reach the VDD1 level, the output of the inverter INV30 whose threshold voltage is set lower than VDD1 is inverted from the VDD2 level to the VSS level, and the output signal OUT rises from the VSS level to VDD2.

Thereafter, the PMOST 31 is turned off, and the supply of the VDD1 level voltage to the connection node N3 is cut off. At the same time, the connection node N3 is further charged up from the VDD1 level to the VDD2 level because the PMOST22 is in the ON state, and the PMOST2 is turned on.
1 is turned off. The above is the state of B in FIG.

When the input signal IN is at the VDD1 level, N
The MOST11, the PMOST22, and the PMOST32 are turned on, and the NMOST12, the PMOST21, and the PMOST3 are turned on.
1 is off. Therefore, the connection node N1 and the connection node (second connection node) N2 are at the VSS level (0 level), and the connection node (first connection node) N3 and the output signal OUT are at the VDD2 level. The above is the state of C in FIG.

When the input signal IN falls from the VDD1 level to the VSS level from this state, the inverter I
The output of NV1 rapidly rises to VDD1 level,
MOST12 is turned on. The output of the inverter INV2 rapidly falls to the VSS level and the NMOST1
1 is turned off. Further, since the output of the inverter INV1 goes to the VDD1 level, the PMOST 32 is turned off.

After the connection node N3 transitions to the VSS level, the output signal OUT changes from the VDD2 level to the VSS level.
Change to a level. VSS is applied to the gate of PMOST31.
Although the voltage of the level is applied, the PMOST 32 is in the off state, so that the connection node N3 is not affected. Therefore, since the connection node N3 is at the VSS level, the PMOST 21 is turned on, and the connection node N2 slowly moves toward the VDD2 direction. At the same time, the PMOST 22 transitions to the off state. The above is the state of D in FIG.

FIG. 4 is a circuit diagram showing a level shift circuit according to a second embodiment of the present invention. In FIG. 4, portions having the same or similar functions as those in FIG. 1 are denoted by the same reference numerals, and duplicate description will be omitted.

In the circuit shown in FIG. 1, when there is a concern that the timing of the on / off state of the PMOST 31 for controlling the gate from the output terminal OUT is shifted due to the load capacitance in the output signal OUT of the level shift circuit, FIG. Circuit can be used.

That is, in FIG. 4, the PMOST 31 of FIG.
Is used instead of the NMOST41.
Has a gate connected to the output of the inverter INV30, a drain connected to the drain of the PMOST 32, and a source connected to a connection node (first connection node) N3. Therefore, the timing of the ON / OFF state of the NMOST 41 is not affected by the load of the output signal OUT. Other operations are the same as those of the first embodiment shown in FIGS.

[0056]

The first effect of the present invention is that the input signal is VS.
When the voltage rises from S to the first high potential voltage (VDD1), the output signal is high speed and the second signal is higher than the first high potential voltage.
And outputs the high potential voltage. This is because a pull-up transistor is provided.

The second effect is that the pattern area of the control circuit for controlling the pool-up transistor is very small. The reason is that it can be realized with only two transistors.

The third effect is that the input signal changes from VSS to the first
When the voltage rises to a higher voltage, the through current of the buffer (INV30) in the level shifter circuit can be reduced. The reason for this is that the input signal rises at high speed by inserting the pull-up transistor.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a level shift circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing each inverter in the level shift circuit according to the first embodiment of the present invention.

FIG. 3 is a time chart illustrating an operation of the level shift circuit according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a level shift circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a conventional level shift circuit.

FIG. 6 is a time chart illustrating an operation of the level shift circuit of FIG. 5;

FIG. 7 is a circuit diagram showing another conventional level shift circuit.

[Explanation of symbols]

11, 12, 41, 61, 62, 63, 64 NMO
ST 21, 22, 31, 32, 51, 52, 53, 54
PMOST 102 Signal change detection pulse generation circuit 105, 106, 112, 113 PMOST 107, 108 NMOST INV1, INV2 First high-potential-system inverter circuit INV3, INV4 Second high-potential-system inverter circuit INV30 Low Vth 2 High-potential inverter circuit INV Inverter circuit NOR NOR circuit N1, N2, N3 Connection nodes N110, N111, N124, N125 Connection nodes VDD1 First high potential (power supply) VDD2 Second high potential (power supply) VSS Low Potential (ground, 0 V level) IN input terminal, input signal OUT output terminal, output signal

Claims (6)

[Claims] 1. An input terminal for inputting an input signal that transitions between a first high potential and a low potential, and an output signal that transitions between a second high potential and a low potential higher than the first high potential. An output terminal for outputting, a first connection node connecting one end of the first insulated gate field effect transistor and the gate of the second insulated gate field effect transistor, and one end of the second insulated gate field effect transistor; A level conversion section having a second connection node for connecting the gate of one insulated gate field effect transistor; and a first inverter provided between the first connection node and the output terminal. In the shift circuit, first and second P-channel insulated gate field-effect transistors are connected in series between the first high-potential power supply line and the first connection node; A channel insulated gate field effect transistor is controlled by the input signal, a second P-channel insulated gate field effect transistor is controlled by the output signal, and the first inverter is connected at one end to the second high potential power supply line. , And has a characteristic that the input level of the first high potential is inverted. 2. A second inverter having one end connected to the second high-potential power supply line between the first inverter and the output terminal. Level shift circuit. 3. A circuit in which one end is connected between the second connection node and the input terminal to the first high-potential power supply line, and the input level of the first high potential is inverted. A third and a fourth inverter are connected in series,
The signal between the third and fourth inverters causes the first
2. The level shift circuit according to claim 1, wherein said P-channel insulated gate field effect transistor is controlled. 4. An input terminal for inputting an input signal that transitions between a first high potential and a low potential, and an output signal that transitions between a second high potential and a low potential higher than the first high potential. An output terminal for outputting, a first connection node connecting one end of the first insulated gate field effect transistor and the gate of the second insulated gate field effect transistor, and one end of the second insulated gate field effect transistor; A level conversion unit having a second connection node connecting the gates of the first insulated gate field effect transistor; a first and a second inverter provided between the first connection node and the output terminal; A level shift circuit comprising: a P-channel insulated gate field-effect transistor and an N-channel insulated gate field-effect transistor between the first high-potential power supply line and the first connection node; Transistors in series, the P-channel insulated gate field effect transistor is controlled by the input signal, the N-channel insulated gate field effect transistor is controlled by a signal between the first and second inverters, Has one end connected to the second high-potential power supply line and
Wherein the input level of the high potential is inverted. 5. A circuit in which one end is connected between the second connection node and the input terminal to the first high potential power supply line, and the input level of the first high potential is inverted. A third and a fourth inverter are connected in series,
5. The level shift circuit according to claim 4, wherein said P-channel insulated gate field-effect transistor is controlled by a signal between said third and fourth inverters. 6. The level conversion section includes a series connection of a P-channel insulated gate field-effect transistor and an N-channel insulated gate field-effect transistor provided between the second high-potential power supply line and the low-potential power supply line. 6. The semiconductor device according to claim 1, further comprising a pair of bodies, wherein a connection point between both transistors in each series connection body is the first and second connection nodes. 7. 3. The level shift circuit according to 1.