KR100604658B1 - Voltage level sifter - Google Patents

Abstract

The present invention is to provide a voltage level shifter that can improve the transition characteristics of the output signal by driving the potential of the node constituting the positive feedback loop faster and more stable. A first inverter for inverting the input signal as a power source; A pull-down driving unit configured to pull down the first and second nodes to a second power level in response to a signal inverting the output signal of the first inverter and the output signal of the first inverter; A pull-up main driver configured to pull the voltages applied to the first and second nodes to a cross input to drive the first and second nodes to a third power level; A pull-up auxiliary driver for driving the first and second nodes to a first power source before the first and second nodes are pulled up by the pull-up main driver in response to an output signal of the first inverter; And a second inverter for inverting the voltage applied to the second node and outputting the output signal as an output signal using a third power source as a source power source.

Level Shifter, High Potential Voltage, Transient Characteristics, Fighting, Size

Description

Voltage level shifter {VOLTAGE LEVEL SIFTER}             

1 is a circuit diagram of a voltage level shifter according to the prior art.

2 is a circuit diagram of a voltage level shifter according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

200: pull-up auxiliary driving unit

300: pull-down driving unit

100: pull-up main driving unit

TECHNICAL FIELD The present invention relates to semiconductor design techniques, and more particularly, to a voltage level shifter.

As semiconductor memory devices are gradually becoming low power, the level of external power supply is being lowered. Therefore, in order to supply a low level signal applied from the outside to the device at a logic level having a high potential, such as a boosting power source actually used inside, a level shifter circuit for transmitting such a low level signal as a high potential signal. Is used.

1 is a circuit diagram of a voltage level shifter according to the prior art.

Referring to FIG. 1, a voltage level shifter according to the related art includes an inverter I1 for inverting an input signal in as VDD as a source power source, and a high potential voltage level corresponding to an output signal of the inverter I1. A level shifting unit 10 for outputting a signal of VPP) and an inverter I2 for inverting the output signal of the level shifting unit 10 using VPP as a source power source.

The level shifting unit 10 has an output signal of the interleaver I1 as a gate input, an NMOS transistor NM2 having a drain-source path between the node a and the power supply voltage VSS, and an inverted input signal. NMOS transistor NM1 having an inverter I3 and an output signal of inverter I3 as a gate input and having a drain-source path between node / a and a power supply voltage VSS, and a voltage applied to node / a as a gate input. A PMOS transistor (PM2) having a source-drain path between the power supply voltage VPP and node a, and a PMOS transistor having a source-drain path between the power supply voltage VPP and node / a as a gate input. PM1).

Next, the operation of the voltage level shifter will be briefly described.

First, when the input signal in transitions from the logic level 'low' to 'high', the NMOS transistor NM2 is turned off by the inverted input signal inb that has passed through the inverter I1. off), the node a is in an unstable state maintaining a voltage level close to the power supply voltage VSS. The PMOS transistor PM1 having the VSS level of the node a as the gate input and the NMOS transistor NM1 having the output signal ind of the inverter I2 as the gate input are turned on at the same time, and are fighting by their fighting. The voltage level at node / a is determined. At this time, the node / a is lowered by relatively increasing the driving force of the NMOS transistor. Subsequently, the node a is raised to the power supply voltage VPP level by the PMOS transistor PM2 having the node / a as the gate input, thereby turning off the PMOS transistor PM1 having the node a as the gate input.

Thereby, the node / a becomes the VSS level, and this value is output as the output signal out of the VPP level via the inverter I2.

As a result, after the PMOS transistor PM1 and the NMOS transistor NM1 are turned on at the same time, the PMOS transistor PM1 is subjected to level shifting with positive feedback from the moment the PMOS transistor PM2 is turned on. When turned off, the node / a becomes the power supply voltage VSS level completely by the pull-down operation of the NMOS transistor NM1, and the output signal out is transitioned from the power supply voltage VSS to VPP.

In addition, even when the input signal transitions from the logic level 'high' to 'low', a situation in which the PMOS transistor PM2 and the NMOS transistor NM2 are simultaneously turned on until positive feedback is generated.

As described above, when the input signal in transitions from the logic level 'low' to 'high' and from 'high' to 'low', the PMOS transistor PM1 or PM2 and the NMOS transistor NM1 or NM2 All are turned on, and since the fighting continues until the potentials of the connected nodes are fed back to the gate input and rise above the threshold voltage of the PMOS transistors PM2 or PM1, the short-circuit currents of the supply voltages VPP and VSS The transition characteristics of the output signal deteriorate. During the fighting, the potential of the output node is determined by the ratio of the driving capability of the PMOS transistors PM1 and 2 and the NMOS transistors NM1 and 2 simultaneously turned on.

The present invention has been proposed to solve the above problems of the prior art, and by driving the potential of the node constituting the positive feedback loop to a faster and more stable level, a voltage level shifter capable of improving the transition characteristics of the output signal is provided. The purpose is to provide.

According to an aspect of the present invention, a voltage level shifter includes: a first inverter configured to invert an input signal using a first power source as a source power source; A pull-down driving unit configured to pull down the first and second nodes to a second power level in response to a signal inverting the output signal of the first inverter and the output signal of the first inverter; A pull-up main driver configured to pull the voltages applied to the first and second nodes to a cross input to drive the first and second nodes to a third power level; A pull-up auxiliary driver for driving the first and second nodes to a first power source before the first and second nodes are pulled up by the pull-up main driver in response to an output signal of the first inverter; And a second inverter for inverting the voltage applied to the second node and outputting the output signal as an output signal using the third power source as the source power source.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2 is a circuit diagram of a voltage level shifter according to an embodiment of the present invention.

Referring to FIG. 2, the voltage level shifter according to an embodiment of the present invention includes an inverter I4 for inverting an input signal in with the power source voltage VDD as a source power source, and an output signal inb of the inverter I4. ) And pull-down driving unit 300 for pull-down driving the nodes b and / b to the power supply voltage VSS level in response to the signal ind inverting the output signal inb of the inverter I4, and the nodes b and / b. The pull-up main driving unit 100 for driving the nodes b and / b to the power supply voltage VPP level by bringing the voltage applied to the cross input, and the pull-up in response to the output signals inb and ind of the inverters I4 and I6. Before the nodes b and / b are pulled up by the main driver 100, the pull-up auxiliary driver 200 for driving the nodes b and / b to the power supply voltage VDD and the node using the power supply voltage VPP as the source power source. An inverter I5 is provided for inverting the voltage applied to / b and outputting it as an output signal out.

Looking at the connection relationship of the above-described voltage level shifter in detail, the voltage level shifter is an inverter I4 receiving an input signal in with the power supply voltage VDD as the source power supply, and an inverter I4 with the power supply voltage VDD being the source power supply. Inverter I6 receiving an output signal inb of the inverter, a pulldown transistor NM4 for pull-down driving node b to the power supply voltage VSS level in response to the output signal inb of the inverter I4, and the inverter I6. A pull-down transistor NM3 for pull-down driving node / b to the power supply voltage VSS level in response to the output signal ind, and a pull-up transistor for pull-up driving node b to the power supply voltage VPP level in response to the signal of node / b. (PM4), pull-up transistor PM3 for pull-up driving node / b to power supply voltage VPP level in response to the signal of node b, and node / b in VDD level in response to output inb of inverter I4. Pull-up transistor (NM5) and inverter And a pull-up transistor for pulling up node b to the VDD level in response to the output ind of the inverter I6, and an inverter I5 receiving a signal from the node / b using the power supply voltage VPP as a source power source.

Next, a brief look at the operation of the voltage level shifter according to an embodiment of the present invention.

First, when the input signal in transitions from the logic level 'low' to 'high', the operation of the NMOS transistors NM3 and NM6 is turned on by the output voltage of the inverter I6 and the NMOS transistor NM6 is turned on. This causes the voltage at node b to rise to VDD-Vt. Therefore, the driving amount of the PMOS transistor PM3 having the node b as the gate input is reduced than before, so that the voltage of the node / b drops to VSS relatively faster than before. Then, the PMOS transistor PM4 having the node / b as the gate input is turned on to gradually increase the voltage of the node b from VDD -Vt to VPP. Since the PMOS transistor PM3 having the node b as the gate input is turned off completely, the voltage of the node / b falls completely to VSS. The voltage applied to the node / b is inverted by the inverter I5 and output as the output signal out.

In addition, when the input signal in transitions from the logic level 'high' to 'low', the NMOS transistors NM4 and NM5 are turned on in response to the output signal of the inverter I4. The voltage of the node / b is increased to VDD-Vt by the NMOS transistor NM5, thereby reducing the time for fighting by turning on both the PMOS transistor PM4 and the NMOS transistor NM4. That is, the PMOS transistor PM4 is completely turned off faster and the voltage at the node / b is fully raised to VPP. The node / b is inverted by the inverter I5 and output as the output signal out.

The above-described voltage level shifter adds NMOS transistors for pull-up driving nodes b and / b of the level shifting portion, thereby reducing the transition time of the output signal, thereby improving the transition characteristics of the output signal. Due to the transition of the input signal, both the PMOS transistors PM3 or PM4 and the NMOS transistors NM3 or NM4 for driving the nodes b and / b of the level shifting part are turned on, and the node voltage is determined by the fighting of these MOS transistors. As described above, an NMOS transistor for driving pull-ups of nodes b and / b can be added to pull up the voltage level of the level shifting node faster, so that the potential of the node is fixed before the positive feedback loop is formed. As a result, the transition time of the output signal is reduced.

In the above-described present invention, the circuit can be configured in an area smaller than that of the conventional circuit by adjusting the size, and the signal transfer characteristic can be made stable.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

In the above-described present invention, since both PMOS transistors and NMOS transistors for driving nodes are turned on and fight in response to the transition of the input signal, the node voltages are determined more quickly in the process of determining the node voltages. An NMOS transistor for driving the node is added to improve the transition characteristics of the output signal.

Claims (6)

A first inverter for inverting the input signal using the first power source as a source power source; A pull-down driving unit configured to pull down the first and second nodes to a second power level in response to a signal inverting the output signal of the first inverter and the output signal of the first inverter; A pull-up main driver configured to pull the voltages applied to the first and second nodes to a cross input to drive the first and second nodes to a third power level; Pull-up assistance for driving the first and second nodes to the level of the first power source before the first and second nodes are pulled up by the pull-up main driver in response to an output signal of the first inverter. A driving unit; And A second inverter for inverting the voltage applied to the second node and outputting it as an output signal using a third power source as a source power source Voltage level shifter having a. A first inverter receiving an input signal using the first power source as a source power source; A second inverter receiving an output signal of the first inverter using a first power source as a source power source; First pull-down means for pulling down the first node to a second power level in response to an output signal of the first inverter; Second pull-down means for pull-down driving a second node to a second power level in response to an output signal of the second inverter; First pull-up means for pulling up the second node to a third power level in response to a signal from the first node; Second pull-up means for pulling up the first node to a third power level in response to a signal from the second node; Third pull-up means for pulling up the second node to the first power level in response to an output of the first inverter; Fourth pull-up means for pulling up the first node to the first power level in response to an output of the second inverter; And A third inverter configured to receive a signal from the second node using a third power source as a source power source Voltage level shifter having a. delete The method according to claim 1 or 2, And the first power supply is a supply power supply voltage. The method of claim 4, wherein And the second power supply is a ground power supply voltage. The method of claim 4, wherein The third power supply is a voltage level shifter, characterized in that the high power supply voltage boosted by the supply power supply voltage.

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