KR100907017B1 - Circuit of semiconductor memory apparatus - Google Patents

Abstract

A level shifter circuit of a semiconductor memory device is provided to minimize collision between a pull-up current and a pull-down current by arranging a driving control part between a pull-up driving part and a pull-down driving part. A level shifter circuit of a semiconductor memory device includes a pull-up driving part(300), a driving control part(400), and a pull-down driving part(500). The pull-up driving part provides a high voltage(VDDH) to a third node(N3) and a fourth node(N4) in response to an input signal(INb) swung between a low voltage(VDDL) and a ground voltage(VSS). The driving control part provides electric potential of the third node and the fourth node to an internal node(IN-node) and an output node(OUT-node) in response to the input signal. The pull-down driving part drives the output node and the internal node by a ground voltage in response to the input signal.

Description

Level circuit of a semiconductor memory device {Circuit of Semiconductor Memory Apparatus}

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a level shifter circuit for use in connecting a circuit using a low voltage with a circuit using a high voltage.

As the power consumption of the semiconductor memory device is lowered, the level of an externally supplied voltage is lowered. Therefore, in order to supply a low voltage level signal applied from the outside of the semiconductor memory device to the internal circuit of the semiconductor memory device using the boosted voltage, a level shifter circuit for converting the low voltage level to the high voltage level is used. That is, the level shifter circuit is a circuit for interfacing circuits using voltages of different levels.

For example, a word line driver of a semiconductor memory device uses a boosted voltage VPP, which is a voltage higher than an external voltage VDD, as a power supply voltage, and a signal for driving the word line driver is connected to an external voltage VDD and a ground. Switch between voltages VSS. The word line driver switches between the boost voltage (VPP) and the ground voltage (VSS). When connecting a circuit whose power voltage is the external voltage (VDD) and a circuit whose power supply voltage is the boost voltage (VPP), a level shifter is used. do.

1 is a circuit diagram of a semiconductor memory device including a level shifter circuit according to the prior art.

Here, a power supply voltage having a low voltage level may be referred to as a low voltage VDDL, and a power supply voltage having a high voltage level may be referred to as a high voltage VDDH, the low voltage VDDL may be an external voltage VDD, and the high voltage VDDH may be boosted. Voltage VPP.

Referring to FIG. 1, a conventional semiconductor memory device includes a first logic circuit 110, a level shifter circuit 120, and a second logic circuit 130.

The first logic circuit 110 includes an inverter IV1 using the low voltage VDDL as a power supply voltage. The inverter IV1 inverts the input signal IN and outputs an input signal INb input to the level shifter circuit 120.

The level shifter circuit 120 includes first and second PMOS transistors PM1 and PM2, first and second NMOS transistors NM1 and NM2, and low voltage VDDL and ground, whose gates are cross-connected to drains. An inverter IV2 using the voltage VSS as a power source is included.

In the level shifter circuit 120, a high voltage VDDH is connected to a source of the first and second PMOS transistors PM1 and PM2, and a ground voltage VSS is connected to a source of the first and second NMOS transistors NM1 and NM2. ) Is connected. The inverter IV2 is connected between the gate of the first NMOS transistor NM1 and the gate of the second NMOS transistor NM2. The level shifter circuit 120 converts the input signal IN of the low voltage VDDL to the output signal OUT1 of the high voltage VDDH.

The second logic circuit 130 includes a third PMOS transistor PM3 and a third NMOS transistor NM3 constituting the inverter. The high voltage VDDH terminal is connected to the source of the third PMOS transistor PM3. The ground voltage VSS terminal is connected to the source of the third NMOS transistor NM3. The second logic circuit 130 inverts the output signal OUT1 having the high voltage VDDH and the ground voltage VSS to output the output signal OUT2 having the high voltage VDDH and the ground voltage VSS.

More specifically, the operation of the level shifter circuit 120 will be described as follows.

First, when the input signal INb transitions from a low level to a high level, the first NMOS transistor NM1 is turned on and the second NMOS transistor NM2 is turned off. Since the pull-down current I1 flows through the turned-on first NMOS transistor NM1, the voltage of the first node N1 drops to the ground voltage VSS. In this case, since the second node N2 is in the state of the ground voltage VSS, the first PMOS transistor PM1 is turned on, and the first node N1 is pulled-up current I3 through the first PMOS transistor PM1. ) Flows. The first node N1 has a voltage level determined by the pull-up current I3 and the pull-down current I1. When the voltage level of the first node N1 is lowered, the second PMOS transistor PM2 is turned on so that the voltage level of the second node N2 approaches the level of the high voltage VDDH. Accordingly, the voltage driving capability of the first PMOS transistor PM1 is reduced, so that the pull-up current I3 is reduced, and the first node N1 is converted to the ground voltage VSS. When the first node N1 is completely converted to the level of the ground voltage VSS, the voltage level of the second node N2 is completely transitioned to the voltage level of the high voltage VDDH. The level shifter circuit outputs a high level output signal OUT1. The second logic circuit 130 receives the high level output signal OUT1 and outputs the low level output signal OUT2.

Here, if the voltage of the second node N2 is lower than the high voltage VDDH, the third PMOS transistor PM3 of the second logic circuit 130 is not completely turned off, so that a leakage current flows.

On the contrary, when the input signal INb transitions from the high level to the low level, the first NMOS transistor NM1 is turned off and the second NMOS transistor NM2 is turned on. Since the second pull-down current I2 flows through the turned-on second NMOS transistor NM2, the potential of the second node N2 starts to fall. At this time, the pull-up current I4 is supplied to the second node N2 through the second PMOS transistor PM2 which is turned on by the potential of the first node N1 before the input signal INb transitions to the low level. Therefore, the potential of the second node N2 drops to the ground voltage VSS level. The voltage of the second node N2 turns on the first PMOS transistor PM1. Therefore, since the pull-up current I3 flows to the first node N1 through the turned-on first PMOS transistor PM1, the voltage level of the first node N1 increases to the voltage level of the high voltage VDDH. . The second PMOS transistor PM2 that receives the voltage level of the first node N1 is turned off, and the pull-up current I4 does not flow to the second node N2. Accordingly, the level shifter circuit outputs a low level output signal OUT1, and the second logic circuit 130 receives a low level output signal OUT1 and outputs a high level output signal OUT2. do.

The level shifter circuit 120 should have a better current driving capability of the first and second NMOS transistors NM1 and NM2 as pull-down elements than those of the first and second PMOS transistors PM1 and PM2 as pull-up elements. Therefore, the size of the first and second NMOS transistors NM2 should be large. That is, to reduce the delay time that occurs when the level transition of the input signal INb occurs. However, in this case, a problem arises in that the area of the level shifter circuit becomes large.

Figure 2 shows another type of level shifter circuit in the prior art.

Referring to FIG. 2, the level shifter circuit 220 connects fourth and fifth PMOS transistors PM4 and PM5 to the high voltage VDDH end of the level shifter 120 shown in FIG. 1, respectively. And the fifth PMOS transistors PM4 and PM5 as the input signal INb.

More specifically, the level shifter circuit 220 according to another exemplary embodiment will be described.

First, when the input signal INb transitions from the low level to the high level, the first NMOS transistor NM1 and the fifth PMOS transistor PM5 are turned on, and the second NMOS transistor NM2 and the fourth PMOS transistor ( PM4) is turned off. Since the pull-down current I1 flows through the first NMOS transistor NM1 after being turned on, the potential of the first node N1 starts to fall. At this time, the first PMOS transistor PM1 is turned on by the potential of the second node N2 before the input signal INb transitions to the high level. However, since the fourth PMOS transistor PM4 interrupts the supply of the high voltage VDDH, the pull-up current I3 does not flow to the first node N1. The potential of the first node N1 quickly drops to the ground voltage VSS. When the potential of the first node N1 falls, the second PMOS transistor PM2 is turned on. Accordingly, since the pull-up current I4 flows to the second node N2 through the fifth PMOS transistor PM5 and the second PMOS transistor PM2, the second node N2 is connected to the high voltage VDDH. Rises to the voltage level. When the second node N2 rises to the voltage level of the high voltage VDDH, the first PMOS transistor PM1 is turned off, and the pull-up current I3 does not flow to the first node N1.

On the contrary, when the input signal INb transitions from the high level to the low level, the second NMOS transistor NM2 and the fourth PMOS transistor PM4 are turned on, and the first NMOS transistor NM1 and the fifth PMOS transistor are turned on. PM5 is turned off. The potential of the second node N2 starts to fall to the voltage level of the ground voltage VSS. At this time, although the second PMOS transistor PM2 is turned on by the potential of the first node N1 before the input signal INb transitions to the low level, the fifth PMOS transistor PM5 supplies the high voltage VDDH. Because of blocking the pull-up current (I4) does not flow to the second node (N2). Thereafter, the operation outputs the output signal OUT1 through a process as shown in FIG. 1.

However, since the level of the input signal INb for turning on / off the fourth and fifth PMOS transistors PM4 and PM5 is the level of the low voltage VDDL, the fourth and fifth PMOS transistors PM4 and PM5. Cannot be turned on / off completely. As a result, the first node N1 slows down to the ground voltage VSS level by the pull-up current I3 and the pull-down current I1 due to the leakage current. Similarly, the second node N2 also slows down to the ground voltage VSS level by the pull-up current I4 and the pull-down current I2 having the leakage current. Thus, the operation of the level shifter circuit 220 is slowed down.

The operating speed of the conventional level shifter circuits 120 and 220 is controlled by the collision of the pullup currents I3 and I4 and the pulldown currents I1 and I2. That is, when the collision between the pull-up currents I3 and I4 and the pull-down currents I1 and I2 is eliminated, the transition speed of the voltage levels of the level shifter circuits 120 and 220 increases.

In the level shifter circuits 120 and 220 according to the related art, when the input signal INb transitions from the high level to the low level, the voltage of the second node N2 is higher than the ground voltage VSS due to the coupling effect. Lower to low voltage. In this case, in order to recover the voltage of the second node N2, the second NMOS transistor NM2 is turned on so that the voltage of the second node N2 is converted to a low level to turn on the first PMOS transistor PM1. do. If the coupling effect is large due to the delay time caused in this process, the level does not shift from the low voltage VDDL to the high voltage VDDH.

The level shifter circuit of the semiconductor memory device according to the present invention has a purpose to provide a stable and fast operating speed.

A level shifter circuit of a semiconductor memory device according to the present invention provides a voltage higher than a first voltage to a first node in response to a signal of an output node, and a second in response to a signal of an internal node having a phase opposite to that of the output node. A pull-up driver configured to provide a voltage higher than the first voltage to the node, and selectively supply the voltage higher than the first voltage to the first node and the second node; In response to an input signal swinging between the first and ground voltages, providing the internal node with the voltage of the first node, providing the output node with the voltage of the second node, the internal node and the A drive controller configured to provide an output node with voltages of the first and second nodes selectively; And a pull-down driver configured to drive the output node and the internal node to the ground voltage in response to the input signal.

The level shifter circuit of the semiconductor memory device according to the present invention has an effect that a stable operation and faster operation speed can implement a more reliable circuit.

3 is a level shifter circuit of a semiconductor memory device according to the present invention.

In the conventional level shifter circuit, the voltage of the internal node through which the pull-down current passes is lowered below the ground voltage (VSS) level due to the coupling effect generated by the pull-down current. At this time, the internal node may not rise to the full high voltage VDDH due to the pull-up device that is not turned on completely. Due to the collision between the pull-up current and the pull-down current of the output node having an inversion level with the internal node, a delay time until the voltage of the output node reaches a low voltage (VSS) or a high voltage (VDDH) occurs. That is, the overall operation speed is slowed down due to the delay time until the pull-up element is completely turned on. The present invention includes a current controller for controlling a pull-up current transmitted to an internal node or an output node between the node connecting the pull-up element and the pull-down element, so that the voltage level of the internal node or the output node is quickly lowered and rises quickly. The circuit is implemented to do this.

Referring to FIG. 3, a level shifter of a semiconductor memory device may generate a high voltage at a third node N3 and a fourth node N4 in response to an input signal INb swinging between a low voltage VDDL and a ground voltage VSS. A pull-up driving unit 300 for providing and blocking VDDH, and the potentials of the third node N3 and the fourth node N4 in response to the input signal INb, and the internal node IN_node; The driving control unit 400 for providing and blocking the output node OUT_node, and the output node OUT-node and the internal node IN-node in response to the input signal INb are provided with a ground voltage ( And a pull-down driver 500 for driving with VSS.

Herein, the signal of the IN-node and the signal of the OUT-node are signals having differential pair levels that are opposite in phase to each other.

The level shifter circuit of the semiconductor memory device according to the present invention is configured to generate a voltage of the output node OUT-node as the high voltage VDDH or the low voltage VDDL in response to the input signal INb. The driving controller 400 may be provided between the pull-down driver 500 to minimize the collision between the pull-up current and the pull-down current.

The pull-up driver 300 includes sixth and seventh PMOS transistors PM6 and PM7 configured to be switched to be opposite to each other. The sixth PMOS transistor PM6 includes a gate connected to the output node OUT_node, a source connected to the high voltage VDDH, and a drain connected to the third node N3. The seventh PMOS transistor PM7 includes a gate connected to the internal node IN_node, a source connected to the high voltage VDDH, and a drain connected to the fourth node N4.

The driving controller 400 includes eighth and ninth PMOS transistors PM8 and PM9 configured to be switched to be opposite to each other. The eighth PMOS transistor PM8 includes a gate configured to receive an input signal INb, a source connected to the third node N3, and a drain connected to the internal node IN_node. The ninth PMOS transistor PM9 includes a gate configured to receive an inverted signal of the input signal INb, a source connected to the fourth node N4, and a drain connected to the output node OUT_node.

The pull-down driver 500 includes fourth and fifth NMOS transistors NM4 and NM5 that receive differential input signals INb, and a third inverter IV3 that inverts and outputs the input signal INb. do. The fourth NMOS transistor NM4 includes a gate configured to receive an input signal INb, a source connected to the internal node IN-node, and a drain connected to a ground voltage VSS terminal. The fifth NMOS transistor NM5 includes a gate configured to receive an inverted signal of the input signal INb, a source connected to the output node OUT_node, and a drain connected to the ground voltage VSS terminal.

More specifically, the level shifter circuit of the present invention will be described.

First, a case where the input signal INb transitions from the high level to the low level will be described. For example, if the input signal INb is at the high level, the voltage of the internal node IN_node may also be grounded by the coupling effect. ) Is lower than At this time, since the input signal INb transitions to the low level, the fourth NMOS transistor NM4 is turned off and the eighth PMOS transistor PM8 is completely turned on, so that the voltage of the third node N3 is turned on. Is provided to the internal node IN_node. Subsequently, the potential of the internal node IN_node rises quickly to turn off the seventh PMOS transistor PM7 quickly. The fifth NMOS transistor NM5 is turned on and the ninth PMOS transistor PM9 is turned off while the input signal INb transitions to a low level. Therefore, the potential of the output node OUT_node quickly drops to the level of the ground voltage VSS. The potential of the low level output node OUT_node turns on the sixth PMOS transistor PM6, rapidly provides a high voltage VDDH to the third node N3, and the eighth PMOS transistor PM8 A high voltage VDDH is provided to the internal node IN_node. Accordingly, the internal node IN_node has a level of high voltage VDDH, and the output node OUT_node has a level of ground voltage VSS. That is, when the input signal INb transitions from the high level to the low level, the ninth PMOS transistor PM9 is turned on by the low voltage VDDL, so that the driving capability is finer than when the high voltage VDDH is input. Therefore, the potential of the output node OUT_node has a larger driving capability of the pull-down current I9 than the supply of the pull-up current I8, and therefore rapidly drops to the level of the ground voltage VSS.

In the level shifter circuit of the present invention, when the input signal INb transitions from the high level to the low level, the output node OUT-node is pulled down to the ground voltage VSS stage rather than the supplied pull-up current I8. The driving ability of the current I6 is better, and the internal node IN_node has better driving capability than the pull-down current I5 from which the pull-up current I7 supplied is discharged to the ground voltage VSS terminal.

On the contrary, when the input signal INb transitions from the low level to the high level, the output node OUT has a driving capability of the pull-down current I6 from which the pull-up current I8 supplied is discharged to the ground voltage VSS terminal. The internal node IN_node has a better driving capability than the pull-down current I5 discharged to the ground voltage VSS stage than the pull-up current I7 supplied.

That is, under the same conditions, it has a faster transition time than the conventional level shifters shown in Figs. 1 and 2, and the current consumption is also small.

4 is a level shifter circuit of a semiconductor memory device according to another exemplary embodiment.

4 includes a pull-down unit 600 for accelerating driving capability of a node connected between the pull-up driver 300 and the drive controller 400 of the level shifter circuit shown in FIG. 3 in response to an input signal INb.

Referring to FIG. 4, a level shifter circuit of a semiconductor memory device according to another exemplary embodiment includes a pull-up driver 300, a drive controller 400, a pull-down driver 500, and a pull-down unit 600.

Since the pull-up driving unit 300, the driving control unit 400, and the pull-down driving unit 500 are the level shifter circuits shown in FIG. 3, redundant description will be omitted.

The pull-down unit 600 accelerates the conversion of the potentials of the third node N3 and the fourth node N4 to the level of the ground voltage VSS in response to the input signal INb.

The pull-down unit 600 is connected to the first pull-down unit 610 and the input signal INb to pull down the third node N3 to the level of the ground voltage VSS in response to the input signal INb. In response, the second pull-down unit 620 pulls down the fourth node N3 to the level of the ground voltage VSS. The first pull-down unit 610 includes a sixth NMOS transistor NM6. The sixth NMOS transistor NM6 receives an input voltage INb, includes a drain connected to the third node N3, and a source connected to the ground voltage VSS terminal. The second pull-down unit 620 includes a seventh NMOS transistor NM7. The seventh NMOS transistor NM7 includes a gate configured to receive an inverted signal of the input signal INb, a drain connected to the fourth node N4, and a source connected to the ground voltage VSS terminal.

More specifically, the operation of the level shifter circuit of the semiconductor memory device according to another embodiment is as follows.

The operation of the level shifter circuit shown in FIG. 3 is the same, but the level shifter circuit according to another embodiment turns on the seventh NMOS transistor NM7 when the input signal INb transitions from a high level to a low level. In this case, since the potential of the fourth node N4 is generated at the level of the ground voltage VSS, the ninth PMOS transistor PM9 is completely turned off, and the potential of the output node OUT_node is set to the ground voltage. VSS) is lowered faster than the level shifter shown in FIG. At this time, the turn-on time of the sixth PMOS transistor PM6 is faster, and the internal node IN-node is generated at a level of high voltage VDDH more quickly, so that the overall operation of the level shifter circuit is faster.

In the opposite case (ie, when the input signal INb transitions from the low level to the high level), the sixth NMOS transistor NM6 is turned on to turn the third node N3 to the ground voltage VSS. By generating the level, the internal node (In-node) is lowered more quickly to the level of the ground voltage (VSS). Accordingly, the turn-on speed of the seventh PMOS transistor PM7 is also increased, and as the speed generated at the level of the high voltage VDDH to the output node OUT_node is increased, the operation speed of the level shifter circuit is increased.

5 is a timing diagram of a delay time between the level shifter circuit of FIG. 2 and the level shifter circuit of FIG. 3.

Referring to FIG. 5, it may be determined that the output signal OUT1 of the level shifter circuit of FIG. 3 is generated a predetermined time earlier than the output signal OUT1 of the level shifter circuit of FIG. 2. That is, the level shifter circuit of FIG. 3 has a higher driving capability than the first and second PMOS transistors PM1 and PM2 shown in FIG. 2. small. When the input signal INb transitions from a high level to a low level, the pull-up current I7 has a better pull-up driving capability than the pull-up current I3 shown in FIG. 2, and the pull-down current I6 is shown in FIG. 2. Since the pull-down driving capability is superior to the pull-down current I2 shown in Fig. 2, the output speed of the output signal OUT1 is faster than the level shifter circuit of FIG. When the input signal INb transitions from a low level to a high level, the pull-up current I8 has a better pull-up driving capability than the pull-up current I4 shown in FIG. 2, and the pull-down current I5 is shown in FIG. 2. Since the pull-down driving capability is superior to the pull-down current I1 shown in Fig. 2, the output speed of the output signal OUT1 is faster than the level shifter circuit of FIG.

6 is a timing diagram for current consumption of the level shifter circuit of FIG. 2 and the level shifter circuit of FIG. 3.

Referring to FIG. 6, the output signal OUT1 of the level shifter circuit of FIG. 3 may be smaller than the output signal OUT1 of the level shifter circuit of FIG. 2. It can be seen that the level shifter circuit of FIG. 2 has a higher operating current than the level shifter circuit of FIG.

The level shifter circuit according to the present invention minimizes the collision between the pull-up current and the pull-down current than the conventional level shifter shown in FIGS. 1 and 2, thereby performing a more stable operation and improving the operation speed.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and equivalent concepts are included in the scope of the present invention. Should be interpreted.

1 is a semiconductor memory device including a level shifter circuit according to the prior art,

2 is a semiconductor memory device including a level shifter circuit according to another exemplary embodiment of the present invention;

3 is a level shifter circuit of a semiconductor memory device according to the present invention;

4 is a level shifter circuit of a semiconductor memory device according to another embodiment of the present disclosure;

5 is a timing diagram of an output signal of the level shifter circuit shown in FIG. 2 and the level shifter circuit shown in FIG.

6 is a timing diagram of current consumption of the level shifter circuit shown in FIG. 2 and the level shifter circuit shown in FIG.

<Explanation of symbols for the main parts of the drawings>

300: pull-up drive unit 400: drive control unit

500: pull-down drive unit 600: pull-down unit

Claims (9)

Providing a voltage higher than the first voltage to the first node in response to the signal of the output node and providing a voltage higher than the first voltage to the second node in response to the signal of the internal node having a phase opposite to the output node; A pull-up driver configured to selectively provide a voltage higher than the first voltage to the first node and the second node; In response to an input signal swinging between the first and ground voltages, providing the internal node with the voltage of the first node, providing the output node with the voltage of the second node, the internal node and the A drive control configured to selectively provide an output node with voltages of the first and second nodes, and And a pull-down driving unit configured to drive the output node and the internal node to the ground voltage in response to the input signal. The method of claim 1, The pull-up drive unit, If the internal node signal is at a ground voltage level, supply a voltage higher than the first voltage to the second node, And supplying a voltage higher than the first voltage to the first node when the output node signal is at a ground voltage level. The method of claim 1, The drive control unit, If the input signal is at the first voltage level, connect the first node and the internal node, And the second node and the output node are connected when the input signal is at the ground voltage level. The method of claim 1, The pull-down drive unit, If the input signal is the first voltage level, the output node and the ground voltage terminal is connected, And if the input signal is at the ground voltage level, connecting the internal node and the ground voltage terminal. The method of claim 1, And a pull-down unit configured to pull down the first node and the second node in response to the input signal. The method of claim 5, wherein The pull-down unit, A first pull-down unit for pulling down the first node in response to the input signal, and And a second pull-down section for pulling down the second node in response to the input signal. The method of claim 6, The pull-down unit, If the input signal is the first voltage level, connect the first node with a ground voltage terminal, And when the input signal is at the ground voltage level, connecting the second node to a ground voltage terminal. The method of claim 1, The first voltage is, An external voltage level shifter circuit of a semiconductor memory device. The method of claim 1, The voltage higher than the first voltage, A level shifter circuit of a semiconductor memory device, characterized in that the boost voltage.

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