JP4604610B2 - Inkjet recording head drive waveform generation circuit and inkjet recording apparatus - Google Patents

Description

  The present invention relates to a drive waveform generation circuit for an inkjet recording head and an inkjet recording apparatus, and more particularly, inkjet recording that records an image by ejecting ink droplets based on a drive signal corresponding to image data indicating a recorded image. The present invention relates to a drive waveform generation circuit for a head and an inkjet recording apparatus using the inkjet recording head and the drive waveform generation circuit.

  Conventionally, a pressure generating chamber filled with ink is volume-changed (expanded / contracted) using an actuator such as a piezoelectric element, and a nozzle formed in communication with the pressure generating chamber by a change in internal pressure due to this volume change. 2. Related Art An ink jet recording apparatus (so-called ink jet printer) including an ink jet recording head that discharges ink droplets from the tip is known.

  As a technique related to a drive waveform generation circuit that generates a drive waveform for driving the actuator of the ink jet recording head as described above, conventionally, a plurality of waveform generation circuits that output a plurality of types of drive waveforms within one printing cycle are provided. A technology that enables a plurality of gradations to be obtained within one drive cycle by selecting one of a plurality of types of drive waveforms according to waveform selection data based on the gradation data and supplying the selected one to the actuator. (For example, see Patent Document 1).

  In this technique, a trapezoidal wave shape is applied as the drive waveform, so that meniscus perturbation of the ink liquid level can be precisely controlled, and high-quality image recording with multiple gradations can be realized.

  However, in this technique, it is necessary to make the waveform generating circuit large in order to make the drive waveform trapezoidal.

  Therefore, as a technique that can solve this problem, there has conventionally been a technique that applies a pulse signal having two voltage levels (a so-called binary pulse signal) as the drive waveform.

  According to this technique, since the drive waveform generation circuit can be configured with a simple switching circuit, the drive waveform generation circuit can be reduced in size.

  However, this technique has a problem that it is difficult to record high-quality images with multiple gradations because of poor controllability of meniscus perturbation.

  Therefore, as a technique that can be applied to solve this problem, conventionally, there has been a technique that applies a pulse signal having three or more voltage levels as a drive waveform (for example, Patent Document 2, Patent Document 3, and Patent Document 4). reference.).

According to this technique, if the number of voltage levels of the drive waveform is close to 2, the drive waveform generation circuit can be reduced in size as in the case of the binary pulse signal, and compared with the case of the binary pulse signal. Thus, the controllability of meniscus perturbation can also be improved.
JP 2001-26102 A JP-A-9-66603 JP-A-9-29961 JP-A-9-123445

  However, in the technique of applying the pulse signal having three or more voltage levels as the drive waveform described above, each voltage level is switched by an independent switching circuit. Therefore, the switching circuit and the independent circuit are independent according to the voltage level. There was a problem that a control signal was required and the control was complicated.

  The present invention has been made to solve the above-described problems, and is a drive waveform of an ink jet recording head that can generate a drive waveform with high controllability of meniscus perturbation with simple control without causing an increase in size. It is an object to provide a generation circuit and an ink jet recording apparatus.

  In order to achieve the above object, the drive waveform generation circuit for an ink jet recording head according to claim 1 is supplied with drive waveforms having three voltage levels and discharges ink droplets according to the supplied drive waveforms. A drive waveform generation circuit for an ink jet recording head provided with an element, wherein a voltage having two voltage levels among the voltage levels of the drive waveform is applied, and a first waveform signal indicating a predetermined waveform is input In response to the signal level of the first waveform signal, the first signal generating unit that outputs one of the two applied voltage levels and the first signal generating unit output the voltage. A voltage having a third voltage level that is not applied to the first signal generation unit of the voltage and the voltage level of the drive waveform is applied, and the first A second waveform signal having a waveform different from the waveform of the waveform signal is input, and one of the two applied voltage levels is output as the drive waveform according to the signal level of the second waveform signal. Second signal generating means.

  The drive waveform generation circuit according to claim 1 is supplied to a drive waveform having three voltage levels and supplied to an ink jet recording head provided with an energy element for ejecting ink droplets according to the supplied drive waveform. The drive waveform is generated.

  Here, in the drive waveform generation circuit according to the present invention, a voltage having two voltage levels among the voltage levels of the drive waveform is applied, and a first waveform signal indicating a predetermined waveform is input. In accordance with the signal level of the first waveform signal, one of the two applied voltage levels is output by the signal generating means.

  In the drive waveform generation circuit according to the present invention, the voltage output from the first signal generation unit and the voltage level included in the drive waveform are not applied to the first signal generation unit. In response to the signal level of the second waveform signal, the second signal generation means receives a second waveform signal having a waveform different from the waveform of the first waveform signal. Thus, one of the two applied voltage levels is output as the drive waveform.

  Here, the principle of the present invention will be described with reference to FIG. 1A shows a specific example of a drive waveform according to the present invention, and FIG. 1B shows a preferable specific example of a drive waveform generation circuit to which the present invention is applied.

  As shown in FIG. 1A, the driving waveform assumed here has three voltage levels GND (ground level), HV1, and HV2. Further, as shown in FIG. 1B, the first signal generation means and the second signal generation means assumed here are a P-channel MOS FET (hereinafter referred to as “PMOS”) and an N-channel. The inverter circuit is configured by connecting MOS FETs (hereinafter referred to as “NMOS”) in series.

  In this case, two of the three voltage levels (voltage level GND and voltage level HV1 in the figure) are applied to the first signal generation means, and the voltage levels GND, HV1, and HV2 are applied. A first waveform signal S1 having a predetermined waveform is input, and the first signal generation means receives either one of two applied voltage levels according to the signal level of the first waveform signal S1. Is output. That is, in the example shown in the figure, when the signal level of the first waveform signal S1 is high, the PMOS is turned off and the NMOS is turned on, so that the voltage level of the output voltage is the voltage level GND. . On the other hand, when the signal level of the first waveform signal S1 is low, the PMOS is turned on and the NMOS is turned off, so that the voltage level of the output voltage is the voltage level HV1. As a result, the voltage output from the first signal generating means has the same waveform as the inverted waveform of the first waveform signal S1, and has two voltage levels, that is, the voltage level GND and the voltage level HV1.

  On the other hand, the second signal generation means includes the voltage output from the first signal generation means and the remaining of the three voltage levels GND, HV1, and HV2 (voltage level HV2 in the figure). And a second waveform signal S2 having a predetermined waveform different from that of the first waveform signal S1 is input, and the second signal generating unit is configured to respond to the signal level of the second waveform signal S2. One of the two applied voltage levels is output as a drive waveform. That is, in the example shown in the figure, when the signal level of the second waveform signal S2 is high, the PMOS is turned off and the NMOS is turned on, so that the voltage level of the output voltage is the first signal generation. The voltage is the same as the voltage output from the means (the waveform is the same as the inverted waveform of the first waveform signal S1, and the voltage level has two voltage levels GND and HV1). On the other hand, when the signal level of the second waveform signal S2 is low, the PMOS is on and the NMOS is off, so that the voltage level of the output voltage is the voltage level HV2. As a result, the voltage (drive waveform) output from the second signal generation unit is output from the first signal generation unit and the second signal generation unit in accordance with the first waveform signal S1 and the second waveform signal S2, respectively. A voltage level GND, a voltage level HV1, and a voltage level HV2 are combined as voltage levels.

  In the present invention, since the drive waveform having three voltage levels is generated as described above, the controllability of the meniscus perturbation can be enhanced as compared with the drive waveform having two voltage levels, and the ink droplet The first waveform signal and the second waveform signal fixedly determined in advance according to the type of ejection amount (the number of gradations of the recorded image) and the like are input to the first signal generation unit and the second signal generation unit. A drive waveform can be generated by simple control only. Furthermore, in the present invention, the first signal generating means and the second signal generating means can be configured with a simple configuration as shown in FIG. 1B as an example, so that the circuit scale is very small. be able to.

  As described above, according to the drive waveform generation circuit for an ink jet recording head according to claim 1, a drive waveform having three voltage levels to be supplied for driving an energy element for ejecting ink droplets to the ink jet print head is generated. In doing so, the first waveform is applied by the first signal generating means to which the voltage of two voltage levels of the voltage levels of the drive waveform is applied and the first waveform signal indicating the predetermined waveform is input. According to the signal level of the signal, one of the two applied voltage levels is output, and the voltage output from the first signal generation unit and the voltage level of the drive waveform have the above-described voltage level. A voltage of a third voltage level that is not applied is applied to the first signal generating means, and a waveform different from the waveform of the first waveform signal is shown. According to the second signal generation means to which the two waveform signals are input, one of the two applied voltage levels is output as the drive waveform in accordance with the signal level of the second waveform signal. Therefore, a driving waveform with high controllability of meniscus perturbation can be generated with simple control without causing an increase in size.

  In the present invention, as illustrated in FIG. 1, the first signal generation unit and the second signal generation unit may be an inverter circuit configured by connecting a pair of switching elements in series. .

  In the present invention, as illustrated in FIG. 1, each of the first waveform signal and the second waveform signal is a waveform having a binary value that can turn on and off the switching element. Accordingly, the drive waveform can be shown by combining the voltages respectively output from the first signal generating means and the second signal generating means.

  According to a fourth aspect of the present invention, the drive waveform has four or more voltage levels as in the fourth aspect of the present invention, and the gap is between the first signal generation unit and the second signal generation unit. Any one of the voltage output from the previous signal generation means and the voltage level of the drive waveform that is not applied to the first signal generation means and the second signal generation means While a voltage is applied, waveform signals that are different from the waveforms of the first waveform signal and the second waveform signal and that are different from each other are input and applied according to the signal level of the waveform signal. The number of the third signal generation means for outputting any one of the two voltage levels to the subsequent signal generation means may be provided in accordance with the number of voltage levels of the drive waveform.

  Particularly, according to the invention described in claim 4, as in the invention described in claim 5, the third signal generating means may be an inverter circuit configured by connecting a pair of switching elements in series.

  Further, according to a fifth aspect of the present invention, as in the sixth aspect of the present invention, the waveform signal has a binary waveform that can turn on and off the switching element of the third signal generating means. And 4 by combining the voltage output from the third signal generation means in accordance with the waveform and the voltage output from the first signal generation means and the second signal generation means, respectively. A drive waveform having more than one voltage level may be shown.

  On the other hand, in order to achieve the above object, an ink jet recording apparatus according to claim 7 is generated by the drive waveform generation circuit according to any one of claims 1 to 6 and the drive waveform generation circuit. And an ink jet recording head provided with an energy element for ejecting ink droplets according to the supplied driving waveform.

  According to an ink jet recording apparatus according to a seventh aspect, the ink jet recording head provided with an energy element that ejects ink droplets according to the supplied driving waveform is provided with any one of the first to sixth aspects. A drive waveform generated by the described drive waveform generation circuit is supplied. The ink jet recording head has a long shape having a width substantially equal to the width of the recording medium (recording paper), and performs recording while transporting only the recording paper without being moved. Is shorter than the width of the recording medium and includes recording while moving in the main scanning direction.

  Thus, according to the ink jet recording apparatus of the seventh aspect, the drive waveform generation circuit of the present invention is applied as the drive waveform generation circuit that generates the drive waveform to be supplied to the ink jet recording head. Similar to the circuit, a driving waveform with high controllability of meniscus perturbation can be generated with simple control without causing an increase in size.

  According to the present invention, as in the invention described in claim 8, the inspection means for inspecting the state of an ejector that ejects ink droplets by driving energy elements provided in the ink jet recording head, and the drive waveform generation circuit A power source that applies the voltage of the third voltage level to the second signal generation unit, a point of application of the voltage of the third voltage level in the second signal generation unit, the inspection unit, and the power source And a switching unit that is selectively interposed between the inspection unit and the power source with respect to the application point, and when the image is recorded by the inkjet recording head, the application point and the When the state of the ejector is inspected by the inspection means, the switching means is controlled so that the application point and the inspection means are connected. Means may further comprise a.

  As described above, according to the present invention, it is possible to obtain an excellent effect that a drive waveform with high meniscus perturbation controllability can be generated with simple control without causing an increase in size.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  First, the ink jet recording apparatus 10 according to the present embodiment will be described with reference to FIGS.

  FIG. 2 is a diagram showing a main part configuration of the ink jet recording apparatus 10 according to the present embodiment. Here, the configuration of the peripheral part of the ink jet recording head is mainly shown except for the recording paper transport system.

  As shown in the figure, the inkjet recording apparatus 10 according to the present embodiment includes a controller 12 that controls the operation of the entire inkjet recording apparatus 10 and a plurality of piezoelectric elements 30 that eject ink droplets according to the supplied drive waveform. An ink jet recording head 14 provided, and a semiconductor substrate 16 provided with a drive control circuit to be described later for supplying the drive waveform to the ink jet recording head 14 are provided.

  The ink jet recording head 14 according to the present embodiment is a long one having a width substantially equal to the width of the recording paper. That is, the inkjet recording apparatus 10 is configured as a so-called FWA (Full Width Array) type inkjet recording apparatus that performs recording while transporting only the recording paper while the inkjet recording head 14 is fixed.

  Further, the ink jet recording head 14 according to the present embodiment includes a pressure generating chamber filled with ink, an ink discharge port that communicates with the pressure generating chamber and can discharge ink, and a wall surface of the pressure generating chamber. A vibrating plate that expands or contracts the pressure generating chamber by vibrating, and a piezoelectric element that vibrates the vibrating plate by being deformed by a voltage applied according to image data indicating an image to be recorded A large number of actuators including the (piezo element) 30 are provided along the longitudinal direction.

  However, the ink jet recording head of the present invention is not limited to the ink jet recording head corresponding to the FWA system as described above and using a large number of piezoelectric elements, and a piezoelectric element that ejects ink droplets according to a supplied drive signal. Any device can be applied as long as it is provided.

  A semiconductor substrate 16 is connected to the controller 12, and the operation of the drive control circuit provided on the semiconductor substrate 16 is controlled by a clock signal, a selection signal, and a latch signal, and a waveform signal that is a pair of signals. A, waveform signal B, waveform signal C, and the like are used by controller 12.

  On the other hand, in the ink jet recording apparatus 10, the inspection unit 18 that inspects the state of the ejector 32 that ejects ink droplets by driving the piezoelectric element 30 provided in the ink jet recording head 14, and drive control provided in the semiconductor substrate 16. A second power source 20 that applies a voltage of a predetermined voltage level (corresponding to a “third voltage level” of the present invention) to the circuit, an application point of the voltage of the predetermined voltage level in the drive control circuit, and an inspection unit 18. A switching unit 22 is provided that is interposed between the second power source 20 and selectively connects either the inspection unit 18 or the second power source 20 to the application point.

  Here, the switching unit 22 is connected to the controller 12. When the controller 12 records an image with the ink jet recording head 14, the application point and the second power source 20 are connected, and the inspection unit 18 ejects the ejector 32. When the state is inspected, the application point and the inspection unit 18 are controlled to be connected.

  FIG. 3 shows the configuration of the drive control circuit 40 provided on the semiconductor substrate 16 according to the present embodiment.

  As shown in the figure, the drive control circuit 40 according to the present embodiment includes a shift register 42, a latch circuit 44, a selector 46, a level shifter 48, and a drive waveform generation circuit 50.

  The clock signal and selection signal output from the controller 12 are input to the shift register 42, and the latch signal is input to the latch circuit 44.

  The selection signal is a signal for selecting one (a pair of signals) of the waveform signal A, the waveform signal B, and the waveform signal C. The waveform signal A selection signal 42A, the waveform signal B selection signal 42B, the waveform This is a serial signal composed of the signal C selection signal 42C. The waveform signal A selection signal 42A, the waveform signal B selection signal 42B, and the waveform signal C selection signal 42C are signals indicating 1-bit data that is “0” or “1”, respectively. The waveform signal A selection signal 42A is “1” when the waveform signal A is selected, and is “0” when the waveform signal A is not selected. The waveform signal B selection signal 42B is “1” when the waveform signal B is selected, and is “0” when the waveform signal B is not selected. Further, the waveform signal C selection signal 42C is “1” when the waveform signal C is selected, and is “0” when the waveform signal C is not selected.

  That is, the selection signal is “100” when selecting the waveform signal A, “010” when selecting the waveform signal B, and “001” when selecting the waveform signal C. It becomes. Such selection signals are continuously input to the shift register 42 by the number of the piezoelectric elements 30.

  In the following, a case where a drive waveform is supplied to one piezoelectric element 30 will be described, but the same applies to the other piezoelectric elements 30 and thus the description thereof will be omitted.

  The shift register 42 converts the input selection signal, which is 3-bit serial data, into 3-bit parallel data and outputs it to the latch circuit 44.

  The latch circuit 44 latches (self-holds) the parallel data output from the shift register 42 according to the input of the latch signal.

  The selector 46 receives the waveform signal A, the waveform signal B, and the waveform signal C from the controller 12 as selection target signals, and the selection signal parallel data latched by the latch circuit 44 is input to the select terminal. Therefore, the selector 46 selects and outputs the waveform signal A, the waveform signal B, and the waveform signal C that are selected by the selection signal.

  The waveform signal output terminal of the selector 46 is connected to the level shifter 48, and the waveform signal output from the selector 46 is level-converted by the level shifter 48 and output. The level shifter 48 is supplied with power of a predetermined voltage level (a predetermined level exceeding 40 V in this embodiment) HVDD from a third power source (not shown), and the level shifter 48 has a waveform selected by a selection signal. The signal is level-converted to a voltage level corresponding to the voltage level HVDD.

  As the level shifter 48, a conventionally known level shifter can be applied. However, in the present embodiment, a circuit configuration using four series of PMOS and NMOS series circuits shown in FIG. 4 is applied. ing. Note that the circuit shown in the figure corresponds to one of a pair of waveform signals input from the selector 46, and therefore, in practice, two sets of the circuits are necessary. Further, the circuit shown in FIG. 6 is also adapted to level conversion of a signal obtained by inverting one of the waveform signals, but this portion is not used in this embodiment.

  On the other hand, the drive waveform generation circuit 50 according to the present embodiment includes a first signal generation circuit 52 as a first signal generation unit and a second signal generation circuit 54 as a second signal generation unit. ing.

  The first signal generation circuit 52 according to the present embodiment is configured as an inverter circuit configured by connecting PMOS 52A and NMOS 52B in series. Similarly, the second signal generation circuit 54 is also configured by connecting PMOS 54A and NMOS 54B in series. The inverter circuit is configured as described above.

  That is, in the first signal generation circuit 52, the drains of the PMOS 52A and the NMOS 52B are connected to each other, and the gates of the PMOS 52A and the NMOS 52B are connected. Similarly, in the second signal generation circuit 54, the drains of the PMOS 54A and the NMOS 54B are connected to each other, and the gates of the PMOS 54A and the NMOS 54B are connected.

  Here, the source of the PMOS 52A in the first signal generation circuit 52 has a power set to a predetermined voltage level HV1 (a predetermined level in the range from 10V to 30V in this embodiment) from a first power supply (not shown). Are supplied, and the source of the NMOS 52B is grounded to the ground level. Further, one output terminal of the level shifter 48 is connected to each gate of the PMOS 52A and the NMOS 52B, and one of the pair of waveform signals selected by the selector 46 and the waveform signal S1 whose level is converted by the level shifter 48 are input. Is done.

  Therefore, in the first signal generation circuit 52, when the signal level of the waveform signal S1 input from the level shifter 48 is high, the PMOS 52A is turned off and the NMOS 52B is turned on. Become ground level. In contrast, when the signal level of the waveform signal S1 input from the level shifter 48 is low, the PMOS 52A is on and the NMOS 52B is off, so that the voltage level of the output voltage is the voltage level HV1. As a result, the voltage output from the first signal generation circuit 52 has the same waveform as the inverted waveform of the waveform signal S1 input from the level shifter 48, and has two voltage levels: ground level and voltage level HV1. It becomes.

  On the other hand, the switching unit 22 is connected to the source of the PMOS 54 </ b> A in the second signal generation circuit 54. Accordingly, either the inspection unit 18 or the second power supply 20 is connected to the source of the PMOS 54A via the switching unit 22 under the control of the controller 12. The second power supply 20 is configured to supply power at a predetermined voltage level HV2 (in this embodiment, a predetermined level within a range from 20 V to 40 V). When the power supply 20 is connected to the source of the PMOS 54A, the voltage at the voltage level HV2 is applied to the source.

  The connection point (drain) of the PMOS 52A and the NMOS 52B in the first signal generation circuit 52 is connected to the source of the NMOS 54B in the second signal generation circuit 54. Therefore, the inverter output of the first signal generation circuit 52 is applied to the source of the NMOS 54B. Further, the other output terminal of the level shifter 48 is connected to the gates of the PMOS 54A and the NMOS 54B, and the other of the pair of waveform signals selected by the selector 46 and the waveform signal S2 whose level has been converted by the level shifter 48 are input. Is done.

  Accordingly, in the second signal generation circuit 54, when the signal level of the waveform signal S2 input from the level shifter 48 is high, the PMOS 54A is turned off and the NMOS 54B is turned on. The voltage level of the waveform is the same as the voltage output from the first signal generation circuit 52 (the waveform is the same as the inverted waveform of the waveform signal input from the level shifter 48, and the voltage level is the ground level and the voltage level HV1). 2). In contrast, when the signal level of the waveform signal S2 input from the level shifter 48 is low, the PMOS 54A is on and the NMOS 54B is off, so that the voltage level of the output voltage (drive waveform) is the voltage level. It becomes HV2. As a result, the voltage (drive waveform) output from the second signal generation circuit 54 is output from the first signal generation circuit 52 and the second signal generation circuit 54 in accordance with the pair of waveform signals S1 and S2 input from the level shifter 48. The output voltage is a combination of three output voltages: a ground level, a voltage level HV1, and a voltage level HV2.

  FIG. 5 shows an example of the drive waveform applied to the piezoelectric element 30, the output waveform of the first signal generation circuit 52 alone and the output of the second signal generation circuit 54 required to generate the drive waveform. An example of a waveform is shown.

  As shown in the figure, when the voltage level of the drive waveform is desired to be the voltage level HV2, the voltage level of the output waveform from the second signal generation circuit 54 is set to the voltage level HV2. Therefore, in this case, the waveform signal S2 input to the second signal generation circuit 54 may be set to a low level. In this case, since the output of the first signal generation circuit 52 does not affect the output of the second signal generation circuit 54, the level of the waveform signal S1 input to the first signal generation circuit 52 is not limited.

  On the other hand, when the voltage level of the drive waveform is desired to be the voltage level HV1, the voltage level of the output waveform from the first signal generation circuit 52 is set to the voltage level HV1, and the voltage level of the output waveform from the second signal generation circuit 54 is set. Needs to be at the voltage level HV1. Therefore, in this case, it is necessary to set the waveform signal S1 input to the first signal generation circuit 52 to the low level and the waveform signal S2 input to the second signal generation circuit 54 to the high level.

  Further, when the voltage level of the drive waveform is desired to be the ground level, the voltage level of the output waveform from the first signal generation circuit 52 is set to the ground level, and the voltage level of the output waveform from the second signal generation circuit 54 is also set to the ground level. Need to be level. Therefore, in this case, it is necessary to set the waveform signal S1 input to the first signal generation circuit 52 to the high level and also set the waveform signal S2 input to the second signal generation circuit 54 to the high level.

  Table 1 shows a truth table showing the operation of the drive waveform generation circuit 50 according to the present embodiment when the second power supply 20 is connected by the switching unit 22. In the table, S1 indicates a waveform signal input to the first signal generation circuit 52, S2 indicates a waveform signal input to the second signal generation circuit 54, and OUT corresponds from the second signal generation circuit 54. The voltage level of the drive waveform supplied to the piezoelectric element 30 is shown.

  When the waveform signals S1 and S2 to be input to the first signal generation circuit 52 and the second signal generation circuit 54 are generated, a desired drive waveform is finally obtained based on the truth table shown in Table 1. A pair of waveform signal A, waveform signal B, and waveform signal C may be generated and supplied to the drive control circuit 40 so as to be obtained. FIG. 10 shows an example of the waveform signal S1 input to the first signal generation circuit 52, the waveform signal S2 input to the second signal generation circuit 54, and the drive waveform generated by these waveform signals. ing.

  In the inkjet recording apparatus 10 according to the present embodiment, three types of “large droplets”, “medium droplets”, and “small droplets” are applied as types of ink droplets ejected by driving the piezoelectric element 30. The controller 12 generates a waveform signal A, a waveform signal B, and a waveform signal C as three sets of waveform signals that can generate drive waveforms corresponding to each of the three types of ejection amounts. , And is input to the drive control circuit 40.

  In the inkjet recording apparatus 10 according to the present embodiment, the relationship between the voltage level HVDD of power supplied from a third power supply (not shown) and the voltage level HV2 of power supplied from the second power supply 20 (voltage level). HVDD ≧ voltage level HV2), and the relationship between the voltage level HV2 and the voltage level HV1 of the power supplied from the first power source (not shown) is (voltage level HV2> voltage level HV1).

  By the way, in the ink jet recording apparatus 10 according to the present embodiment, the state of the ejector 32 that ejects ink droplets by driving the piezoelectric element 30 provided in the ink jet recording head 14 is determined at a predetermined timing (in this embodiment, the ink jet The controller 12 controls the switching unit 22 to connect the test unit 18 to the drive control circuit 40 at the timing of execution of the diagnostic mode. .

  The test executed in the diagnosis mode according to the present embodiment uses a predetermined reflected wave detection signal (in this embodiment, a single pulse signal having a voltage level of 20 V and a width of 1 μsec) as a drive waveform. Applied to the piezoelectric element 30 to be inspected, and when the piezoelectric element 30 vibrates accordingly, the pressure generating chamber corresponding to the piezoelectric element 30 is opposite to the side where the piezoelectric element 30 is disposed. By detecting the voltage level of the voltage generated by the piezoelectric element 30 according to the intensity of the reflected wave from the inner surface and determining whether the voltage level is detected at a predetermined level or higher, the abnormality of the ejector 32 is detected. It is supposed to check for the presence or absence. That is, since the pressure generating chamber is filled with ink, the voltage level of the voltage generated in the piezoelectric element 30 by the reflected wave becomes lower as the viscosity of the ink becomes higher. Using this point, in the diagnosis mode according to the present embodiment, it is inspected whether the viscosity of the ink is abnormally high.

  FIG. 6 shows a main configuration of the inspection unit 18 according to the present embodiment.

  As shown in the figure, the inspection unit 18 includes a reflected wave detection unit 18A and a control unit 18B.

  The input terminal of the reflected wave detecting unit 18A is connected to the switching unit 22, and when the reflected wave detecting unit 18A is connected to the drive control circuit 40 by the switching unit 22, the reflected wave detecting unit 18A includes a second of the drive waveform generating circuit 50. The source of the PMOS 54A in the signal generation circuit 54 is connected. Therefore, the reflected wave detection signal is used as the drive waveform applied to the piezoelectric element 30 to be inspected by using the waveform signals S1 and S2 input to the first signal generation circuit 52 and the second signal generation circuit 54 in the drive waveform generation circuit 50. Is generated, and the piezoelectric element 30 is vibrated. Immediately thereafter, the waveform signal S2 input to the second signal generation circuit 54 is changed to a signal that turns on the PMOS 54A. A voltage at a voltage level indicating the intensity of the reflected wave is applied to the wave detector 18A. The reflected wave detector 18A generates digital data indicating the applied voltage level, that is, digital data indicating the intensity of the reflected wave.

  On the other hand, the reflected wave detection unit 18A is connected to the control unit 18B, and digital data indicating the intensity of the reflected wave is input from the reflected wave detection unit 18 to the control unit 18B. Then, the control unit 18B determines whether or not the ejector to be inspected is in an abnormal state by determining whether or not the input digital data is greater than or equal to a predetermined threshold value.

  On the other hand, the control unit 18B is connected to the controller 12, and the control unit 18B outputs information indicating whether or not the ejector is in an abnormal state (hereinafter referred to as “inspection result information”) to the controller 12.

  Next, with reference to FIG. 7, an operation when the diagnosis mode is executed will be described as an operation of the ink jet recording apparatus 10 according to the present embodiment. FIG. 7 shows a diagnostic processing program executed by the controller 12 when the predetermined timing (in this embodiment, the timing when the inkjet recording apparatus 10 is turned on) is reached and the diagnostic mode is executed. It is a flowchart which shows the flow of a process.

  In step 100 in the figure, the switching unit 22 is controlled to connect the inspection unit 18 to the drive control circuit 40, and in the next step 102, the first signal generation circuit 52 and the second signal generation in the drive waveform generation circuit 50 are controlled. The reflected wave detection signal is generated as a drive waveform for applying the waveform signals S1 and S2 input to the circuit 54 to any of the piezoelectric elements 30 (hereinafter referred to as “processing target piezoelectric elements”) in the inkjet recording head 14. In the next step 104, the waveform signal S2 input to the second signal generation circuit 54 is changed to one that turns on the PMOS 54A.

  As described above, the inspection result information is output from the control unit 18B of the inspection unit 18 by the above processing. Therefore, in the next step 106, input of the inspection result information is waited, and in the next step 108, The received inspection result information is stored in a nonvolatile memory (not shown) in a state associated with identification information for identifying the processing target piezoelectric element.

  In the next step 110, it is determined whether or not the recording of the inspection result information has been completed for all the piezoelectric elements 30 provided in the ink jet recording head 14. When the determination is made, the routine proceeds to step 112. In addition, when repeatedly executing the processing of step 102 to step 110, the piezoelectric element 30 that has not been processed until then is applied as a processing target piezoelectric element.

  In step 112, with reference to the inspection result information regarding all the piezoelectric elements stored in the non-volatile memory, it is determined whether there is an ejector that is in an abnormal state. Goes to step 114.

  In step 114, an inspection result reflection process is executed, and after the abnormal state is notified to the user in the next step 116, the process proceeds to step 118. If the determination in step 112 is negative, the process proceeds to step 118 without executing the processes in steps 114 and 116.

  In the inkjet recording apparatus 10 according to the present embodiment, as the inspection result reflecting process in step 114, the drive waveform for the piezoelectric element 30 in the ejector assumed to be in an abnormal state is not generated thereafter. Processing for changing the waveform signal corresponding to the piezoelectric element 30 is performed. As a result, it is possible to prevent a secondary failure caused by ink ejection by the ejector in an abnormal state. Further, in the inkjet recording apparatus 10 according to the present embodiment, as a notification to the user in the above step 116, the occurrence of an abnormal state of the ejector is displayed by a liquid crystal panel (not shown) provided in the inkjet recording apparatus 10. Information is applied.

  In step 118, the switching unit 22 is controlled so as to connect the second power source 20 to the drive control circuit 40, and then the diagnostic processing program is terminated.

  As described above in detail, according to the drive waveform generation circuit according to the present embodiment, 3 is supplied for driving the energy element (here, the piezoelectric element 30) that causes the ink jet recording head to eject ink droplets. When generating a drive waveform having one voltage level, two voltage levels (here, the ground level and the voltage level HV1) of the voltage levels of the drive waveform are applied and a predetermined waveform is shown. The first waveform signal (here, the waveform signal S1) is applied by the first signal generation means (here, the first signal generation circuit 52) according to the signal level of the first waveform signal. One of the two voltage levels is output, and the voltage output from the first signal generation means and the voltage level of the drive waveform are included. A voltage of a third voltage level (here, voltage level HV2) that is not applied is applied to the first signal generating means, and a second waveform showing a waveform different from the waveform of the first waveform signal. The second signal generation means (here, the second signal generation circuit 54) to which the signal (here, the waveform signal S2) is input, is applied in accordance with the signal level of the second waveform signal. Since one of the voltage levels is output as the drive waveform, a drive waveform with high meniscus perturbation controllability can be generated with simple control without causing an increase in size.

  According to the present embodiment, the first signal generation unit and the second signal generation unit are configured by connecting a pair of switching elements (here, PMOS 52A and NMOS 52B, and PMOS 54A and NMOS 54B) in series. Since the inverter circuit is provided, the present invention can be realized with a simple configuration.

  In addition, according to the drive waveform generation circuit according to the present embodiment, the first waveform signal and the second waveform signal have a binary waveform that can turn on and off the switching element, respectively. Since the drive waveform is shown by combining the voltages output from the first signal generation unit and the second signal generation unit according to each waveform, the first waveform signal and the second waveform signal are It can be created easily.

  On the other hand, according to the ink jet recording apparatus according to the present embodiment, the drive waveform generating circuit as described above is applied as the drive waveform generating circuit that generates the drive waveform supplied to the ink jet recording head. Similar to the generation circuit, a drive waveform with high controllability of meniscus perturbation can be generated with simple control without causing an increase in size.

  Furthermore, according to the ink jet recording apparatus according to the present embodiment, the inspection unit (in this case, the inspection unit 18) for inspecting the state of the ejector that ejects ink droplets by driving the piezoelectric element provided in the ink jet recording head; A power supply (here, the second power supply 20) for applying a voltage of the third voltage level to the second signal generation means of the drive waveform generation circuit, and the third voltage level in the second signal generation means Switching means (here, switching) that is interposed between the voltage application point and the inspection means and the power source, and selectively connects either the inspection means or the power source to the application point. 22), and when the image is recorded by the ink jet recording head by the control means (here, the controller 12), the application point and the power source are connected. When the inspection unit inspects the state of the ejector, the switching unit is controlled so that the application point and the inspection unit are connected. Therefore, the ejector of the ink jet recording head can be configured with a simple configuration. Inspection can be performed.

  In the present embodiment, the case where the drive waveform generation circuit of the present invention is configured to generate a drive waveform for four gradations has been described, but the present invention is not limited to this, The drive waveform generation circuit of the invention can be configured to generate a drive waveform for five gradations or more.

  FIG. 8 shows a configuration example of a main part in the ink jet recording apparatus 10A in this case. In the figure, the same components as those in FIG. 2 are denoted by the same reference numerals as those in FIG.

  As shown in the figure, in this case, the number of waveform signals supplied to the drive control circuit of the semiconductor substrate 16A is a number corresponding to the number of types of drive waveforms to be generated (the number of gradations).

  In this case, as compared with the ink jet recording apparatus 10 according to the present embodiment, an image can be recorded by the ink jet recording head with more gradations.

  In the present embodiment, the drive waveform generation circuit of the present invention is described as generating a drive waveform having three voltage levels. However, the present invention is not limited to this, The drive waveform generation circuit of the invention may be configured to generate a drive waveform having four or more voltage levels.

  FIG. 9 shows a configuration example of the drive control circuit 40A in this case and generating a drive waveform for five gradations or more. In FIG. 3, the same components as those in FIG. 3 are denoted by the same reference numerals as those in FIG.

  As shown in the figure, in this case, the number of third signal generation circuits 56 corresponding to the number of voltage levels of the drive waveform to be generated is between the first signal generation circuit 52 and the second signal generation circuit 54. Is provided.

  Here, the third signal generation circuit 56 is a first signal of the voltage output from the previous stage signal generation circuit (the first signal generation circuit 52 or the third signal generation circuit 56) and the voltage level of the drive waveform. Any one of the voltage levels not applied to the generation circuit 52 and the second signal generation circuit 54 is applied, and the waveform signal input to the first signal generation circuit 52 and the second signal generation circuit 54 A waveform signal that is different from each waveform and that shows a different waveform is input, and one of the two applied voltage levels is converted into a signal generation circuit in the subsequent stage according to the signal level of the waveform signal ( The signal is output to the second signal generation circuit 54 or the third signal generation circuit 56).

  In the example shown in the figure, the third signal generation circuit 56 is configured by connecting a pair of switching elements (PMOS 56A and NMOS 56B) in series, like the first signal generation circuit 52 and the second signal generation circuit 54. The inverter circuit. In this case, the waveform signal input to the third signal generation circuit 56 is a waveform having a binary value that can turn on and off the switching element of the third signal generation circuit 56, and according to the waveform. Drive waveforms indicating the four or more voltage levels are shown by combining the voltage output from each third signal generation circuit 56 and the voltage output from each of the first signal generation circuit 52 and the second signal generation circuit 54. Shall.

  In this case, since a drive waveform having four or more voltage levels can be generated, the controllability of meniscus perturbation can be further improved as compared with the present embodiment.

  Further, in the present embodiment, the case where the drive waveform generation circuit of the present invention is configured using only a signal generation circuit configured by a series circuit of PMOS and NMOS has been described, but the present invention is not limited to this. The circuit configuration shown in FIG. 11 may be used instead.

  First, in FIG. 11A, an NMOS is applied to the second signal generation circuit 54 according to the present embodiment instead of the PMOS 54A. In this case, the waveform signal input to the NMOS gate needs to be an inverted signal of the waveform signal S2. Since the level shifter 48 (see also FIG. 4) applied in the drive control circuit 40 according to the present embodiment can also level-convert the inverted signal of the waveform signal, the level shifter 48 and the waveform signal S2 are concerned. This configuration can be easily accommodated only by inputting an inverted signal of the waveform signal S2.

  On the other hand, in FIG. 11B, a PMOS is newly connected in parallel to the NMOS of the second signal generation circuit 54 according to the present embodiment, and N / PMOS transmission is performed by the NMOS and the PMOS. A gate is constructed. In this case, the impedance characteristic can be made flat, and the stability can be improved over a wide range of power supply voltages.

  FIG. 11D shows a modification of that shown in FIG. 11B, in which an NMOS is newly connected in parallel to the PMOS of the second signal generation circuit 54 according to the present embodiment. An N / PMOS transmission gate is constituted by the PMOS and NMOS. Also in this case, the impedance characteristic can be made flat, and the stability can be improved over a wide range of power supply voltages.

  Further, in FIG. 11C, a PMOS and NMOS series circuit having the same configuration as that of the second signal generation circuit 54 is newly added to the second signal generation circuit 54 according to the present embodiment. Are connected in parallel, and this configuration can improve the stability most among the configurations shown in FIG.

In the present embodiment, the case where the inspection executed in the diagnosis mode is to inspect the abnormal state of the ejector from the detection result of the reflected wave when the piezoelectric element 30 is driven by applying a single pulse is described. However, the present invention is not limited to this. For example, the piezoelectric element 30 has a predetermined bias voltage (for example, 10V) and has a predetermined frequency (for example, the resonance frequency of the ejector). In addition, a sine wave signal having a predetermined amplitude (for example, 1 V _PP ) is applied, the impedance of the piezoelectric element 30 at this time is measured, and it is determined whether or not the measured value is within a predetermined reference range. Thus, the impedance characteristic of the piezoelectric element can be inspected. Also in this case, the same effects as in the present embodiment can be obtained. In this case, it is preferable to inspect a plurality of frequencies near the resonance frequency including the resonance frequency of the ejector as the predetermined frequency. As a result, a more detailed inspection can be performed.

  Further, in the present embodiment, the case where the diagnosis mode is executed at the timing when the inkjet recording apparatus 10 is turned on has been described. However, the present invention is not limited to this, and for example, the factory of the inkjet recording apparatus 10 Timing at the time of shipment, timing from when a print request is received until printing is started, timing at which the inkjet recording head 14 moves to the maintenance section during execution of printing, timing after completion of printing, printing standby time It is also possible to adopt a form in which the diagnosis mode is executed at any one timing at which a user's diagnosis request is received at an arbitrary timing, or at a plurality of these timings. Also in this case, the same effects as in the present embodiment can be obtained.

  In the present embodiment, the waveform signal corresponding to the piezoelectric element 30 is changed so that the drive waveform for the piezoelectric element 30 is not generated for the ejector 32 determined to be in an abnormal state as a result of the examination in the diagnostic mode. Although the present invention has been described, the present invention is not limited to this. For example, in an abnormal state by changing the voltage amplitude of the drive waveform or changing the pulse width of the drive waveform according to the degree of abnormality. It is also possible to change the drive waveform so that the ink discharge amount is about the same as that of the non-ejector. In this case, since the ink can be ejected also to the ejector in an abnormal state, it is possible to realize high-quality image formation as compared with the present embodiment.

  In addition, the configuration of the inkjet recording apparatus 10 described in the present embodiment, the drive waveform, and the state of the waveform signal (see FIGS. 2 to 6 and FIGS. 8 to 11) are merely examples, and depart from the gist of the present invention. Needless to say, it can be appropriately changed within a range not to be performed.

  Furthermore, the flow of the diagnostic processing program described in the present embodiment (see FIG. 7) is also an example, and it goes without saying that the flow can be appropriately changed without departing from the gist of the present invention.

2A and 2B are diagrams for explaining the principle of the present invention, in which FIG. 1A is a waveform diagram illustrating an example of a drive waveform, and FIG. 2B is a circuit diagram illustrating a configuration example of a drive waveform generation circuit according to the present invention; 1 is a schematic diagram illustrating a main configuration of an ink jet recording apparatus according to an embodiment. It is a block diagram (partial circuit diagram) showing a configuration of a drive control circuit according to an embodiment. It is a circuit diagram which shows the structure of the level shifter which concerns on embodiment. It is a wave form diagram which shows the example of the drive waveform which concerns on embodiment, and the example of the output waveform of the 1st signal generation circuit independent required in order to produce | generate the said drive waveform, and the output waveform of the 2nd signal generation circuit alone . It is a block diagram which shows the structure of the test | inspection part which concerns on embodiment. It is a flowchart which shows the flow of a process of the diagnostic processing program which concerns on embodiment. It is the schematic which shows the principal part structure of the modification of the inkjet recording device which concerns on embodiment. It is a block diagram (partial circuit diagram) showing a configuration of a modified example of the drive control circuit according to the embodiment. It is a wave form diagram which shows the example of the waveform signal S1 input into the 1st signal generation circuit which concerns on embodiment, the waveform signal S2 input into the 2nd signal generation circuit, and the drive waveform produced | generated by these waveform signals. It is a circuit diagram which shows the structure of the modification of the drive waveform generation circuit which concerns on embodiment.

Explanation of symbols

10, 10A Inkjet recording device 12 Controller (control means)
14 Inkjet recording head 18 Inspection section (inspection means)
20 Second power supply
22 Switching section (switching means)
DESCRIPTION OF SYMBOLS 30 Piezoelectric element 32 Ejector 50, 50A Drive waveform generation circuit 52 1st signal generation circuit (1st signal generation means)
52A PMOS (switching element)
52B NMOS (switching element)
54 Second signal generation circuit (second signal generation means)
54A PMOS (switching element)
54B NMOS (switching element)
56 Third signal generation circuit (third signal generation means)
56A PMOS (switching element)
56B NMOS (switching element)
S1 waveform signal S2 waveform signal

Claims (8)

A drive waveform generation circuit for an ink jet recording head provided with an energy element that is supplied with drive waveforms having three voltage levels and ejects ink droplets according to the supplied drive waveforms,
Two voltages of the voltage levels of the drive waveform are applied, and a first waveform signal indicating a predetermined waveform is input and applied according to the signal level of the first waveform signal. First signal generating means for outputting one of the two voltage levels;
Of the voltage output from the first signal generation means and the voltage level of the drive waveform, a voltage of a third voltage level not applied to the first signal generation means is applied, and A second waveform signal having a waveform different from the waveform of the first waveform signal is input, and one of two applied voltage levels is set as the drive waveform in accordance with the signal level of the second waveform signal. Second signal generating means for outputting as:
A drive waveform generation circuit for an ink jet recording head comprising: 2. The drive waveform generation of an ink jet recording head according to claim 1, wherein the first signal generation unit and the second signal generation unit are inverter circuits configured by connecting a pair of switching elements in series. circuit. Each of the first waveform signal and the second waveform signal is a waveform having a binary value that can turn on and off the switching element, and the first signal generation unit and the second waveform signal corresponding to each waveform. The drive waveform generation circuit for an ink jet recording head according to claim 2, wherein the drive waveform is displayed by combining voltages output from the signal generation means. The driving waveform has four or more voltage levels;
Between the first signal generation means and the second signal generation means, the first signal generation means and the first of the voltage output from the previous signal generation means and the voltage level of the drive waveform Any one of the unapplied voltage levels is applied to the signal generating means 2 and the waveforms of the first waveform signal and the second waveform signal are different and different from each other. The third signal generating means for inputting the waveform signal and outputting either one of the two applied voltage levels to the subsequent signal generating means in accordance with the signal level of the waveform signal is driven. The drive waveform generation circuit for an ink jet recording head according to any one of claims 1 to 3, wherein a number corresponding to the number of voltage levels of the waveform is provided. 5. The drive waveform generation circuit for an ink jet recording head according to claim 4, wherein the third signal generation means is an inverter circuit configured by connecting a pair of switching elements in series. The waveform signal is a waveform having a binary value that can turn on and off the switching element of the third signal generation unit, and a voltage output from the third signal generation unit according to the waveform The drive waveform having the four or more voltage levels is represented by combining the voltage output from each of the first signal generation unit and the second signal generation unit. 6. A drive waveform generation circuit for an inkjet recording head according to item 5. The drive waveform generation circuit according to any one of claims 1 to 6,
An ink jet recording head provided with an energy element that is supplied with the drive waveform generated by the drive waveform generation circuit and ejects ink droplets according to the supplied drive waveform;
An ink jet recording apparatus comprising: Inspection means for inspecting the state of an ejector that ejects ink droplets by driving energy elements provided in the ink jet recording head;
A power supply for applying a voltage of the third voltage level to the second signal generating means of the drive waveform generating circuit;
One of the inspection means and the power supply is interposed between the application point of the voltage of the third voltage level in the second signal generation means and the inspection means and the power supply. Switching means for selectively connecting one;
The application point and the power source are connected when an image is recorded by the ink jet recording head, and the application point and the inspection unit are connected when the state of the ejector is inspected by the inspection unit. Control means for controlling the switching means;
The inkjet recording apparatus according to claim 7, further comprising:

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