JP2008125095A - Semiconductor circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a leak current of a logic circuit in which a logic during a standby mode is not determined. <P>SOLUTION: Inverters 30, whose output logic levels during the standby mode become equal with each other, are connected between a buffer power line 24 and a buffer ground line 28. Inverters 32 of which output levels during the standby mode are different from the output logic levels but become equal with each other, are connected between a buffer power line 22 and a buffer ground line 26. In response to an output signal of a latch circuit 44, the buffer power lines 22, 24 are connected to a main power line 10 or a sub power line 12 by power supply selectors 34, 36 and the buffer ground lines 26, 28 are connected to a main ground line 16 or a sub ground line 18 by power supply selectors 38, 40. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor circuit device, and more particularly to a semiconductor circuit device having a hierarchical power supply configuration.

  In recent semiconductor memories, the threshold value of a transistor tends to decrease as the operating power supply voltage decreases. When the threshold value of the transistor is lowered, the subthreshold leakage current increases. In order to prevent this, various SCRC (Subthreshold Current Reduced Control) techniques have been developed (see, for example, Patent Document 1). ).

  On the other hand, internal control of DRAM (Dynamic Random Access Memory) is divided into row and column operations, but with the recent increase in the number of banks and the independent operation for each bank, the circuit configuration for bank control has been increased. In addition, the number of circuits as a whole chip increases, and as a result, the standby leakage current tends to increase.

  According to the SCRC technique described above, in order to reduce the subthreshold leakage current during standby, the sub power supply line and the sub ground line are provided in addition to the main power supply line and the main ground line. A logic circuit such as a CMOS inverter circuit that outputs a L (logic low) level signal by connecting a logic circuit such as a CMOS inverter circuit that outputs a level signal between the main power supply line and the sub power supply line. A hierarchical power supply configuration has been proposed in which a sub power supply line and a main ground line are connected to each other, and the sub power supply line and the sub ground line are electrically disconnected from the main power supply line and the main ground line, respectively, during standby.

In such a hierarchical power supply configuration, the source of the P channel MOS transistor in the CMOS inverter circuit that outputs an H level signal is connected to the main power supply line, but the source of the N channel MOS transistor is connected to the sub-ground line. Has been. Therefore, during standby, the source potential of the N channel MOS transistor becomes higher than the ground potential, and as a result, the subthreshold leakage current of the N channel MOS transistor is reduced. On the other hand, the source of the N channel MOS transistor in the CMOS inverter circuit that outputs the L level signal is connected to the main ground line, while the source of the P channel MOS transistor is connected to the sub power supply line. Therefore, the source potential of the P channel MOS transistor becomes lower than the power supply potential during standby, and as a result, the subthreshold leakage current of the P channel MOS transistor is reduced.
JP-A-6-237164

  The above-described hierarchical power supply configuration can be adopted for a logic circuit whose output signal logic level is fixed during standby, but the hierarchical power supply configuration cannot be adopted for an uncertain logic circuit. For this reason, such a logic circuit has to be connected between the main power supply line and the main ground line, and the subthreshold leakage current during standby cannot be reduced.

  In particular, in the latch circuit, since it is not certain which signal of the logic level is latched during standby, the subthreshold leakage current cannot be reduced by the hierarchical power supply configuration described above.

  An object of the present invention is to provide a semiconductor circuit device capable of reducing a subthreshold leakage current even for a logic circuit in which the logic level of an output signal during standby is indefinite.

  Another object of the present invention is to provide a semiconductor circuit device capable of reducing subthreshold leakage current in a latch circuit.

  According to one aspect of the present invention, a semiconductor circuit device having an operation mode and a standby mode includes a main power supply line, a sub power supply line, a first switching element, a main ground line, a sub ground line, and a second power supply line. Switching elements, a first buffer power supply line, a first buffer ground line, a second buffer power supply line, a second buffer ground line, a plurality of first logic circuits, and a plurality of second logic circuits. The logic circuit and selection means are provided. The main power supply line receives a power supply voltage. The first switching element is connected between the main power supply line and the sub power supply line, and is turned on in the operation mode and turned off in the standby mode. The main ground line receives a ground voltage. The second switching element is connected between the main ground line and the sub ground line, and is turned on in the operation mode and turned off in the standby mode. Each of the first logic circuits is connected between the first buffer power supply line and the first buffer ground line, and supplies an output signal of the first logic level in the standby mode. Each of the second logic circuits is connected between the second buffer power supply line and the second buffer ground line, and outputs a second logic level output signal complementary to the first logic level in the standby mode. Supply. In the standby mode, the selection unit supplies a logic high level signal as a first logic level by a plurality of first logic circuits and an output signal at a logic low level as a second logic level by a plurality of second logic circuits. , The first buffer power line is connected to the main power line, the first buffer ground line is connected to the sub-ground line, the second buffer power line is connected to the sub-power line, and the second Connect the buffer ground wire to the main ground wire. The selection means also supplies the logic low level output signal as the first logic level and the plurality of second logic circuits as the logic high level as the second logic level in the standby mode. When supplying an output signal, the first buffer power line is connected to the sub power line, the first buffer ground line is connected to the main ground line, the second buffer power line is connected to the main power line, and The second buffer ground line is connected to the sub ground line.

  Preferably, the selection means includes a first selector, a second selector, a third selector, and a fourth selector. The first selector selects the main power supply line or the sub power supply line and connects it to the first buffer power supply line. The second selector selects the main ground line or the sub ground line and connects it to the first buffer ground line. The third selector selects the main power supply line or the sub power supply line and connects it to the second buffer power supply line. The fourth selector selects the main ground line or the sub ground line and connects it to the second buffer ground line.

More preferably, the first selector includes a first P-channel MOS transistor and a second P-channel MOS transistor. The first P-channel MOS transistor is connected between the main power supply line and the first buffer power supply line. The second P-channel MOS transistor is connected between the sub power supply line and the first buffer power supply line. The second selector includes a first N channel MOS transistor and a second N channel MOS transistor. The first N-channel MOS transistor is connected between the main ground line and the first buffer ground line. The second N channel MOS transistor is connected between the sub ground line and the first buffer ground line. The third selector includes a third P channel MOS transistor and a fourth P channel MOS transistor. The third P-channel MOS transistor is connected between the main power supply line and the second buffer power supply line. The fourth P-channel MOS transistor is connected between the sub power supply line and the second buffer power supply line. The fourth selector includes a third N-channel MOS transistor and a fourth N-channel MOS transistor.
A transistor. The third N-channel MOS transistor is connected between the main ground line and the second buffer ground line. The fourth N-channel MOS transistor is connected between the sub ground line and the second buffer ground line.

  In the semiconductor circuit device, the logic circuit is selectively connected between the main power supply line and the sub ground line or between the sub power supply line and the main ground line in accordance with the logic level of the output signal to be supplied from the logic circuit. Therefore, even if the logic level of the output signal in the standby mode is indefinite, the subthreshold leakage current is reduced by adopting the hierarchical power supply configuration.

  According to another aspect of the present invention, a semiconductor circuit device having an operation mode and a standby mode includes a main power supply line, a sub power supply line, a first switching element, a main ground line, a sub ground line, 2 switching elements, a plurality of first logic circuits, a plurality of second logic circuits, and voltage supply means. The main power supply line receives a power supply voltage. The first switching element is connected between the main power supply line and the sub power supply line, and is turned on in the operation mode and turned off in the standby mode. The main ground line receives a ground voltage. The second switching element is connected between the main ground line and the sub ground line, and is turned on in the operation mode and turned off in the standby mode. Each of the first logic circuits is connected between the main power supply line and the sub ground line, and supplies an output signal of the first logic level in the standby mode. Each of the second logic circuits is connected between the sub power supply line and the main ground line, and supplies an output signal having a second logic level complementary to the first logic level in the standby mode. In the standby mode, the voltage supply means supplies a plurality of first logic circuits as a first logic level as a logic low level output signal and a plurality of second logic circuits as a second logic level as a logic high level. When supplying an output signal, a voltage lower than the ground voltage is supplied to the sub-ground line. The voltage supply means also supplies a logic high level output signal as a first logic level by the plurality of first logic circuits and a logic low as the second logic level in the standby mode. When supplying a level output signal, a voltage higher than the power supply voltage is supplied to the sub power supply line.

  Preferably, the voltage supply means includes a first selector and a second selector. The first selector selectively connects the sub power supply line to a node receiving a voltage higher than the power supply voltage. The second selector selectively connects the sub ground line to a node receiving a voltage lower than the ground voltage.

  More preferably, the first selector includes a P channel MOS transistor connected between a node receiving a voltage higher than the power supply voltage and the sub power supply line. The second selector includes an N channel MOS transistor connected between a node receiving a voltage lower than the ground voltage and the sub ground line.

  In the semiconductor circuit device, a voltage lower than the ground voltage is supplied to the sub ground line or a voltage higher than the power supply voltage is supplied to the sub power line according to the logic level of the output signal to be supplied from the logic circuit. Therefore, even if the logic circuit has an indefinite logic level of the output signal, the subthreshold leakage current is reduced by adopting the hierarchical power supply configuration.

  According to still another aspect of the present invention, a semiconductor circuit device having an operation mode and a standby mode includes a main power supply line, a switching element, a main ground line, a latch fixed power supply line, a latch fixed ground line, A logic circuit, a latch circuit, and a shut-off means. The switching element is connected between the node receiving the power supply voltage and the main power supply line, and is turned on in the operation mode and turned off in the standby mode. The latch fixed power supply line receives a power supply voltage. The latch fixed ground line receives a ground voltage. Each of the logic circuits is connected between a main power supply line and a main ground line. The latch circuit is connected between the latch fixed power line and the latch fixed ground line. The blocking means blocks signal input to the latch circuit in the standby mode.

  Preferably, the blocking means includes a latch drive power supply line, drive means, and an inverter circuit. The drive means supplies a power supply voltage to the latch drive power supply line during the operation mode, and supplies a ground voltage or a voltage lower than that to the latch drive power supply line during the standby mode. The inverter circuit receives a voltage from the latch drive power supply line and is inserted into a signal input path to the latch circuit.

  Alternatively, the blocking means includes a latch drive ground line, a first drive means, a first transistor, and a second transistor. The first driving means supplies a ground voltage to the latch drive ground line in the operation mode, and supplies a voltage higher than the ground voltage to the latch drive ground line in the standby mode. The first transistor is connected between one input node of the latch circuit and the latch drive ground line, and has a gate for receiving the first signal. The second transistor is connected between the other input node of the latch circuit and the latch drive ground line, and has a gate for receiving a second signal complementary to the first signal.

  More preferably, the blocking means further includes a second driving means and a third driving means. The second driving means supplies a power supply voltage to the latch fixed power supply line in the operation mode, and supplies a voltage higher than the power supply voltage to the latch fixed power supply line in the standby mode. The third driving means supplies a ground voltage to the latch fixed ground line in the operation mode, and supplies a voltage higher than the ground voltage to the latch fixed ground line in the standby mode.

  Alternatively, the blocking means includes a latch drive ground line, a first transistor, a second transistor, a first drive means, a second drive means, and a third drive means. The first transistor is connected between one input node of the latch circuit and the latch drive ground line, and has a gate for receiving the first signal. The second transistor is connected between the other input node of the latch circuit and the latch drive ground line, and has a gate for receiving a second signal complementary to the first signal. The first drive means temporarily supplies the ground voltage to the latch drive ground line during input of the first and second signals in the operation mode, and supplies the power supply voltage to the latch drive ground line at other times. The second driving means supplies a power supply voltage to the latch fixed power supply line in the operation mode, and supplies a voltage higher than the power supply voltage to the latch fixed power supply line in the standby mode. The third driving means temporarily supplies the power supply voltage to the latch fixed ground line during input of the first and second signals in the operation mode, and supplies the ground voltage to the latch fixed ground line at other times in the operation mode. In the standby mode, a voltage higher than the ground voltage is supplied to the latch fixed ground line.

  In the semiconductor circuit device, since the switching element is turned off in the standby mode, the subthreshold leakage current hardly flows in the logic circuit. However, since the power supply voltage and the ground voltage are supplied to the latch circuit, the latch circuit can continuously latch the signal even in the standby mode. In addition, since the signal input to the latch circuit is blocked in the standby mode, the latch circuit does not latch a random signal.

  More preferably, the semiconductor circuit device is a synchronous dynamic random access memory. The latch circuit latches a row-related command signal in the synchronous dynamic random access memory.

  Alternatively, the latch circuit latches a row address signal in the synchronous dynamic random access memory.

  Alternatively, the latch circuit latches a column-related command signal in the synchronous dynamic random access memory.

Alternatively, the latch circuit latches a column address signal in the synchronous dynamic random access memory.

  In the synchronous dynamic random access memory, the latch circuit can continue to latch a row or column command or address signal even during the standby mode.

  As described above, according to the present invention, the logic circuit is arranged between the main power supply line and the sub ground line or between the sub power supply line and the main ground line according to the logic level of the output signal to be supplied from the logic circuit. Since it is configured to be selectively connected, the subthreshold leakage current can be reduced by adopting the hierarchical power supply configuration even if the logic level of the output signal is indefinite.

  In addition, a voltage lower than the ground voltage is supplied to the sub ground line or a voltage higher than the power supply voltage is supplied to the sub power line according to the logic level of the output signal to be supplied from the logic circuit. Therefore, even if the logic circuit of the output signal has an indefinite logic level, the subthreshold leakage current can be reduced by adopting the hierarchical power supply configuration.

  In addition, since the latch circuit is connected between the latch fixed power line that always receives the power supply voltage and the latch fixed ground line that always receives the ground voltage, the input signal to the latch circuit is cut off in the standby mode. A signal can be prevented from being input to the latch circuit.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

[Embodiment 1]
1 is a circuit diagram showing a configuration of a semiconductor circuit device according to a first embodiment of the present invention. Referring to FIG. 1, this semiconductor circuit device includes a main power supply line 10, a sub power supply line 12, a P channel MOS transistor 14, a main ground line 16, a sub ground line 18, and an N channel MOS transistor 20. , Buffer power lines 22, 24, buffer ground lines 26, 28, CMOS inverter circuits 30, 32, and power selectors 34, 36, 38, 40.

  Main power supply line 10 receives power supply voltage VCC. Transistor 14 is connected between main power supply line 10 and sub power supply line 12 and has a gate for receiving control signal / SCRC. Control signal / SCRC is at the L level during the operation mode, and is at the H level during the standby mode. Therefore, the transistor 14 is a switching element that is turned on in the operation mode and turned off in the standby mode. Transistor 20 is connected between main ground line 16 and sub-ground line 18 and has a gate for receiving control signal SCRC. Control signal SCRC is a signal complementary to control signal / SCRC, and is at the H level in the operation mode and at the L level in the standby mode. Therefore, the transistor 20 is a switching element that is turned on in the operation mode and turned off in the standby mode.

  Each inverter circuit 32 is connected between the buffer power supply line 22 and the buffer ground line 26, and outputs a first logic level signal in the standby mode. Each inverter circuit 30 is connected between the buffer power line 24 and the buffer ground line 28, and outputs a signal of a second logic level complementary to the first logic level in the standby mode.

The power supply selector 34 selects the main power supply line 10 or the sub power supply line 12 and connects it to the buffer power supply line 22. More specifically, the power supply selector 34 selects the main power supply line 10 in the operation mode and connects it to the buffer power supply line 22. When the inverter circuit 32 outputs an H level signal in the standby mode, the power supply selector 34 On the other hand, the buffer power supply line 22 is connected to the sub power supply line 12 when the inverter circuit 32 outputs an L level signal in the standby mode.

  The power selector 36 selects the main power line 10 or the sub power line 12 and connects it to the buffer power line 24. More specifically, the power supply selector 36 selects the sub power supply line 12 in the operation mode and connects it to the buffer power supply line 24. When the inverter circuit 30 outputs an H level signal in the standby mode, the power supply selector 36 On the other hand, the buffer power supply line 24 is connected to the sub power supply line 12 when the inverter circuit 30 outputs an L level signal in the standby mode.

  The power selector 38 selects the main ground line 16 or the sub ground line 18 and connects it to the buffer ground line 26. More specifically, the power supply selector 38 selects the main ground line 16 in the operation mode and connects it to the buffer ground line 26. When the inverter circuit 32 outputs an H level signal in the standby mode, the power source selector 38 connects the buffer ground line 26. On the other hand, the buffer ground line 26 is connected to the main ground line 16 when the inverter circuit 32 outputs an L level signal.

  The power selector 40 selects the main ground line 16 or the sub ground line 18 and connects it to the buffer ground line 28. More specifically, the power supply selector 40 selects the sub ground line 18 in the operation mode and connects it to the buffer ground line 28. When the inverter circuit 30 outputs an L level signal in the standby mode, the power source selector 40 connects the buffer ground line 28 to the buffer ground line 28. On the other hand, the buffer ground line 28 is connected to the sub ground line 18 when the inverter circuit 30 outputs an H level signal in the standby mode.

  The semiconductor circuit device further includes a CMOS inverter circuit 42 and a latch circuit 44. The inverter circuit 42 always outputs an H level signal in response to an L level input signal in the standby mode. Therefore, the inverter circuit 42 is connected between the main power supply line 10 and the sub ground line 18. On the other hand, the latch circuit 44 latches an H or L level signal during standby, and its output signal is not fixed to one. Therefore, the latch circuit 44 is connected between the main power supply line 10 and the main ground line 16.

  Here, each of inverter circuits 30, 32, 42 includes a P channel MOS transistor 46 and an N channel MOS transistor 48.

  FIG. 2 is a circuit diagram showing the configuration of power supply selectors 36 and 40. Referring to FIG. 2, power supply selector 36 includes a NOR circuit 361, an inverter circuit 362, and P channel MOS transistors 363 and 364. Power supply selector 40 includes a NAND circuit 401, an inverter circuit 402, and N channel MOS transistors 403 and 404.

NOR circuit 361 receives the output signal of latch circuit 44 (input signal of inverter circuit 30) and control signal SCRC. The output signal of the NOR circuit 361 is supplied to the gate of the transistor 363 through the inverter circuit 362 and directly to the gate of the transistor 364. Therefore, when the control signal SCRC is at the H level, the transistor 363 is turned off, the transistor 364 is turned on, and the buffer power supply line 24 is short-circuited to the sub power supply line 12. On the other hand, when control signal SCRC is at L level, transistors 363 and 364 are alternately turned on or off in response to the output signal of latch circuit 44. More specifically, when the output signal of the latch circuit 44 is at an H level, the transistor 363 is turned off,
Transistor 364 is turned on. On the other hand, when the output signal of the latch circuit 44 is at L level, the transistor 363 is turned on and the transistor 364 is turned off.

  NAND circuit 401 receives an output signal of latch circuit 44 (an input signal of inverter circuit 30) and control signal / SCRC. An output signal of the NAND circuit 401 is supplied to the gate of the transistor 403 through the inverter circuit 402 and directly to the gate of the transistor 404. Therefore, when the control signal / SCRC is at L level, the transistor 403 is turned off and the transistor 404 is turned on. On the other hand, when control signal / SCRC is at L level, transistors 403 and 404 are alternately turned on or off in response to the output signal of latch circuit 44. More specifically, when the output signal of the latch circuit 44 is at an H level, the transistor 403 is turned on and the transistor 404 is turned off. On the other hand, when the output signal of the latch circuit 44 is at L level, the transistor 403 is turned off and the transistor 404 is turned on.

  The power selector 34 is configured similarly to the power selector 36, and the power selector 38 is configured similarly to the power selector 40.

  Next, the operation of the semiconductor circuit device configured as described above will be described. This semiconductor circuit device has an operation mode and a standby mode. First, in the operation mode, control signal SCRC is at H level and control signal / SCRC is at L level. Therefore, transistors 14 and 20 are turned on, and sub power supply line 12 and sub ground line 18 are short-circuited to main power supply line 10 and main ground line 16, respectively.

  Further, the power source selector 34 short-circuits the buffer power source line 22 to the sub power source line 12, and the power source selector 36 short-circuits the buffer power source line 24 to the sub power source line 12. Further, the power supply selector 38 short-circuits the buffer ground line 26 to the sub-ground line 18, and the power supply selector 40 short-circuits the buffer ground line 28 to the sub-ground line 18.

  In the operation mode, as a result of the above, buffer power supply lines 22 and 24 receive power supply voltage VCC, and buffer ground lines 26 and 28 receive ground voltage VSS. Therefore, this semiconductor circuit device operates as usual.

  On the other hand, in standby mode, control signal SCRC is at L level and control signal / SCRC is at H level. Therefore, transistors 14 and 20 are turned off, and sub power supply line 12 and sub ground line 18 are electrically disconnected from main power supply line 10 and main ground line 16, respectively.

  Since the inverter circuit 42 always receives an L level input signal in the standby mode, it always supplies an H level output signal to the latch circuit 44 as a set signal SET. Here, since the source of the P-channel MOS transistor 46 in the inverter circuit 42 is connected to the main power supply line 10, the power supply voltage VCC is output as an H level output signal. On the other hand, since the source of N-channel MOS transistor 48 is connected to sub-ground line 18, the subthreshold leakage current flowing in transistor 48 is reduced.

  The latch circuit 44 always receives the H level set signal SET in the standby mode, but the reset signal RESET is not fixed to one. Therefore, the latch circuit 44 latches the H level signal or latches the L level signal in the standby mode.

Since the level of the output signal of the latch circuit 44 in the standby mode is not determined to be one, the logical level of each output signal of the inverter circuits 30 and 32 in the standby mode is also not determined to be one. More specifically, when the latch circuit 44 outputs an H level signal, each inverter circuit 30 outputs an L level signal, and each inverter circuit 32 outputs an H level signal. . On the other hand, when the latch circuit 44 outputs an L level signal, each inverter circuit 30 outputs an H level signal, and each inverter circuit 32 outputs an L level signal.

  When the latch circuit 44 outputs an H level signal, the transistor 363 in the power supply selector 36 is turned off and the transistor 364 is turned on, whereby the buffer power supply line 24 is short-circuited to the sub power supply line 12. . Further, the transistor 403 in the power supply selector 40 is turned on and the transistor 404 is turned off, whereby the buffer ground line 28 is short-circuited to the main ground line 16.

  Similarly, the buffer power supply line 22 is short-circuited to the main power supply line 10 by the power supply selector 34, and the buffer ground line 26 is short-circuited to the sub-ground line 18 by the power supply selector 38.

  As a result, all inverter circuits 30 that output an L level signal are connected between the sub power line 12 and the main ground line 16, and all inverter circuits 32 that output an H level signal are the main power supply. The line 10 and the sub ground line 18 are connected. Therefore, the subthreshold leakage current flowing in P channel MOS transistor 46 of inverter circuit 30 is reduced, and the subthreshold leakage current flowing in N channel MOS transistor 48 of inverter circuit 32 is reduced.

  On the other hand, when the latch circuit 44 outputs an L level signal, the transistor 363 in the power supply selector 36 is turned on and the transistor 364 is turned off, whereby the buffer power supply line 24 is short-circuited to the main power supply line 10. Is done. Further, the transistor 403 in the power supply selector 40 is turned off and the transistor 404 is turned on, whereby the buffer ground line 28 is short-circuited to the sub ground line 18. Similarly, the buffer power line 22 is short-circuited to the sub power line 12 by the power selector 34, and the buffer ground line 26 is short-circuited to the main ground line 16 by the power selector 38.

  As a result, all inverter circuits 30 that output H level signals are connected between the main power supply line 10 and the sub ground line 18, and all inverter circuits 32 that output L level signals are sub power supplies. It is connected between the line 12 and the main ground line 16. Therefore, the subthreshold leakage current flowing in N channel MOS transistor 48 of inverter circuit 30 is reduced, and the subthreshold leakage current flowing in P channel MOS transistor 46 of inverter circuit 32 is reduced.

  By the way, the latch circuit 44 is connected between the main power supply line 10 and the main ground line 16, but in order to reduce the subthreshold leakage current flowing in the latch circuit 44, the latch circuit 44 is as follows. It is desirable to be configured.

FIG. 3 is a circuit diagram showing a configuration of the latch circuit 44. Referring to FIG. 3, latch circuit 44 includes NAND circuits 441 and 442 connected to each other to form an RS flip-flop, and P channel MOS transistors connected in parallel to the power supply side of NAND circuit 441. 443 and 444, N channel MOS transistors 445 and 446 connected in parallel to the ground side of the NAND circuit 441, P channel MOS transistors 447 and 448 connected in parallel to the power supply side of the NAND circuit 442, NAND N channel MOS transistors 449 and 450 connected in parallel to the ground side of circuit 442, NAND circuit 451, inverter circuits 452 and 453, connected between the output node of NAND circuit 441 and main ground line 16 N channel MOS transistor It includes a Njisuta 454, and a P-channel MOS transistor 455 connected between the output node of the main power supply line 10 and the NAND circuit 442.

  Here, the threshold values of transistors 443 to 450 are preferably set larger than the threshold values of other transistors (for example, transistors in NAND circuits 441 and 442).

  NAND circuit 451 receives reset signal RESET and power-on reset signal / POR. An output signal of NAND circuit 451 is applied to NAND circuit 442 through inverter 452. The power-on reset signal / POR is directly applied to the gate of the transistor 455 and also to the gate of the transistor 454 via the inverter 453. Since this power-on reset signal / POR is at L level for a predetermined period from when the power is turned on, both transistors 454 and 455 are turned on. Therefore, the NAND circuit 441 outputs an L level signal, and the NAND circuit 442 outputs an H level signal. Thus, the latch circuit 44 is reset when the power is turned on.

  In the operation mode, control signal SCRC is at H level and control signal / SCRC is at L level, so that transistors 444, 446, 448, and 450 are all turned on. Since the power supply voltage VCC and the ground voltage VSS are supplied to the NAND circuits 441 and 442, the latch circuit 44 operates as usual.

  On the other hand, in standby mode, control signal SCRC is at L level and control signal / SCRC is at H level, so that transistors 444, 446, 448 and 450 are all turned off. When the latch circuit 44 outputs an H level signal, that is, when the NAND circuit 441 outputs an H level signal and the NAND circuit 442 outputs an L level signal, the transistors 443 and 449 are turned on. Transistors 445 and 447 are turned off. Therefore, the power supply voltage VCC is output as an H level output signal from the NAND circuit 441, but the subthreshold leakage current flowing in the NAND circuit 441 is reduced. The ground voltage VSS is output as an L level output signal from the NAND circuit 442, but the subthreshold leakage current flowing in the NAND circuit 442 is reduced.

  On the other hand, when the latch circuit 44 outputs an L level signal, that is, when the NAND circuit 441 outputs an L level signal and the NAND circuit 442 outputs an H level signal, the transistors 445 and 447 are Turns on and transistors 443 and 449 are turned off. Therefore, the ground voltage VSS is output as an L level output signal from the NAND circuit 441, but the subthreshold leakage current flowing in the NAND circuit 441 is reduced. The power supply voltage VCC is output from the NAND circuit 442 as an H level output signal, but the subthreshold leakage current flowing in the NAND circuit 442 is reduced.

  As described above, according to the first embodiment, buffer power supply line 22 is connected to main power supply line 10 or sub power supply line 12 and buffer power supply line 24 is connected to sub power supply line 12 or according to the output signal of latch circuit 44. Since the buffer ground line 26 is connected to the sub ground line 18 or the main ground line 16 and the buffer ground line 28 is connected to the main ground line 16 or the sub ground line 18 while being connected to the main power supply line 10, the standby mode Even in the inverter circuits 30 and 32 in which the logic level of the output signal at that time is not fixed to one, the subthreshold leakage current can be reduced by adopting the hierarchical power supply configuration.

Further, the transistors 443, 445, 445 are output in accordance with the output signals of the NAND circuits 441, 442.
Since 447 and 449 are turned on or off, the subthreshold leakage current flowing in the latch circuit 44 can also be reduced.

[Embodiment 2]
4 is a circuit diagram showing a configuration of a semiconductor circuit device according to a second embodiment of the present invention. Referring to FIG. 4, this semiconductor circuit device includes an external power supply line 50, a negative power supply line 52, a voltage down converter (VDC) 54, and a charge pump circuit 56 in addition to the configuration shown in FIG. . The voltage down converter 54 steps down the external power supply voltage EVCC, generates an internal power supply voltage IVCC lower than the external power supply voltage EVCC, and supplies it to the main power supply line 10. The charge pump circuit 56 generates a negative voltage VBB lower than the ground voltage VSS and supplies it to the negative power supply line 52.

  This semiconductor circuit device includes power selectors 58 and 60 in place of the power selectors 34, 36, 38 and 40 of FIG. When the inverter circuit 32 outputs an H level signal in the standby mode, the power selector 58 connects the sub power line 12 to the external power line 50 to connect the external power voltage EVCC higher than the internal power voltage IVCC to the sub power line. 12 is supplied. When the inverter circuit 30 outputs an L level signal, the power selector 60 connects the sub ground line 18 to the negative power line 52 to supply the sub ground line 18 with a negative voltage VBB lower than the ground voltage VSS.

  This semiconductor circuit device does not include the buffer power supply lines 22 and 24 and the buffer ground lines 26 and 28 as shown in FIG. Therefore, the inverter circuit 30 that outputs a signal of the first logic level in the standby mode is connected between the main power supply line 10 and the sub ground line 18, and a second complementary to the first logic level in the standby mode. The inverter circuit 32 that outputs a logic level signal is connected between the sub power line 12 and the main ground line 16. The inverter circuits 30 and 32 are not sure what logic level signals are output in the standby mode, but are connected between the power supply lines 10 and 12 and the ground lines 16 and 18 for the time being. .

  FIG. 5 is a circuit diagram showing the configuration of power supply selectors 58 and 60. Referring to FIG. 5, power supply selector 58 includes a NOR circuit 581, an inverter circuit 582, and a P channel MOS transistor 583. NOR circuit 581 receives an output signal of latch circuit 44 (input signal of inverter circuit 30) and control signal SCRC. The output signal of the NOR circuit 581 is supplied to the gate of the transistor 583 through the inverter circuit 582. Power supply selector 60 includes an AND circuit 601 and an N-channel MOS transistor 602. AND circuit 601 receives an output signal of latch circuit 44 (input signal of inverter circuit 30) and control signal / SCRC. The output signal of the AND circuit 601 is directly applied to the gate of the transistor 602.

  Therefore, when control signal SCRC is at H level and control signal / SCRC is at L level, transistors 583 and 602 are both turned off. On the other hand, when control signal SCRC is at L level and control signal / SCRC is at H level, transistors 583 and 602 are alternately turned on or off in response to the output signal of latch circuit 44. More specifically, when the output signal of the latch circuit 4 is at an H level, the transistor 583 is turned off and the transistor 602 is turned on. Therefore, the sub ground line 18 is short-circuited to the negative power supply line 52. On the other hand, when the output signal of the latch circuit 44 is at L level, the transistor 583 is turned on and the transistor 602 is turned off. Therefore, the sub power supply line 12 is short-circuited to the external power supply line 50.

Next, the operation of the semiconductor circuit device configured as described above will be described. First, in operation mode, control signal SCRC attains H level and control signal / SCRC attains L level, so that each sub power supply line 12 and each sub ground line 18 are short-circuited to main power supply line 10 and main ground line 16, respectively. The Since transistors 583 and 602 are turned off at this time, sub power supply line 12 and sub ground line 18 are not connected to external power supply line 50 and negative power supply line 52, respectively. As a result, this semiconductor circuit device operates normally.

  On the other hand, in the standby mode, control signal SCRC attains L level and control signal / SCRC attains H level, so that each sub power supply line 12 and each sub ground line 18 are electrically connected from main power supply line 10 and main ground line 16, respectively. Separated. However, even if the transistor 14 is turned off, the sub power supply line 12 is slightly charged by the subthreshold leakage current of the transistor 14. Similarly, even when the transistor 20 is turned off, the sub-ground line 16 is slightly charged by the sub-threshold leakage current of the transistor 20.

  When latch circuit 44 outputs an H level signal in the standby mode, power supply selector 60 short-circuits sub-ground line 18 to negative power supply line 52. At this time, N channel MOS transistor 48 of inverter circuit 30 is turned on, so that negative voltage VBB is applied to the gates of transistors 46 and 48 of inverter circuit 32. Since the source voltage of the N channel MOS transistor 48 of the inverter circuit 32 is the ground voltage VSS, the subthreshold leakage current flowing in the transistor 48 is reduced.

  On the other hand, when the output signal of latch circuit 44 is at the L level, power supply selector 58 short-circuits sub power supply line 12 to external power supply line 50. At this time, P channel MOS transistor 46 of inverter circuit 30 is turned on, so that internal power supply voltage IVCC is applied to the gates of transistors 46 and 48 of inverter circuit 32. At this time, the source voltage of N channel MOS transistor 46 of inverter circuit 32 becomes external power supply voltage EVCC higher than internal power supply voltage IVCC, so that the subthreshold leakage current of transistor 46 is reduced.

  As described above, according to the second embodiment, even when the inverter circuits 30 and 32 are not sure what kind of logic level signal is output in the standby mode, grounding is performed when the output signal of the latch circuit 44 is at H level. Negative voltage VBB lower than voltage VSS is supplied to sub-ground line 18, while external power supply voltage EVCC higher than internal power supply voltage IVCC is supplied to sub power supply line 12 when the output signal of latch circuit 44 is at L level. Therefore, the subthreshold leakage current flowing in the inverter circuits 30 and 32 can be reduced.

[Embodiment 3]
6 is a circuit diagram showing a configuration of a semiconductor circuit device according to a third embodiment of the present invention. Referring to FIG. 6, this semiconductor circuit device includes a P channel MOS transistor 62 connected between a node receiving power supply voltage VCC and main power supply line 10, unlike the configuration of FIGS. The transistor 62 is turned on in response to the L level control signal / SCRC in the operation mode, and turned off in response to the H level control signal / SCRC in the standby mode.

  The semiconductor circuit device further includes a NAND circuit 63. This semiconductor circuit device does not include the sub power supply line 12 and the sub ground line 18 as shown in FIGS. Therefore, each of the logic circuits such as the inverter circuits 30, 32, and 42 and the NAND circuit 63 is connected between the main power supply line 10 and the main ground line 16.

The semiconductor circuit device further includes a latch circuit 68 in place of the latch circuit 44 shown in FIGS. The semiconductor circuit device further includes a latch fixed power line 64 that constantly receives the power supply voltage VCC, a latch fixed ground line 66 that always receives the ground voltage VSS, a latch drive power line 70, a latch drive ground line 72, and a latch drive power supply. And a drive interval 74 connected to the line 70.

  Each of the latch circuits 68 is connected not between the main power supply line 10 and the main ground line 16 but between the latch fixed power supply line 64 and the latch fixed ground line 66. Therefore, the latch circuit 68 can latch the signal even in the standby mode.

  The drive circuit 74 supplies the power supply voltage VCC to the latch drive power supply line 70 in the operation mode, and supplies the ground voltage VSS to the latch drive power supply line 70 in the standby mode. In this embodiment, the latch drive ground line 72 is always supplied with the ground voltage VSS.

  FIG. 7 is a circuit diagram showing the configuration of the latch circuit 68 and the drive circuit 74. Referring to FIG. 7, latch circuit 68 includes a latch circuit 76 composed of two CMOS inverter circuits connected to each other, and a CMOS inverter circuit 78. Latch circuit 76 includes P channel MOS transistors 761 and 762 and N channel MOS transistors 763 and 764. Here, transistors 761 and 763 form one CMOS inverter circuit, and transistors 762 and 764 form another CMOS inverter circuit. The latch circuit 76 is connected between the latch fixed power line 64 and the latch fixed ground line 66.

  Inverter circuit 78 includes a P channel MOS transistor 781 and an N channel MOS transistor 782. The inverter circuit 78 is connected between the latch drive power supply line 70 and the latch drive ground line 72 and is inserted into a signal input path to the latch circuit 76. Therefore, the latch circuit 68, more specifically the inverter circuit 78, is driven by a potential difference between the latch drive power supply line 70 and the latch drive ground line 72. The output signal of the NAND circuit 63 is input to the latch circuit 76 via the inverter circuit 78.

  The drive circuit 74 supplies the power supply voltage VCC to the latch drive power supply line 70 in the operation mode, and supplies the ground voltage VSS to the latch drive power supply line 70 in the standby mode. Drive circuit 74 includes a P channel MOS transistor 741 and an N channel MOS transistor 742. When the control signal / SCRC becomes L level in the operation mode, the transistor 741 is turned on, and the power supply voltage VCC is supplied to the latch drive power supply line 70. On the other hand, when the control signal / SCRC becomes H level in the standby mode, the transistor 742 is turned on, and the ground voltage VSS is supplied to the latch drive power supply line 70.

  Next, the operation of the semiconductor circuit device configured as described above will be described. First, in the operation mode, since the control signal / SCRC is at the L level, the transistor 62 is turned on and the power supply voltage VCC is supplied to the main power supply line 10. At the same time, the transistor 741 is turned on, and the power supply voltage VCC is supplied to the latch drive power supply line 70. Since the power supply voltage VCC is always supplied to the latch fixed power supply line 64 and the ground voltage VSS is always supplied to the main ground line 16, the latch fixed ground line 66, and the latch drive ground line 72, this semiconductor circuit device is Works as normal.

  On the other hand, in the standby mode, control signal / SCRC is at H level, so that transistor 62 is turned off. Therefore, inverter circuits 30, 32 and 42 and NAND circuit 63 do not operate, and their subthreshold leakage currents are reduced.

However, since the power supply voltage VCC is always supplied to the latch fixed power supply line 64, the latch circuit 76 operates. Therefore, the latch circuit 76 can continue to latch the logic level signal latched immediately before the semiconductor circuit device enters the standby mode even during the standby mode. Therefore, the inverter circuits 30, 32 and 42 and the NAND circuit 63 are completely powered off in the standby mode. However, when this semiconductor circuit device returns to the operation mode, the state immediately before the standby mode can be restored. .

  In the standby mode, the NAND circuit 63 is powered off as described above, and therefore, a random logic level signal may be input to the latch circuit 68. However, since the ground voltage VSS is supplied from the drive circuit 74 to the latch drive power supply line 70 in the standby mode, both the transistors 781 and 782 are turned off. Therefore, in the standby mode, the input to the latch circuit 76 is cut off, and a random signal is not latched by the latch circuit 76.

  As described above, according to the third embodiment, since the signal input to the latch circuit 76 is cut off in the standby mode, the latch circuit 76 can be operated even when the inverter circuits 30, 32 and 42 and the NAND circuit 63 are turned off. The logic level signal latched immediately before the semiconductor circuit device enters the standby mode can be reliably latched even in the standby mode.

  In the third embodiment, the drive circuit 74 supplies the ground voltage VSS to the latch drive power supply line 70 in the standby mode. Instead, the drive circuit 74 supplies a voltage lower than the ground voltage VSS to the latch drive power supply line 70. A circuit can also be provided. The ground voltage VSS is always supplied to the latch drive ground line 72. However, the ground voltage VSS is supplied to the latch drive ground line 72 in the operation mode, and a voltage higher than the ground voltage VSS in the standby mode (for example, the power supply voltage). A drive circuit for supplying VCC) to the latch drive ground line 72 may be provided. With such a driver circuit, the transistor 782 is completely turned off in the standby mode.

  In the third embodiment, the inverter circuit 78 is provided to cut off the signal input to the latch circuit 76 in the standby mode. Instead of this, the number of transistors is increased, but a three-state buffer is provided. You can also.

[Embodiment 4]
Instead of the latch circuit shown in FIG. 7, the latch circuit shown in FIG. 8 can be used. The semiconductor circuit device according to the fourth embodiment includes N channel MOS transistors 80 and 82 in addition to latch circuit 76. Transistor 80 is connected between one input node of latch circuit 76 and latch drive ground line 72, and has a gate for receiving signal AA. Transistor 82 is connected between the other input node of latch circuit 76 and latch drive ground line 72, and has a gate for receiving signal / AA complementary to signal AA. Signals AA and / AA are supplied from logic circuit 84 connected between main power supply line 10 and main ground line 16.

  The semiconductor circuit device further includes a drive circuit 86 for driving the latch drive ground line 72, a drive circuit 88 for driving the latch fixed power line 64, a drive circuit 90 for driving the latch fixed ground line 66, and the main power line 10. And a drive circuit 92 for driving.

  Drive circuit 86 includes a P-channel MOS transistor 861 and an N-channel MOS transistor 862, supplies ground voltage VSS to latch drive ground line 72 in the operation mode in which control signal SCRC is at H level, and control signal SCRC is at L level. In the standby mode, a voltage higher than the ground voltage VSS (here, the power supply voltage VCC) is supplied to the latch drive ground line 72.

Drive circuit 88 includes a boosted potential generation circuit 881, level conversion circuits 882 and 883, and P channel MOS transistors 884 and 885. Boosted potential generation circuit 881 generates a voltage VPP higher than power supply voltage VCC. Level conversion circuit 882 converts a logic level that changes between power supply voltage VCC and ground voltage VSS into a logic level that changes between voltage VPP and power supply voltage VCC. Similarly, level conversion circuit 883 converts the logic level of control signal / SCRC. Therefore, drive circuit 88 supplies power supply voltage VCC to latch fixed power supply line 64 in the operation mode in which control signal SCRC is at H level and control signal / SCRC is at L level, and control signal SCRC is at L level. In the standby mode in which the control signal / SCRC is at the H level, a voltage VPP higher than the power supply voltage VCC is supplied to the latch fixed power supply line 64.

  Drive circuit 90 includes an intermediate potential generation circuit 901, a P channel MOS transistor 902, and an N channel MOS transistor 903. Intermediate potential generation circuit 901 generates intermediate voltage VCC / 2. Therefore, drive circuit 90 supplies ground voltage VSS to latch fixed ground line 66 in the operation mode in which control signal SCRC is at the H level, and voltage higher than ground voltage VSS in the standby mode in which control signal SCRC is at the L level. (Here, intermediate voltage VCC / 2) is supplied to latch fixed ground line 66.

  Drive circuit 92 includes a P-channel MOS transistor 921 and an N-channel MOS transistor 922, supplies power supply voltage VCC to main power supply line 10 in an operation mode in which control signal / SCRC is at L level, and control signal / SCRC is at H level. The ground voltage VSS is supplied to the main power supply line 10 in the standby mode.

  Next, the operation of the semiconductor circuit device configured as described above will be described with reference to the timing chart of FIG.

  First, in the operation mode, the voltage M-VCC of the main power supply line 10 becomes the power supply voltage VCC. The voltage F-VCC of the latch fixed power supply line 64 also becomes the power supply voltage VCC. The voltage F-VSS of the latch fixed ground line 66 becomes the ground voltage VSS. The voltage D-VSS of the latch drive ground line 72 also becomes the ground voltage VSS. The voltage M-VSS of the main ground line 16 is always the ground voltage VSS.

  Therefore, the latch circuit 76 operates normally. More specifically, when an H level signal AA and an L level signal / AA are supplied, the transistor 80 is turned on and the transistor 82 is turned off. Therefore, the ground voltage VSS from the latch drive ground line 72 is input to the latch circuit 76 as the L level signal / BB. The latch circuit 76 latches this signal and sets the signal BB to the H level. On the other hand, when an L level signal AA and an H level signal / AA are applied, the transistor 80 is turned off and the transistor 82 is turned on. Therefore, the ground voltage VSS is input from the latch drive ground line 72 to the latch circuit 76 as the L level signal BB. Therefore, latch circuit 76 latches this signal and sets signal / BB to H level.

  On the other hand, in the standby mode, the voltage M-VCC of the main power supply line 10 becomes the ground voltage VSS. The voltage F-VCC of the latch fixed power supply line 64 becomes a voltage VPP higher than the power supply voltage VCC. The voltage F-VSS of the latch fixed ground line 66 becomes an intermediate voltage VCC / 2 higher than the ground voltage VSS. The voltage D-VSS of the latch drive ground line 72 becomes the power supply voltage VCC.

  Therefore, as shown in FIG. 9, when signal BB goes to L level and signal / BB goes to H level, the drain voltage of transistor 82 becomes intermediate voltage VCC / 2 and the source voltage becomes power supply voltage VCC. Therefore, a relatively negative bias is applied to the gate of the transistor 82, and the leakage current can be reduced as compared with the case of applying the zero bias.

  On the other hand, when the signal BB becomes H level and the signal / BB becomes L level, the drain voltage of the transistor 80 becomes the intermediate voltage VCC / 2 and the source voltage becomes the power supply voltage VCC. Also, a relatively negative bias is applied, and the leakage current can be reduced as compared with the case of applying the zero bias.

  As described above, in the standby mode, the transistors 80 and 82 block signal input to the latch circuit 76, so that no random signal is input to the latch circuit 76.

  Further, since a potential difference is applied to the latch circuit 76 between the voltage VPP and the intermediate voltage VCC / 2 in the standby mode, the latch circuit 76 ensures that the signal immediately before the semiconductor circuit device enters the standby mode also in the standby mode. You can continue to latch.

  In this circuit, the threshold values of the transistors 80 and 82 are preferably low, and the threshold values of the transistors 761 to 764 are preferably set high. A voltage is constantly applied to the latch circuit 76 to hold a signal, and a leak current is generated. The reason for setting the threshold in this way is to reduce this leakage current. However, for N channel MOS transistors 763 and 764, when voltage F-VSS rises in the standby mode, a substrate bias is applied, the threshold value rises, and the leakage current is reduced. It is also possible to adopt a transistor with a low value. Similarly, for P channel MOS transistors 761 and 762, a transistor having a low threshold can be adopted if the leakage current is reduced by driving the well voltage to a voltage higher than voltage VPP in the standby mode. is there. As a result, the threshold values of all the P-channel MOS transistors and N-channel MOS transistors can be unified, the transistor channel profile setting process for setting the threshold values can be reduced, and the process can be simplified. It becomes possible.

  As described above, according to the fourth embodiment, the transistors 80 and 82 are completely turned off in the standby mode, so that a random signal is not input to the latch circuit 76. In addition, since the predetermined voltage is supplied to the latch circuit 76 in the standby mode, the latch circuit 76 can reliably latch the signal.

  In the fourth embodiment, the voltage D-VSS of the latch drive ground line 72 is set to the power supply voltage VCC in the standby mode, but this voltage only needs to be higher than the ground voltage VSS. Further, although the voltage F-VSS is raised to the intermediate voltage VCC / 2, the voltage may be raised to any voltage as long as the transistors 80 and 82 are turned off and the leakage current can be reduced. Here, in order to maintain the latch signal in the standby mode, the latch voltage is secured and the voltage F-VCC is raised to the voltage VPP higher than the power supply voltage VCC. However, if the latch signal can be maintained, There is no need to change the voltage F-VCC.

[Embodiment 5]
In place of the drive circuits 86 and 90 shown in FIG. 5, the drive circuits 94 and 96 shown in FIG. 10 can be provided.

Drive circuit 94 includes a P-channel MOS transistor 941 and an N-channel MOS transistor 942. An enable signal EN is supplied to the gates of the transistors 941 and 942. As this enable signal EN, for example, a signal for activating a sense amplifier in an SDRAM (Synchronous Dynamic Random Access Memory) described later can be used. Therefore, this drive circuit 94 temporarily supplies ground voltage VSS to latch drive ground line 72 during input of signals AA and / AA in the operation mode, as shown by voltage D-VSS in FIG. At other times, the power supply voltage VCC is supplied to the latch drive ground line 72.

  Drive circuit 96 includes a P-channel MOS transistor 961, an AND circuit 962, an N-channel MOS transistor 963, an intermediate potential generation circuit 901, and a P-channel MOS transistor 964. An enable signal / EN is supplied to the gate of the transistor 961. AND circuit 962 receives enable signal / EN and control signal SCRC, and provides the output signal to the gate of transistor 963. A control signal SCRC is supplied to the gate of the transistor 964. Therefore, as shown by voltage F-VSS in FIG. 11, drive circuit 96 latches power supply voltage VCC while signal AA and / AA are being input in the operation mode in which control signal SCRC is at the H level. In other cases, the ground voltage VSS is supplied to the latch fixed ground line 66. In the standby mode in which control signal SCRC is at L level, drive circuit 96 supplies a voltage higher than the ground voltage (in this case, intermediate voltage VCC / 2) to latch fixed ground line 66.

  Next, the operation of the semiconductor circuit device configured as described above will be described with reference to the timing chart of FIG.

  Since the operation in the standby mode is the same as that of the fourth embodiment shown in FIGS. 8 and 9, only the operation in the operation mode will be described here.

  In the fifth embodiment, as shown in FIG. 11, the voltage of the latch drive ground line 72 is basically the power supply voltage VCC even in the operation mode. Therefore, the transistors 80 and 82 are turned off, and a random signal is not input to the latch circuit 76. However, this voltage D-VSS temporarily becomes ground voltage VSS when signals AA and / AA are applied. When voltage D-VSS of latch drive ground line 72 becomes ground voltage VSS, signals BB and / BB are input to latch circuit 76 in response to signals AA and / AA.

  Since the voltage D-VSS of the latch drive ground line 72 becomes the ground voltage VSS and the voltage F-VSS of the latch fixed ground line 66 becomes the power supply voltage VCC, the signals BB and / BB are initially at the power supply voltage VCC level. is there. However, since the voltage D-VSS becomes the power supply voltage VCC and the voltage F-VSS becomes the ground voltage VSS, the potential difference generated between the two input nodes is amplified according to the signals BB and / BB. When signal AA is at H level and signal / AA is at L level, the level of signal BB maintains power supply voltage VCC, and the level of signal / BB becomes ground voltage VSS. On the other hand, when the signal AA is at the L level and the signal / AA is at the H level, the level of the signal BB becomes the ground voltage VSS, and the level of the signal / BB maintains the power supply voltage VCC.

  As described above, according to the fifth embodiment, the voltage D-VSS of the latch drive ground line 72 and the voltage F-VSS of the latch fixed ground line 66 are synchronized with the inputs of the signals AA and / AA and the power supply voltage VCC and Since the voltage swings between the ground voltages VSS, the latch circuit 76 exhibits an amplification function. As a result, the latch circuit 76 can reliably latch a signal immediately before the semiconductor circuit device enters the standby mode.

  As the power supply voltage VCC in the first to fifth embodiments, an external power supply voltage can be used unless otherwise specified, and an internal power supply voltage lower than the external power supply voltage can be used. Similarly, an external ground voltage can be used as the ground voltage VSS unless otherwise specified, and an internal ground voltage higher than the external ground voltage can also be used.

In the fifth embodiment, the voltages F-VSS and G-VSS operate in a complementary manner in the operation mode. However, such a complementary operation is an example, and is changed according to a required operation specification. Is possible. For example, if it is desired to increase the margin of the amplification operation of the input signals AA, / AA by the transistors 80 and 82, the ground voltage VSS is maintained for a while after the voltage F-VSS changes to the ground voltage VSS. Also good. What is important is that the latch circuit 76 that amplifies the input signals AA and / AA operates dynamically.

[Embodiment 6]
The latch circuits in the fourth and fifth embodiments shown in FIGS. 8 and 10 can be used for, for example, a row predecoder of an SDRAM. More specifically, as shown in FIGS. 12 and 13, a latch circuit 98 that latches row-related address signals ACT, PC, APC, EQ, RXQ, SE is configured as shown in FIG. The same applies to the other latch circuits 234 and 244. In latch circuit 98, as shown in FIG. 14, P-channel MOS transistor 981 is connected to the gate of transistor 80, and P-channel MOS transistor 982 is connected to the gate of transistor 82. One-shot pulse signal SHOT generated when signal ACT is activated by one-shot pulse generation circuit 207 is applied to the gate of transistor 981. The gate of the transistor 982 is supplied with a signal APC generated as a one-shot pulse at reset. Therefore, the gate voltages of the transistors 80 and 82 become the ground voltage VSS except when the signals EQ and RST are input.

  Further, a latch circuit 100 (shown in FIG. 12) that latches row-related address signals is configured as shown in FIG. Also in this latch circuit 100, a P channel MOS transistor 1001 is connected to the gate of the transistor 80, and a P channel MOS transistor 1002 is connected to the gate of the transistor 82. Bank hit signal BH generated by one-shot pulse generation circuit 204 is applied to the gates of transistors 1001 and 1002. Therefore, the gate voltages of the transistors 80 and 82 become the ground voltage VSS except when the row address signals RA and / RA are input.

  As described above, according to the sixth embodiment, since the latch circuit 98 is configured as shown in FIG. 14, even if the power is turned off after the latch circuit 98 latches the command signal, the latch circuit 98 is latched. Continues to latch the command signal, and when the power is turned on again, the latch circuit 98 can output the latched command signal.

  Since the latch circuit 100 is configured as shown in FIG. 15, the latch circuit 100 continues to latch the address signal even if the power is turned off after latching the address signal. Therefore, when the power is turned on again, the latch circuit 100 can output the latched address signal.

[Details of SDRAM and Row Predecoder]
The details of the SDRAM and the row predecoder using the latch circuit in the fourth and fifth embodiments will be described below for reference.

  FIG. 20 is a schematic block diagram showing the overall configuration of this SDRAM. Referring to FIG. 20, SDRAM 1000 receives external control signals / RAS, / CAS, / W, / CS, etc. given through external control signal input terminal group 106, decodes them, and receives internal control signals. A control circuit 108 is generated, command data buses 53a and 53b for transmitting an internal control signal output from the control circuit 108, and a memory cell array 110 in which memory cells are arranged in a matrix.

  As shown in FIG. 20, the memory cell array 110 is divided into a total of 16 memory cell blocks 100a to 100b. For example, when the storage capacity of SDRAM 1000 is 1 Gbit, each memory cell block has a capacity of 64 Mbits. Each block is configured to be able to operate independently as a bank.

  The SDRAM 1000 further includes an external clock signal Ext. CLK is received and controlled by the control circuit 108 to start the synchronous operation, and the internal clock signal int. An internal synchronization signal generation circuit 114 that outputs CLK is included.

  The internal synchronization signal generation circuit 114 is connected to the external clock signal Ext. By a delayed loop circuit (hereinafter referred to as a DLL circuit), for example. The internal clock signal int. Generate CLK.

  External address signals A0 to Ai (i: natural number) applied through address signal input terminal group 116 are controlled by internal clock signal int. The data is taken into the SDRAM 1000 in synchronization with CLK.

  Of the external address signals A0 to Ai, data having a predetermined number of bits is applied to the bank decoder 22 via the address bus 51a. Decoded bank addresses B0 to B7 are transmitted from bank decoder 118 to each bank via address buses 51b and 51c.

  On the other hand, other external address signals applied to address signal input terminal group 116 are transmitted to address driver 120 via address buses 50a and 50b. The address signal is further transmitted from the address driver 120 to each bank (memory cell block) via the address bus 50c.

  The SDRAM 1000 is further provided for each pair of memory cell blocks. Under control of the control circuit 108, the SDRAM 1000 latches and predecodes the row address transmitted by the address bus 50c, and the row predecoder 300 Are provided for each memory cell block and are transmitted by the address bus 50c under the control of the control circuit 108. The row decoder 122 selects the corresponding row (word line) of the memory cell block selected based on A column predecoder 400 that latches and predecodes the column address, a column predecoder line 124 that transmits an output from the column predecoder 400, and a memory that is selected based on an output from the column predecoder line 124 Corresponding column of cell blocks (bit line pair Selecting and a column decoder 126.

  Further, SDRAM 1000 is an area along the long side direction at the center of the chip, and data input terminals DQ0 to DQ15 arranged outside the area where external control signal input terminal group 106 and address signal input terminal group 116 are provided. Data bus 128 for transmitting data between DQ16-DQ31, input / output buffer circuits 14a-14f provided corresponding to data input / output terminals DQ0-DQ31, respectively, and memory cell blocks corresponding to the input / output buffers. And a read / write amplifier 130 provided corresponding to each of memory cell blocks 100a to 100b and transferring data between data bus 128 and a selected memory cell column.

  Signal / RAS applied to external control signal input terminal group 106 is a row address strobe signal that starts internal operation of SDRAM 1000 and determines the active period of internal operation. In response to the activation of signal / RAS, a circuit related to the operation of selecting a row of memory cell array 110 such as row decoder 122 is activated.

  Signal / CAS applied to external control signal input terminal group 106 is a column address strobe signal, and activates a circuit for selecting a column in memory cell array 110.

  Signal / CAS applied to external control signal input terminal group 106 is a chip select signal indicating that SDRAM 1000 is selected, and signal / W is a signal for instructing a write operation of SDRAM 1000.

  The signal / CS, the signal / RAS, the signal / CAS and the signal / W are fetched by the internal clock signal int. This is performed in synchronization with CLK.

  In addition, the operation of taking in the address signal applied to the address signal input terminal group 116 and the exchange of data through the data input / output terminals DQ0 to DQ31 are also performed. This is performed in synchronization with CLK.

  FIG. 12 is a schematic block diagram showing the configuration of the row predecoder 300 in the SDRAM.

  The command bus 53b includes a signal Row for instructing activation of row-related circuit operations, a signal Clm for instructing activation of column-related circuit operations, and a signal ACT for instructing activation of circuit operations of internal circuits. The signal PC instructing the bank reset (precharge), the signal APC instructing the precharge of all banks, the equalization of the bit lines, etc. are released, and the work of separating the unused bit lines from the sense amplifier is performed. A signal EQ for instructing this, a signal RXT for instructing activation of the word line, a signal SE for instructing activation of the sense amplifier, and the like are transmitted.

  Bank address bus 51c transmits bank address signals B0-B3 decoded by the bank decoder. Address bus 50c transmits a row address signal from an address driver.

  Among the bank address signals, for example, when the bit data B3 is activated and the signal Row is activated, an active state signal is output from the AND circuit 203, and the one-shot pulse generation circuit 204 is activated accordingly. Bank hit BH is output.

  In response to this, the driver circuit 206 is activated, the level of the signal ACT is taken in, and the level is held in the level holding circuit 208. On the other hand, in response to the output from the driver circuit 206, the one-shot pulse generation circuit 207 outputs a one-shot pulse signal SHOT.

Similarly, driver circuit 210 is activated in response to bank hit signal BH from one-shot pulse generation circuit 204, and level holding circuit 212 holds the level in response to the level of signal PC. On the other hand, in response to the output from the driver circuit 210, the one-shot pulse generation circuit 214 outputs a reset signal RST to the level holding circuit 208. Inverter 220 is activated in response to an output signal from level holding circuit 208, and receives and outputs signal EQ. On the other hand, inverter 222 is activated in response to signal APC, receives signal RST from one-shot pulse generation circuit 214, and outputs its inverted signal. The latch circuit 98 is set according to the output from the inverter 220 and is reset according to the output from the inverter 222. The driver circuit 226 activated by the control signal SCRC receives and outputs the output of the latch circuit 98, and the level holding circuit 228 holds the output level of the driver circuit 226. The output level of the level holding circuit 228 is the signal l. EQ
Is given to the corresponding memory cell block.

  Similarly, the latch circuit 234 is set by the output of the inverter 230 and reset by the output of the inverter 232.

  Driver circuit 236 receives the output of latch circuit 234 and is activated by control signal SCRC. The output level of the driver circuit 236 is held by the level holding circuit 238, and the output level of the level holding circuit 238 is the signal l. It is output to the corresponding memory cell block as RXT.

  The latch circuit 244 is set by the output of the inverter 240 and is reset according to the output of the inverter 242. Driver circuit 246 receives the output of latch circuit 244 and is activated by control signal SCRC. The output level of the driver circuit 246 is held by the level holding circuit 244. The output level of the level holding circuit 244 is the signal l. It is given to the corresponding memory cell block as SE.

  On the other hand, latch circuit 100 is reset in response to activation of control signal SCRC, activated in response to a bank hit signal from one-shot pulse generation circuit 204, and receives a row address signal transmitted via address bus 50c. Hold. The output from the latch circuit 100 is transmitted to a redundant address decoder (not shown) and is given to the predecoder 252, and the predecoded result is given to the driver circuit 254.

  The driver circuit 254 is activated by the output signal of the driver control circuit 302. Driver control circuit 302 is controlled by an output signal of NAND circuit 303 receiving signals APC and RST, an output signal of level holding circuit 208, and control signal SCRC. When the driver control circuit 302 is once activated and then deactivated, the driver control circuit 302 maintains the driver circuit 254 in the inactive state even if the control signal SCRC is activated again during the active period of the signal ACT. Circuit. That is, by controlling the driver circuit 254 with such a driver control circuit 302, an operation is performed in which the control signal SCRC is activated again after the row address is once taken into the level holding circuit 256. In such a case, the driver 254 is activated to prevent the predecoder address signal held in the level holding circuit 256 from being reset. That is, once the driver circuit 254 is activated and then inactivated, the latch circuit 100 and the predecoder 252 which are circuit systems for taking in the address signal are reset, so that the driver circuit 254 is activated again. In this state, the predecode address signal held in the level holding circuit 256 is prevented from being reset.

  The output from the driver circuit 254 is held by the level holding circuit 256, and the level holding circuit 256 is output to the corresponding row predecoder line.

  In the row predecoder 300 shown in FIG. 12, the level holding circuits 208, 212, 228, 238 and 248 and the level holding circuit 256 and the area including the corresponding memory cell block are areas not controlled by the control signal. This is a non-hierarchical power supply region that always operates using the power supply voltage VCC and the ground voltage VSS as the power supply voltage in both the active state and the standby state.

On the other hand, the other regions of row predecoder 300 are controlled by the control signal and operate while receiving power supply voltage VCC and ground voltage VSS while control signal SCRC is active. During the period in which SCRC is at the L level, the hierarchical power supply region operates using a potential lower than power supply voltage VCC and a voltage higher than ground voltage VSS as power supply voltages.

  The circuit included in the hierarchical power supply region can reduce the subthreshold leakage current of the MOS transistor during normal standby when the bank is not activated.

  In contrast, the circuits included in the non-hierarchical power supply area, that is, the level holding circuits 208, 212, 228, 238, 248, and 256 change their levels depending on the operating state even during the standby operation. This circuit does not have a hierarchical power supply configuration.

  In other words, row predecoder 300 shown in FIG. 12 is sufficient for taking in data from the outside in order to perform operations such as reading data from the memory cells even during the active period of the chip. After this period is over, the circuit other than the necessary portion is configured to have a hierarchical power supply configuration, thereby reducing the subthreshold current.

  In this way, for the circuits included in the hierarchical power supply region, driver circuits 226, 236, and 246 that operate according to the output levels of latch circuits 98, 234, and 244 operate only for the first period during which the command level is transmitted. . After the command level is held in the level holding circuits 228 to 248, the driver circuits 226 to 246 have a tri-state configuration, so that their output levels are in a floating state. That is, the circuit system before this driver circuits 226 to 246 is an operation command output to the corresponding memory cell block (bank) even when the subthreshold current is reduced by the hierarchical power supply configuration. Are held by level holding circuits 228 to 248.

  Similarly, the address data fetched from the address bus 50c is also fetched into the latch circuit 100, and then processed in the predecoder 252 to propagate to the corresponding memory cell block, and then the driver circuit 254. Is driven for a certain period of time. After that, even when the driver circuit 254 having the tri-state configuration is operated by a voltage lower than the power supply voltage VCC or a voltage higher than the ground voltage VSS in accordance with the inactivation of the control signal SCRC, the driver circuit 254 The output is in a floating state.

  The level of the predecode signal driven by the driver circuit 254 is held by the level holding circuit 256. With the above configuration, the circuit system above the driver circuit 254 is output to the memory cell array even when the hierarchical power supply configuration is reset in a direction to reduce the subthreshold current of the MOS transistor constituting the circuit system. This predecode address signal holds that state.

  FIG. 13 is a schematic block diagram showing the configuration of latch circuit 98, driver circuit 226, and level holding circuit 228 shown in FIG.

  Driver circuit 226 receives control signal SCRC at one input node and NAND circuit 2286 receives one output signal of latch circuit 98 at the other, and receives control signal SCRC at one input node and latch circuit at the other input node. The NAND circuit 2288 receiving the other output of 224, the gate potential is controlled by the output of the NAND circuit 2286, the N channel MOS transistor 2290 receiving the hierarchical power supply voltage S-GND (voltage of the sub ground line) at the source, and the gate P channel MOS transistor 2292 receiving the output of NAND circuit 2288 and receiving hierarchical power supply voltage S-VCC (sub power supply line voltage) at its source. The drain of N channel MOS transistor 2290 and the drain of P channel MOS transistor 2292 are connected, and the potential level of this connection node is the output potential of driver circuit 226.

  Level holding circuit 228 is a latch circuit activated by control signal SCRC2. Control signal SCRC2 is activated at the same time as control signal SCRC, and is deactivated in response to inactivation of control signal SCRC at time t6 in FIG.

  FIG. 16 is a timing chart for explaining the operation of predecode circuit 300 shown in FIG.

  In FIG. 16, signals B0 to B3 are signals indicating bank addresses, a signal Row is a row access identification signal instructing activation of a row (row) circuit operation, and a signal Clm is a column (column) Column) access identification signal for instructing the activation of the circuit operation of the (system), and the signal ACT is a bank activation signal.

  Further, the flag signal is a signal held in the level holding circuit 208 in response to the bank being accessed (bank hit), and the signal PC is a precharge signal for instructing the precharge operation of the selected bank. A signal APC is an all-bank precharge signal for instructing the precharge operation of all banks.

  Signal l. EQ is a local bit line equalize signal held by level holding circuit 228, and signals l. RXT is a local word line activation signal held by level holding circuit 238, and signals l. SE is a local sense amplifier activation signal held by the level holding circuit 248, and the potential MWL is the potential level of the main word line in the memory cell block (bank).

Signal Add. The latch is an address signal held in the level holding circuit 256.
Next, the operation will be described. At the rising edge of clock signal CLK at time t1, bit B3 in the decoded bank address is active, and the corresponding bank is selected. At this time, since the signal Row is also in an active state, an active one-shot pulse is output from the one-shot pulse generation circuit 204 accordingly. In response to this, the active signal ACT transmitted through the command bus 53b is driven by the driver circuit 206, and the level of the active signal ACT is held in the level holding circuit 208 as a flag signal.

  In response to the activation of the flag signal, the level of the signal EQ transmitted by the command bus 53b is held in the latch circuit 98.

  At time t1, the control signal SCRC is also at the H level, and all the circuits in the hierarchical power supply region operate by receiving the power supply voltage VCC and the ground voltage VSS.

  The level of the signal EQ taken into the latch circuit 98 is driven by the driver circuit 226, and the internal equalize signal l. It is held as EQ.

  The control signal SCRC2 is a signal that resets the level holding circuits 228, 238, and 248, and the signal RDDRV is a signal that controls the operation of the driver circuit 254. At time t1, in response to the bank address signal B3 and the signal Row being in the active state, the level of the active signal ACT is taken from the command bus 53b to the level holding circuit 208, and the level holding circuit The level of the flag output from 208 changes to the H level. In response to this, the driver control signal RDDRV output from the driver control circuit 302 becomes H level. Control signals SCRC and SCRC2 are also activated.

  On the other hand, at time t2, signal RXT transmitted through command bus 53b is activated, and this level is taken into latch circuit 234. In response, level holding circuit 238 receives internal word line activation signal l. The level of RXT is kept active.

  Subsequently, at time t3, the level of the signal SE transmitted through the command bus 53b is activated, and this level is taken into the latch circuit 244. In response, level holding circuit 248 causes internal sense amplifier activation signal l. The SE level is kept active.

  Internal word line activation signal l. In response to the activation of RXT, the potential level of the main word line in the selected row changes to the H level.

  On the other hand, the address signal transmitted through the address bus 50c is latched by the latch circuit 100, predecoded by the predecoder 252 and then driven by the driver 254, and the level of the row predecoder line PDL corresponds to each. Driven to level. At time t4, the control signal SCRC changes to L level by the predecoder 252 according to the level of the row predecoder line PDL. Signal RDDRV also changes to L level at time t4.

  That is, the period from time t1 to time t4 is a period required for the operation of the total circuit of one bank.

  When control signal SCRC is inactivated, the circuits included in the hierarchical power supply region shift to a mode in which leakage current is reduced.

  In contrast to this, internal equalize signals l.m output from level holding circuits 228, 238 and 248, respectively. EQ, internal word line activation signal l. RXT and internal sense amplifier activation signal l. SE holds that level.

  At the rising edge of the clock signal CLK at time t5, the bank signal B3 and the signal Row are activated, and the precharge signal PC is activated, whereby the level of the signal PC input via the driver circuit 210 is increased. In response, inverters 222, 232, and 242 are driven by signals output from one-shot pulse generation circuit 214, and the levels of latch circuits 98, 234, and 244 are reset.

  On the other hand, since control signal SCRC is also activated at time t5, signal l. EQ, l. RXT and l. SE also resets its level. The level held by the latch circuit 100 is also reset in response to the activation of the control signal SCRC, and the level of the row predecode line PDL is also reset accordingly.

  That is, in the period from time t4 to t5, the circuit included in the hierarchical power supply region is reset to reduce the leakage current, but the signal l. EQ, signal l. RXT, signal l. All the levels of the SE and row predecoder lines PDL hold the levels.

  With the above configuration, it is possible to reduce the occupied area of the address bus by providing a common address bus for the banks that operate independently.

In addition, after a predetermined period (period from time t1 to time t4) for taking in the command signal and address signal for the selected and activated bank ends, the circuits included in the hierarchical power supply region Since it is possible to reduce the leakage current, it is possible not only to reduce the leakage current in the standby state, but also to reduce the leakage current during the period when the bank is in the active state.

[Embodiment 7]
The latch circuits in the fourth and fifth embodiments shown in FIGS. 8 and 10 can be used for the latch circuits 102 and 104 in the SDRAM column predecoder shown in FIG. The same applies to the other latch circuits 524, 534, and 548. The latch circuit 102 latches column-related command signals Read, Write, ATPC, BEND, TERM, and PCCMP. The latch circuit 104 latches the column address signal.

  In latch circuit 102, as shown in FIG. 18, P-channel MOS transistor 1021 is connected to the gate of transistor 80, and P-channel MOS transistor 1022 is connected to the gate of transistor 82. A flag signal BACT generated when the bank is activated is applied to the gates of the transistors 1021 and 1022. In latch circuit 102, N-channel MOS transistors 1024 to 1028 forming wired OR circuit 516 (FIG. 17) are provided.

  In order to recognize the attribute of the activation cycle at the time of activation of the bank, a portion usually constituted by a CMOS logic circuit is also constituted by a wired OR circuit 516 in order to speed up the determination. Reset system signals (auto precharge ATPC, burst end BEND, termination TERM wired OR logic output are applied to the gate of transistor 82, and bank activation system signal (bank hit BH) is applied to the gate of transistor 80. The latch operation as a flag is determined by determining the H or L level of the latch circuit 76. When the bank is activated, the gate voltage of the transistor 80 becomes H level in response to the input of the bank hit signal BH, The gate voltage of the transistor 82 becomes L level, the output signal / BB of the latch circuit 76 becomes L level, and the output signal BB becomes H level.When the burst end signal BEND is input at the end of the bank operation, When the bank hit signal BH is at L level, The gate voltage of the transistor 80 becomes L level, the gate voltage of the transistor 82 becomes L level, the output signal / BB of the latch circuit 76 becomes H level, the output signal BB becomes L level, and the latch circuit 76 is reset. The

  On the other hand, in latch circuit 104, as shown in FIG. 19, P-channel MOS transistor 1041 is connected to the gate of transistor 80, and P-channel MOS transistor 1042 is connected to the gate of transistor 82. Bank hit signal BH from one-shot pulse generation circuit 512 is applied to the gates of transistors 1041 and 1042.

[Details of column predecoder]
The details of the SDRAM column predecoder will be described below for reference.

  FIG. 17 is a schematic block diagram showing the configuration of the column predecoder 400. Referring to FIG. 17, a read system access identification signal READ for instructing a read operation, a write system access identification signal WRITE for instructing a write operation, and an auto precharge operation through command bus 53b. Auto precharge identification signal ATPC for instructing, burst end identification signal BEND for instructing the end of the burst operation for each bank, and this column selection operation when another bank is selected during the column selection operation A termination identification signal TERM for instructing to forcibly end and a precharge operation identification signal PCCM for instructing the end of the precharge operation are transmitted.

  The signal BACT is a flag signal held in the level holding circuit 208 (FIG. 12) when a bank is selected.

  Column predecoder circuit 34 receives bank address signal B3 corresponding to signal Clm transmitted by command bus 53b, and outputs a one-shot pulse signal in response to the activation of AND circuit 510. One-shot pulse generation circuit 512, drive circuit 514 activated in response to activation of flag signal BACT and driving the output of one-shot pulse generation circuit 512, and OR circuit 516 receiving signal ATPC, signal BEND and signal TERM Are set by the output of the drive circuit 514, reset by the output of the wired OR circuit 516, and the column flag signal Col. And a latch circuit 102 that outputs FLAG.

  The column predecoder circuit 34 further includes a column flag signal Col. An inverter circuit 520 that is activated in response to the activation of FLAG and drives signal READ transmitted by command bus 53b, an OR circuit 522 that receives signal WRITE, signal ATPC, signal BEND and signal TERM, and inverter circuit 520 Set by the output, reset by the output of the wired OR circuit 522, and read flag signal READ. And a latch circuit 524 that outputs FLAG.

  The column predecoder circuit 34 further includes a column flag signal Col. An inverter circuit 530 that drives signal WRITE that is activated in response to activation of FLAG and transmitted by command bus 53b, OR circuit 532 that receives signal READ, signal ATPC, signal BEND, and signal TERM, and inverter circuit 530 Set by the output, reset by the output of wired OR circuit 532, and write flag signal WRITE. And a latch circuit 534 that outputs FLAG.

  The column predecoder circuit 34 further includes a column flag signal Col. Shift circuit 542 that receives FLAG and delays by a predetermined clock time, OR circuit 540 that receives the output of flag signal BACT and shift circuit 542, and is activated in response to activation of the output of OR circuit 540, and is transmitted by command bus 53b. The inverter circuit 544 that drives the signal ATPC generated, the inverter circuit 546 that receives the signal PCCMP transmitted by the command bus 53b, and the output of the inverter circuit 544 are set, and the output is reset by the output of the inverter circuit 546, and the auto precharge operation Auto precharge flag signal ATPC. And a latch circuit 548 that outputs FLAG.

  Column predecoder circuit 34 further includes a latch circuit 550 that is activated in response to an output signal of one-shot pulse generation circuit 512 and takes in a column signal transmitted through address bus 50c. Latch circuit 550 is reset in response to activation of control signal SCRC.

Column predecoder circuit 34 further adjusts the lower bits of the address signal corresponding to the column selection line (not shown) to be activated in accordance with the lower bits of the column address held in latch circuit 550. 552 and odd bit adjustment circuit 554, predecoder 556 for predecoding upper bit data from latch circuit 550, predecoder 557 for predecoding lower bit data from even bit adjustment circuit 552, and odd bit adjustment circuit 554 Predecoder 558 that predecodes lower-order bit data from, and activated by signal READ or signal WRITE, the predecode signals from predecoders 556, 557, and 558 are delayed by a predetermined number of clocks (for example, two clocks). Output shift circuit 5 0 and activated in response to a signal Miss indicating that an address from a redundant decoder (not shown) does not correspond to a defective address, and receives the output from the shift circuit 560 to change the level of the column predecode line. Drive circuit 562 for driving in accordance with the output signal of the output signal.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a circuit diagram showing a configuration of a semiconductor circuit device according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration of a power supply selector shown in FIG. 1. FIG. 2 is a circuit diagram showing a configuration of a latch circuit shown in FIG. 1. It is a circuit diagram which shows the structure of the semiconductor circuit device by Embodiment 2 of this invention. FIG. 5 is a circuit diagram showing a configuration of a power supply selector shown in FIG. 4. It is a circuit diagram which shows the structure of the semiconductor circuit device by Embodiment 3 of this invention. FIG. 7 is a circuit diagram showing a configuration of a latch circuit and a drive circuit shown in FIG. 6. It is a circuit diagram which shows the structure of the semiconductor circuit device by Embodiment 4 of this invention. FIG. 9 is a timing chart showing an operation of the semiconductor circuit device shown in FIG. 8. It is a circuit diagram which shows the structure of the semiconductor circuit device by Embodiment 5 of this invention. FIG. 11 is a timing chart showing an operation of the semiconductor circuit device shown in FIG. 10. It is a block diagram which shows the structure of the row predecoder in SDRAM by Embodiment 6 of this invention. It is a circuit diagram which shows the detailed structure of the circuit part XIII shown by FIG. FIG. 14 is a circuit diagram showing a configuration of a latch circuit shown in FIG. 13. FIG. 13 is a circuit diagram showing a configuration of a latch circuit that receives the address signal shown in FIG. 12. FIG. 13 is a timing diagram illustrating an operation of the SDRAM illustrated in FIG. 12. It is a block diagram which shows the structure of the column predecoder in SDRAM by Embodiment 7 of this invention. FIG. 18 is a circuit diagram showing a configuration of a latch circuit that receives the command signal shown in FIG. 17. FIG. 18 is a circuit diagram showing a configuration of a latch circuit that receives the address signal shown in FIG. 17. FIG. 18 is a block diagram showing an overall configuration of an SDRAM including the row predecoder shown in FIG. 12 and the column predecoder shown in FIG. 17.

Explanation of symbols

  10 main power supply line, 12 sub power supply line, 14, 62 P channel MOS transistor, 20, 80, 82 N channel MOS transistor, 16 main ground line, 18 sub ground line, 22, 24 buffer power supply line, 26, 28 buffer ground 30, 32, 46, 78 CMOS inverter circuit, 34, 36, 38, 40, 58, 60 power supply selector, 44, 68, 76, 84, 98, 100, 102, 104 latch circuit, 64 latch fixed power supply line , 66 Latch fixed ground line, 70 Latch drive power supply line, 72 Latch drive ground line, 74, 86, 88, 90, 92, 94, 96 Drive circuit.

Claims (2)

A semiconductor circuit device having an operation mode and a standby mode,
The main power line,
A switching element connected between a node receiving a power supply voltage and the main power supply line, turned on in the operation mode and turned off in the standby mode;
The main ground wire,
A latch fixed power line for receiving the power supply voltage;
A latch fixed ground wire that receives a ground voltage; and
A plurality of logic circuits each connected between the main power supply line and the main ground line;
A latch circuit connected between the latch fixed power line and the latch fixed ground line;
A semiconductor circuit device comprising: a blocking unit that blocks signal input to the latch circuit in the standby mode.   The semiconductor circuit device according to claim 1, wherein the latch circuit is arranged before the plurality of logic circuits.

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