CN112020744A - Nonvolatile memory circuit - Google Patents
Nonvolatile memory circuit Download PDFInfo
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- CN112020744A CN112020744A CN201980015138.XA CN201980015138A CN112020744A CN 112020744 A CN112020744 A CN 112020744A CN 201980015138 A CN201980015138 A CN 201980015138A CN 112020744 A CN112020744 A CN 112020744A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
- G11C14/0081—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell
Abstract
The present technology relates to a nonvolatile memory circuit that allows miniaturization and reduced power consumption while maintaining stable writing. The nonvolatile memory circuit is provided with: a volatile storage unit for storing information; and a nonvolatile memory section that writes information in the volatile memory section into the nonvolatile memory section by a memory operation, and reads information from the nonvolatile memory section into the volatile memory section through a restore path different from a memory path for the memory operation by a restore operation, wherein all transistors arranged along the memory path have their drains connected together. The present technique can be applied to NVDFF circuits.
Description
Technical Field
The present technology relates to a nonvolatile memory circuit, and particularly relates to a nonvolatile memory circuit that realizes miniaturization while maintaining stable writing and enables low power consumption to be maintained.
Background
Conventionally, Power Gating (PG) is used as a low power consumption technique for reducing leakage current.
Further, as a nonvolatile flip-flop (NVFF) using PG, there has been proposed an NVFF that connects a Magnetic Tunnel Junction (MTJ) as a nonvolatile memory (NVM) to a flip-flop circuit to be subjected to PG, and can immediately perform logic restoration when power is restored (for example, refer to patent document 1). In such NVFF using MTJ, low power consumption can be achieved to some extent while maintaining stable writing.
CITATION LIST
Patent document
Patent document 1: WO 2016/185903A
Disclosure of Invention
Problems to be solved by the invention
However, in the above NVFF, in order to cause a large storage current to flow to the MTJ at the time of writing, that is, at the time of storage, it is necessary to increase a transistor for forming a latch or a transistor for selecting the MTJ, and therefore the circuit size of the entire NVFF increases.
For example, in the above NVFF, two MTJs are provided, and transistors arranged on a path of a storage current, that is, arranged on a storage path are connected to the respective MTJs. Either of the two transistors is always a source connection with the MTJ connected to the ground side of the transistor.
Therefore, the gate width of the transistor needs to be increased to ensure a sufficient magnitude of the storage current. In addition, it is also necessary to increase the gate width of the transistor to prevent disturbance of the latch (latch destruction) at the time of storage.
The present technology is designed in consideration of such a situation, and can obtain a compact nonvolatile memory circuit with low power consumption while maintaining stable writing.
Solution to the problem
A nonvolatile memory circuit according to an aspect of the present technology includes: a volatile storage section configured to store information; and a nonvolatile memory section that writes information in the volatile memory section into the nonvolatile memory section by a memory operation and reads information from the nonvolatile memory section into the volatile memory section by a restore operation through a restore path different from a memory path at the time of the memory operation, wherein all transistors arranged on the memory path are drain-connected.
According to an aspect of the present technology, a volatile storage section and a nonvolatile storage section are provided in a nonvolatile storage circuit, the volatile storage section is configured to store information, and the information in the volatile storage section is written in the nonvolatile storage section by a storage operation, and the information is read out from the nonvolatile storage section to the volatile storage section through a restoration operation through a restoration path different from a storage path at the time of the storage operation, and all transistors arranged on the storage path are drain-connected.
Drawings
Fig. 1 is a diagram showing a configuration example of an NVDFF circuit of the head SSR-NVFF circuitry.
Fig. 2 is a diagram describing a storage path.
Fig. 3 is a diagram depicting a restoration path.
Fig. 4 is a diagram showing a configuration example of the NVDFF circuit of the foot SSR-NVFF circuitry.
Detailed Description
Hereinafter, embodiments to which the present technology is applied will be described with reference to the drawings.
< first embodiment >
< example of configuration of NVDFF circuit >
By avoiding arranging transistors connected with the source on the storage path and making all transistors on the storage path drain-connected, the present technology can obtain a compact nonvolatile memory circuit with low power consumption while maintaining stable writing.
Fig. 1 is a diagram showing a configuration example of a nonvolatile D flip-flop (NVDFF) nonvolatile flip-flop circuit serving as a head-type split storage/restore nonvolatile flip-flop (SSR-NVFF) circuit system of a nonvolatile memory circuit to which the present technology is applied.
The NVDFF circuit 11 shown in fig. 1 includes a volatile storage section 21, a storage driver 22, a transistor 23, a storage driver 24, a transistor 25, a transistor 26, a transistor 27, a nonvolatile storage section 28, a control driver 29, an or circuit 30, and a transistor 31. Here, the transistor 23, the transistor 25, the transistor 26, the transistor 27, and the transistor 31 are nMOS transistors.
For example, for PG of the NVDFF circuit 11, a pMOS transistor (not shown) is used as the Power Switch (PS). Specifically, for example, when the PS is turned on, power is supplied from the power supply line to each component of the NVDFF circuit 11 via the pMOS transistor, and when the PS is turned off, each component of the NVDFF circuit 11 is electrically separated from the power supply line, thereby implementing PG.
The volatile memory section 21 includes a flip-flop circuit that temporarily holds storage data as information supplied from the outside, more specifically, a state of a storage node such as a voltage level corresponding to the storage data.
The volatile memory section 21 includes an inverter 41, a transmission gate 42, a master latch 43, a transmission gate 44, a slave latch 45, and an inverter 46.
Further, the master latch 43 includes an inverter 51, an inverter 52, and a transmission gate 53.
Further, the slave latch 45 includes an inverter 61, an inverter 62, a transmission gate 63, and a transistor 64. Further, the slave latch 45 includes a storage node N11 and a storage node N12.
In the volatile memory section 21, the transfer gate 42 and the transfer gate 63 are turned on at the timing when the clock signal CLK falls, and turned off at the timing when the clock signal CLK rises.
In contrast, the transfer gate 53 and the transfer gate 44 are turned off at the timing when the clock signal CLK falls, and are turned on at the timing when the clock signal CLK rises.
An input side of the inverter 41 corresponds to an input terminal of the volatile memory section 21, and an output side of the inverter 41 is connected to an input side of the inverter 51 via the transmission gate 42.
Further, the storage node N11 of the slave latch 45 is connected to the output side of the inverter 51 via the transmission gate 44, and the output terminal of the inverter 51 is also connected to the input side of the inverter 52.
Further, the output side of the inverter 52 is connected to the input side of the inverter 51 via a transmission gate 53. In other words, the output side of the transmission gate 53 is connected between the inverter 51 and the transmission gate 42 via the transmission gate 53.
The slave latch 45 includes a storage node N11 and a storage node N12 temporarily holding a voltage level corresponding to input storage data, and an inverter 61 is disposed between the storage node N11 and the storage node N12.
Further, the respective input terminals of the inverter 46, the inverter 62, and the storage driver 24 are connected to the storage node N12.
The output side of the inverter 46 corresponds to the output terminal of the volatile memory unit 21.
The output side of the inverter 62 is connected to the storage node N11 via the transmission gate 63. Further, a transistor 64 as an nMOS transistor is connected to both ends of the transmission gate 63. In other words, one end of the transistor 64 is connected to the input side of the transfer gate 63, and the other end of the transistor 64 is connected to the output side of the transfer gate 63. A control signal R of a predetermined voltage level is supplied to the gate of the transistor 64.
The input terminal of the storage driver 22 is also connected to the storage node N11.
The storage driver 22 includes an inverter as an inverting element. In other words, the memory driver 22 includes a transistor 71 as a pMOS transistor and a transistor 72 as an nMOS transistor.
In the storage driver 22, one end of the transistor 71 is connected to a power supply, and the other end of the transistor 71 is connected to the transistor 72.
Further, one end of the transistor 72 opposite to the one end connected to the transistor 71 is grounded via the transistor 23. The control signal SR2 is supplied to the gate of the transistor 23.
Further, one end of the output side of the inverter including the transistor 71 and the transistor 72 is connected to the nonvolatile memory portion 28 via a node N13.
The storage driver 24 includes an inverter as an inverting element. In other words, the memory driver 24 includes a transistor 81 as a pMOS transistor and a transistor 82 as an nMOS transistor.
In the storage driver 24, one end of the transistor 81 is connected to a power supply, and the transistor 82 is connected to the other end of the transistor 81.
Further, one end of the transistor 82 on the opposite side to the one end connected to the transistor 81 is grounded via the transistor 25. The control signal SR2 is supplied to the gate of the transistor 25.
Further, one end of the output side of the inverter including the transistor 81 and the transistor 82 is connected to the nonvolatile memory portion 28 via a node N14.
The nonvolatile storage unit 28 is a nonvolatile storage unit. At the time of storage (writing), the states of the voltage levels at the storage node N11 and the storage node N12, that is, the storage data are written in the nonvolatile storage section 28.
Further, at the time of recovery (reading), the storage data held in the nonvolatile memory section 28, that is, the held state of the voltage level is read to the storage node N11 and the storage node N12 through a path different from that at the time of storage.
The nonvolatile memory portion 28 includes a memory element 91 and a memory element 92.
The storage element 91 and the storage element 92 each include, for example, a nonvolatile storage element such as MTJ as a magnetoresistive element or resistive random access memory (ReRAM) as a resistive memory.
Note that the following description will be continued using a case where the memory element 91 and the memory element 92 are MTJs as an example.
The MTJ is a nonvolatile memory element which includes a fixed layer (p layer) and a free layer (f layer) and a barrier layer formed between the fixed layer and the free layer, and can change a resistance to a high resistance state or a low resistance state depending on an applied voltage.
Thus, for example, information can be stored in the MTJ by setting the H level, that is, "1" serving as storage data, as a higher voltage level to a high resistance state, and setting the L level, that is, "0" serving as storage data, as a lower voltage level to a low resistance state.
In the present embodiment, the low resistance state of the MTJ is referred to as a parallel state (hereinafter, also referred to as a P state), and the high resistance state is referred to as an anti-parallel state (hereinafter, also referred to as an AP state).
In the nonvolatile memory section 28, the free layer of the memory element 91 is connected to the control line L11, and the opposite side of the free layer, that is, the fixed layer of the memory element 91 is connected to the node N14.
The node N14 is connected to one end of the storage driver 24 on the output side, and is also connected to the storage node N11 via the transistor 26.
In a similar manner, the free layer of storage element 92 is connected to control line L11, and the fixed layer of storage element 92 is connected to node N13.
The node N13 is connected to one end of the storage driver 22 on the output side, and is also connected to the storage node N12 via the transistor 27.
The control signal SR1 is supplied to the gates of transistor 26 and transistor 27.
Further, a control driver 29 for controlling the voltage level in the control line L11 is connected to the control line L11 connected to the storage element 91 and the storage element 92.
The control driver 29 includes an inverter as an inverting element. In other words, the control driver 29 includes a transistor 101 as a pMOS transistor and a transistor 102 as an nMOS transistor.
In the control driver 29, one end of the transistor 101 is connected to a power supply, and the transistor 102 and the control line L11 are connected to the other end of the transistor 101.
Further, one end of the transistor 102 on the opposite side to the one end connected to the transistor 101 and the control line L11 is grounded via the transistor 31.
The control signal CTRL is supplied to one end of the input side of the control driver 29, that is, the gate of the transistor 101 and the gate of the transistor 102.
One end of the output side of the or circuit 30 is connected to the gate of the transistor 31, and the control signal SR1 and the control signal SR2 are supplied to one end of the input side of the or circuit 30.
Note that, for example, in a case where one NVDFF circuit 11 is regarded as one unit forming a memory and a plurality of units are provided in the memory, the transistor 31 in each NVDFF circuit 11 is brought into a conductive state in the storage mode and the recovery mode.
At this time, as the or circuit 30 for bringing the transistor 31 into a conducting state, one common or circuit may be provided to be shared by all of the plurality of cells, that is, all of the plurality of NVDFF circuits 11.
< operation of NVDFF Circuit >
Next, the operation of the NVDFF circuit 11 shown in fig. 1 will be described.
The NVDFF circuit 11 includes four operation modes as operation modes, including an active mode, a storage mode, a sleep mode, and a recovery mode. Then, during operation of the NVDFF circuit 11, the operation mode is sequentially changed from the active mode to the storage mode, the sleep mode, and the recovery mode.
First, in the active mode, the PS (not shown) is turned on. Further, the control signal SR1 is set to the H level, and the transistor 26 and the transistor 27 are turned on. In other words, the transistor 26 and the transistor 27 are brought into a conductive state (on state). At this time, the control signal SR2 is set to the L level.
In this state, for example, when an L level is input to the inverter 41 as the storage data, the output of the inverter 41 is set to an H level. At the timing when the clock signal CLK falls, that is, at the timing when the transmission gate 42 is turned on, the H level is input to the inverter 51.
Then, since the transmission gate 53 and the transmission gate 44 are turned on at the timing when the clock signal CLK next rises, the output of the inverter 51 is set to the L level through the loop of the inverter 51 and the inverter 52. The L level is supplied to the storage node N11 via the transmission gate 44 as storage data.
Therefore, the output of the inverter 61 connected to the storage node N11 is set to the H level, and the output of the inverter 46 connected to the storage node N12 is set to the L level.
Thereafter, when the timing at which the clock signal CLK falls comes, the transmission gate 53 and the transmission gate 44 are turned off, and the transmission gate 42 and the transmission gate 63 are turned on. Then, the L level indicating the stored data is held (stored) in the storage node N11 and the H level obtained by inverting the stored data is held in the storage node N12 through a loop including the inverter 61 and the inverter 62.
If the stored data input in this manner is latched by the slave latch 45, the toggling of the clock signal CLK stops.
Subsequently, in the storage mode, the control signal SR1 is set to the L level and the transistor 26 and the transistor 27 are brought into an off state, and the control signal SR2 is set to the H level and the transistor 23 and the transistor 25 are brought into an on state.
At this time, since the output of the or circuit 30 to which the control signal SR1 and the control signal SR2 are supplied (input) is set to the H level, the transistor 31 having the gate to which the H level is supplied enters the on state.
Then, since the state of the storage node N11 is set to the L level, in the storage driver 22 connected to the storage node N11, the transistor 71 is brought into an on state, and the output terminal of the storage driver 22, that is, the node N13 is set to the H level.
In contrast, since the state of the storage node N12 is set to the H level, in the storage driver 24 connected to the storage node N12, the transistor 82 is brought into a conductive state, and the output terminal of the storage driver 24, that is, the node N14 is set to the L level.
Further, if the control signal CTRL is set to the L level at this time, the transistor 101 is brought into a conductive state, for example, in the control driver 29, and the output terminal of the control driver 29, that is, the control line L11 is set to the H level.
At this time, since the control line L11 is set to the H level and the node N14 is set to the L level, the storage current flows from the power supply connected to the control driver 29 to the ground through the control driver 29, the control line L11, the storage element 91, the node N14, the transistor 82, and the transistor 25.
In this case, in the memory element 91, since a current (memory current) flows from the free layer connected to the control line L11 side to the fixed layer connected to the node N14 side, the memory element 91 enters a low resistance state, that is, a P state.
Therefore, the state "H level" held in the storage node N12 is inverted by the storage driver 24 and held (stored) in the storage element 91. In other words, the state "H level" held by the storage node N12 is inverted and written (stored) in the storage element 91.
Thereafter, if the control signal CTRL is further switched from the L level state to the H level state, the transistor 101 is turned off and the transistor 102 is brought into a conductive state in the control driver 29. As a result, the output terminal of the control driver 29, that is, the control line L11 is grounded and set to the L level.
Then, since the control line L11 is set to the L level and the node N13 is set to the H level, the storage current flows from the power supply connected to the storage driver 22 to the ground through the transistor 71, the node N13, the storage element 92, the control line L11, the transistor 102, and the transistor 31.
In this case, in the memory element 92, since a current (storage current) flows from the fixed layer connected to the node N13 side to the free layer connected to the control line L11 side, the memory element 92 enters a high resistance state, that is, an AP state.
Therefore, the state "L level" held at the storage node N11 is inverted by the storage driver 22 and held in the storage element 92. In other words, the state "L level" held by the storage node N11 is inverted and written into the storage element 92.
If the states of the voltage levels at the storage node N11 and the storage node N12 are stored in the storage element 92 and the storage element 91 in this manner, the control signal CTRL is thereafter set to the L level, and the storage operation ends.
In the above-described memory operation, for example, a memory current flows through the path shown in fig. 2. Note that in fig. 2, portions corresponding to the case shown in fig. 1 are assigned the same reference numerals, and description thereof will be omitted as appropriate.
In the example shown in fig. 2, a path (hereinafter, will also be referred to as a storage path) for storing a current in the above-described storage operation is shown.
Specifically, a broken line L21 indicates a storage path when information (state) is stored into the storage element 91 at the timing when the control signal CTRL is set to the L level. On the memory path indicated by a broken line L21, the transistor 101, the memory element 91, the transistor 82, and the transistor 25 are arranged.
In contrast, a broken line L22 indicates a storage path when information (state) is stored in the storage element 92 at the timing when the control signal CTRL is set to the H level. On the memory path indicated by a broken line L22, the transistor 71, the memory element 92, the transistor 102, and the transistor 31 are arranged.
Meanwhile, in WO 2016/185903a (hereinafter, will also be referred to as document 1), for example, an NVDFF circuit having a storage path and a restoration path different from each other is proposed.
In such an NVDFF circuit, the transistor 23, the transistor 25, the transistor 31, and the or circuit 30 in the NVDFF circuit 11 are not provided. In the NVDFF circuit, transistors are provided at a position on the storage path corresponding to a position between the storage driver 22 and the storage element 92 and at a position on the storage path corresponding to a position between the storage driver 24 and the storage element 91.
In this case, either of the two transistors is always a source connection, with the MTJ connected to the ground side of the transistor.
Therefore, when the storage current flows to the MTJ via the transistor which is the source connection, the storage current becomes smaller due to the reverse bias effect. Therefore, in order to secure a sufficient magnitude of memory current, it becomes necessary to widen the gate width of the transistor, and the circuit size increases.
In contrast, in the NVDFF circuit 11, the transistor 23, the transistor 25, and the transistor 31 are provided between the ground and the storage driver 22, the storage driver 24, and the control driver 29, respectively.
Therefore, in the NVDFF circuit 11, it is not necessary to provide a transistor between the storage driver 22 and the storage element 92 or between the storage driver 24 and the storage element 91.
As a result, in the NVDFF circuit 11, the transistors that are source-connected are not arranged on the storage path, and all the transistors arranged on the storage path are drain-connected, with the storage elements connected to the opposite side of the grounded side of the transistors.
Specifically, for example, the transistor 25 arranged on the storage path indicated by the broken line L21 is a drain connection in which the storage element 91 is connected to the drain side (power supply side).
In a similar manner, the transistor 31 arranged on the storage path indicated by the broken line L22 is also drain connected, with the storage element 92 connected to the drain side. Further, in the case where a storage current flows in the transistor 23 at the time of storage, since the storage current flows from the storage element 92 to the ground through the transistor 23, the transistor 23 is connected to the drain in this case.
Therefore, in the NVDFF circuit 11, since the memory current does not become smaller due to the reverse bias effect, a sufficient memory current can be secured even with a transistor having a narrow gate width, so that the circuit size of the entire NVDFF circuit 11 can also be suppressed.
Further, since the NVDFF circuit 11 has such a structure: in which the storage driver receives the voltage level of the storage node of the slave latch 45 at the time of storage and writes the output into the storage element through a path that does not affect the voltage level of the storage node, latch destruction does not occur. That is, stable writing can be performed.
From these aspects, according to the NVDFF circuit 11, a compact NVDFF circuit 11 with low power consumption can be obtained while maintaining stable writing.
The description returns to the description of the operation of the NVDFF circuit 11. When the states of the storage node N12 and the storage node N11 are stored in the storage element 91 and the storage element 92 in the storage mode, the mode after an appropriate timing is shifted to the sleep mode.
In the sleep mode, the PS (not shown) is turned off and power supplied to the NVDFF circuit 11 is blocked. Therefore, the voltage level of the output side of the inverter 46 is set to the L level.
Thereafter, when recovering from the sleep state, an operation in the recovery mode (recovery operation) is performed.
In the recovery mode, the control signal SR1 is set to the H level and the transistor 26 and the transistor 27 are brought into a conductive state, and the control signal SR2 is set to the L level and the transistor 23 and the transistor 25 are brought into an off state (a non-conductive state).
At this time, since the control signal SR1 is set to the H level and the control signal SR2 is set to the L level, the output of the or circuit 30 is set to the H level, and the transistor 31 enters the on state.
Further, the control signal CTRL is set to the H level, the transistor 102 of the control driver 29 is brought into a conductive state, and the control line L11 is grounded. In other words, the control line L11 is set to the L level.
If PS is turned on from such a state, a recovery current flows from the slave latch 45 side to which the power supply voltage is supplied to the control line L11 through the storage element 91 and the storage element 92.
Here, as described in the above example, it is assumed that the memory element 91 is in a low resistance state, that is, in a P state, and the memory element 92 is in a high resistance state, that is, in an AP state.
In this case, as shown in fig. 3, the recovery current flows through four paths indicated by broken lines L41 to L44 (hereinafter, will also be referred to as recovery paths).
In fig. 3, the recovery path indicated by a broken line L41 is a path in which a recovery current flows from the power supply to the ground through the transistor 81, the node N14, the memory element 91, the control line L11, the transistor 102, and the transistor 31.
The recovery path indicated by the broken line L42 is a path in which a recovery current flows from the inverter 62 to ground through the transmission gate 63, the transistor 26, the node N14, the storage element 91, the control line L11, the transistor 102, and the transistor 31.
Further, the recovery path indicated by the broken line L43 is a path in which a recovery current flows from the power supply to the ground through the transistor 71, the node N13, the memory element 92, the control line L11, the transistor 102, and the transistor 31.
The recovery path indicated by the broken line L44 is a path in which a recovery current flows from the inverter 61 to the ground through the transistor 27, the node N13, the memory element 92, the control line L11, the transistor 102, and the transistor 31.
If the recovery current flows through each recovery path in this manner, the voltage of the node N13 rises more than the voltage of the node N14 due to the resistance difference between the storage element 91 and the storage element 92.
As a result, the conductance drop due to the rise in the source voltage is more significant in transistor 27 than in transistor 26. Therefore, the current flowing in the transistor 27 becomes smaller than the current flowing in the transistor 26 by an amount corresponding to or larger than the resistance difference between the memory element 91 and the memory element 92.
As a result, the voltage of the storage node N12 rises more than the voltage of the storage node N11, the storage node N12 has the power supply voltage (H level) by performing positive feedback through the loop including the inverter 61 and the inverter 62 in the slave latch 45, and the storage node N11 is set to the ground level (L level). In other words, the state is restored to the same state as the state of the voltage levels of the storage node N11 and the storage node N12 at the time of storage.
For example, in the NVDFF circuit described in document 1, elements corresponding to the transistor 23 and the transistor 25 in the NVDFF circuit 11 are not provided. In contrast, in the NVDFF circuit 11, by providing the transistor 23 and the transistor 25, the recovery time can be shortened without consuming unnecessary power at the time of recovery.
For example, it is assumed that the transistor 23 is not provided in the NVDFF circuit 11. In this case, if the recovery current passes through the path indicated by the broken line L42 shown in fig. 3 at the time of recovery, the input terminal of the driver for storage 22 has an intermediate voltage between the power supply voltage and the ground level, and both the transistor 71 and the transistor 72 enter the on state.
As a result, in the storage driver 22, a large current flows from the power supply to the ground through the transistor 71 and the transistor 72, and power consumption increases.
However, actually, the transistor 23 is provided in the NVDFF circuit 11, and the transistor 23 is in an off state at the time of the recovery operation. Therefore, in the storage drive 22, unnecessary current does not flow from the power supply to the ground, current flows from the power supply through the path indicated by the broken line L43, and the current becomes a recovery current.
In the storage drive 24, a similar situation to that in the storage drive 22 occurs, and in the storage drive 24, the current flowing through the path indicated by the broken line L41 becomes the recovery current.
Therefore, in the NVDFF circuit 11, although the recovery current conventionally flows only through the paths indicated by the broken lines L42 and L44, the recovery current flows through the paths indicated by the broken lines L41 and L43 in addition to these paths.
As a result, since the recovery current becomes larger as a whole, the time taken for the voltage levels of the storage node N11 and the storage node N12 to return to the state at the time of storage can be made shorter. In other words, since the short circuit used at the time of recovery is used for charging of the storage node, unnecessary power consumption can be reduced, and the recovery time can be shortened.
If the recovery is completed in the above manner, the above operations in the active mode, the storage mode, the sleep mode, and the recovery mode are then performed according to the input storage data.
As described above, according to the NVDFF circuit 11, miniaturization and low power consumption can be achieved while maintaining stable writing.
< second embodiment >
< example of configuration of NVDFF circuit >
Note that the above description has been given of an example in which the present technique is applied to the NVDFF circuit of the head-type SSR-NVFF circuitry, but the present technique may also be applied to the NVDFF circuit of the foot-type SSR-NVFF circuitry.
In this case, for example, the NVDFF circuit has a configuration as shown in fig. 4. Note that in fig. 4, portions corresponding to the case shown in fig. 1 are assigned the same reference numerals, and description thereof will be omitted as appropriate.
The NVDFF circuit 201 shown in fig. 4 is an NVDFF circuit of the foot SSR-NVFF circuitry.
For PG of the NVDFF circuit 201, an nMOS transistor (not shown) is used as the PS. Specifically, for example, if the PS is turned on, each component of the NVDFF circuit 201 is grounded via an nMOS transistor, and if the PS is turned off, each component of the NVDFF circuit 201 is separated from ground, thereby implementing PG.
The NVDFF circuit 201 includes a volatile storage unit 21, a storage driver 22, a transistor 23, a storage driver 24, a transistor 25, a transistor 211, a transistor 212, a nonvolatile storage unit 213, a control driver 29, an XNOR circuit 214, and a transistor 31.
The circuit configuration of the NVDFF circuit 201 is a configuration in which a transistor 211, a transistor 212, a nonvolatile memory section 213, and an XNOR circuit 214 are provided instead of the transistor 26, the transistor 27, the nonvolatile memory section 28, and the or circuit 30 in the NVDFF circuit 11.
Further, the nonvolatile memory portion 213 includes a memory element 221 and a memory element 222 each including MTJ or ReRAM. The following description is continued assuming that the storage element 221 and the storage element 222 are MTJs.
In the NVDFF circuit 201, the transistor 211 is disposed between the storage node N11 and the node N14, and the transistor 212 is disposed between the storage node N12 and the node N13. The transistor 211 and the transistor 212 are pMOS transistors, and a control signal SR1 is supplied to gates of the transistor 211 and the transistor 212.
Further, the fixed layer (p-layer) of the memory element 221 is connected to the control line L11, and the free layer (f-layer) of the memory element 221 is connected to the node N14. Further, the fixed layer of the storage element 222 is connected to the control line L11, and the free layer of the storage element 222 is connected to the node N13.
Also in the NVDFF circuit 201, all transistors on the storage path are drain connected, similar to the case of the NVDFF circuit 11.
In other words, the transistor 25 and the transistor 23 arranged on the memory path are drain-connected, in which the memory element 221 and the memory element 222 are connected to the drain side. In a similar manner, the transistor 31 arranged on the memory path is also a drain connection, wherein the memory element 221 and the memory element 222 are connected to the drain side.
Further, a control signal SR1 and a control signal SR2 are supplied to an input terminal of the XNOR circuit 214, and an output terminal of the XNOR circuit 214 is connected to the transistor 31.
< operation of NVDFF Circuit >
Next, the operation of the NVDFF circuit 201 shown in fig. 4 will be described.
In the active mode, the NVDFF circuit 201 performs operations similar to those of the NVDFF circuit 11 described above.
Further, in the storage mode, the control signal SR1 is set to the H level and the transistor 211 and the transistor 212 are brought into an off state, and the control signal SR2 is set to the H level and the transistor 23 and the transistor 25 are brought into an on state.
At this time, since the output of the XNOR circuit 214 to which the control signal SR1 and the control signal SR2 are supplied is set to the H level, the transistor 31 having the gate to which the H level is supplied enters the on state.
Further, for example, the control signal CTRL is set to an H level, thereafter the control signal CTRL is set to an L level, and the state of the storage node is stored into the nonvolatile storage section 213.
In other words, for example, it is assumed that the state of the storage node N11 is set to the L level, and the state of the storage node N12 is set to the H level.
In this state, the transistor 71 of the storage driver 22 is brought into an on state and the node N13 is set to the H level, and the transistor 82 of the storage driver 24 is brought into an on state and the node N14 is set to the L level.
At this time, if the control signal CTRL is set to the H level and the control line L11 is set to the L level, in the memory element 222, a storage current flows from the node N13 side to the control line L11 side, and the memory element 222 enters a low resistance state (P state). Therefore, the state of the voltage level of the storage node N11 is held (stored) as it is in the storage element 222 by the storage driver 22.
Further, if the control signal CTRL is set to the L level and the control line L11 is set to the H level, in the memory element 221, a storage current flows from the control line L11 side to the node N14 side, and the memory element 221 enters a high-resistance state (AP state). Therefore, the state of the voltage level of the storage node N12 is held (stored) as it is in the storage element 221 by the storage driver 24.
Also in the NVDFF circuit 201, there are no transistors arranged as a source connection on the storage path, and all transistors on the storage path are drain connected, similar to the case of the NVDFF circuit 11. In other words, the transistor 23, the transistor 25, and the transistor 31 are drain connected.
If the operation in the storage mode is ended and the mode is transited to the sleep mode, the PS (not shown) is turned off, thereby implementing the PG. Then, when the state is subsequently restored from the sleep state, the operation in the recovery mode is performed.
In the recovery mode, the control signal SR1 is set to the L level, and the transistor 211 and the transistor 212 are brought into the on state, and the control signal SR2 is set to the L level, and the transistor 23 and the transistor 25 are brought into the off state.
At this time, since the control signal SR1 is set to the L level and the control signal SR2 is set to the L level, the output of the XNOR circuit 214 is set to the H level, and the transistor 31 enters the on state.
Further, the control signal CTRL is set to the L level, the transistor 101 of the control driver 29 is brought into a conductive state, and the control line L11 is connected to the power supply. In other words, the control line L11 is set to the H level.
If the PS is turned on from this state, a recovery current flows.
Here, as described in the above example, it is assumed that the memory element 221 is in a high-resistance state (AP state), and the memory element 222 is in a low-resistance state (P state).
In the sleep state, because the current path to ground is blocked, the voltage at a certain node in the circuit rises due to leakage to a voltage close to the power supply voltage. If PS is turned on, the ground voltage is supplied to the slave latch 45. Therefore, the recovery current flows from the control line L11 to the slave latch 45 side through the storage element 221 and the storage element 222.
In this example, because the storage element 221 is in the high resistance state and the storage element 222 is in the low resistance state, if the recovery current flows, the voltage of the node N14 drops more than the voltage of the node N13 due to the resistance difference between the storage element 221 and the storage element 222.
Therefore, the decrease in conductance due to the decrease in source voltage is more significant in the transistor 211 than in the transistor 212. Therefore, the current flowing in the transistor 211 becomes smaller than the current flowing in the transistor 212 by an amount corresponding to or more than the resistance difference between the memory element 221 and the memory element 222.
As a result, the voltage of the storage node N11 drops more than the voltage of the storage node N12, positive feedback is performed by a loop including the inverter 61 and the inverter 62 in the slave latch 45, the storage node N12 has the power supply voltage (H level), and the storage node N11 is set to the ground level (L level). In other words, the state is restored to the same state as the state of the voltage levels of the storage node N11 and the storage node N12 at the time of storage.
In this case, similarly to the case of the NVDFF circuit 11, since the transistor 23 and the transistor 25 are in the off state, the recovery current does not flow from the transistor 23 and the transistor 25 to the ground, and unnecessary power consumption is suppressed.
If the restoration is completed, then operations in the active mode, the storage mode, the sleep mode, and the restoration mode are performed according to the input storage data.
Also in the NVDFF circuit 201 described above, similarly to the case of the NVDFF circuit 11, miniaturization and low power consumption can be achieved while maintaining stable writing.
As described above, according to the present technology, a compact nonvolatile memory circuit with low power consumption can be realized while maintaining stable writing.
Note that the embodiments of the present technology are not limited to the above-described embodiments, and various changes may be made without departing from the scope of the present technology.
Further, the present technology may adopt the following configuration.
(1) A non-volatile storage circuit, comprising:
a volatile storage section configured to store information; and
a nonvolatile storage section that writes information in the volatile storage section into the nonvolatile storage section by a storage operation and reads information from the nonvolatile storage section into the volatile storage section through a restoration operation through a restoration path different from a storage path at the time of the storage operation,
wherein all transistors arranged on the storage path are drain connected.
(2) The nonvolatile memory circuit according to (1), further comprising:
a storage driver disposed on the storage path and configured to write information into the nonvolatile storage section; and
and a first transistor disposed between the storage driver and ground.
(3) The nonvolatile memory circuit according to (2),
wherein the storage drive is an inverting element.
(4) The nonvolatile memory circuit according to (2) or (3),
wherein the first transistor is an nMOS transistor.
(5) The nonvolatile memory circuit according to any one of (2) to (4), further comprising
A control driver arranged on the storage path and configured to control a level of a control line connected to the nonvolatile storage section on a side opposite to a storage driver side.
(6) The nonvolatile memory circuit according to (5), further comprising
A second transistor disposed between the control driver and ground.
(7) The nonvolatile memory circuit according to (6),
wherein the control driver is an inverting element.
(8) The nonvolatile memory circuit according to (6) or (7),
wherein the second transistor is an nMOS transistor.
(9) The nonvolatile memory circuit according to any one of (2) to (8),
wherein the volatile storage section includes a first storage node and a second storage node,
the nonvolatile memory section includes a first memory element and a second memory element,
the first storage node and the first storage element are connected via a third transistor, an
The second storage node and the second storage element are connected via a fourth transistor.
(10) The nonvolatile memory circuit according to (9),
wherein the first storage node and the second storage element are connected via the storage driver; and
the second storage node and the first storage element are connected via another storage driver.
(11) The nonvolatile memory circuit according to (9) or (10),
wherein the first storage element and the second storage element are MTJs.
List of reference numerals
11 NVDFF circuit
21 volatile memory unit
22 storage drive
23 transistor
24 storage drive
25 transistor
28 nonvolatile memory section
29 control driver
30 OR circuit
31 transistor
91 memory element
92 memory element
Claims (11)
1. A non-volatile storage circuit, comprising:
a volatile storage section configured to store information; and
a nonvolatile storage section that writes information in the volatile storage section into the nonvolatile storage section by a storage operation and reads information from the nonvolatile storage section into the volatile storage section through a restoration operation through a restoration path different from a storage path at the time of the storage operation,
wherein all transistors arranged on the storage path are drain connected.
2. The non-volatile storage circuit of claim 1, further comprising:
a storage driver disposed on the storage path and configured to write information into the nonvolatile storage section; and
and a first transistor disposed between the storage driver and ground.
3. The non-volatile storage circuit of claim 2,
wherein the storage driver is an inverting element.
4. The non-volatile storage circuit of claim 2,
wherein the first transistor is an nMOS transistor.
5. The non-volatile storage circuit of claim 2, further comprising
A control driver arranged on the storage path and configured to control a level of a control line connected to the nonvolatile storage section on a side opposite to a storage driver side.
6. The non-volatile storage circuit of claim 5, further comprising
A second transistor disposed between the control driver and ground.
7. The non-volatile storage circuit of claim 6, wherein the control driver is an inverting element.
8. The non-volatile storage circuit of claim 6,
wherein the second transistor is an nMOS transistor.
9. The non-volatile storage circuit of claim 2,
wherein the volatile storage section includes a first storage node and a second storage node,
the nonvolatile memory section includes a first memory element and a second memory element,
the first storage node and the first storage element are connected via a third transistor, an
The second storage node and the second storage element are connected via a fourth transistor.
10. The non-volatile storage circuit of claim 9,
wherein the first storage node and the second storage element are connected via the storage driver; and
the second storage node and the first storage element are connected via another storage driver.
11. The non-volatile storage circuit of claim 9,
wherein the first storage element and the second storage element are MTJs.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201862659834P | 2018-04-19 | 2018-04-19 | |
| US62/659,834 | 2018-04-19 | ||
| PCT/JP2019/015073 WO2019203019A1 (en) | 2018-04-19 | 2019-04-05 | Non-volatile storage circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112020744A true CN112020744A (en) | 2020-12-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201980015138.XA Pending CN112020744A (en) | 2018-04-19 | 2019-04-05 | Nonvolatile memory circuit |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JP7282749B2 (en) |
| CN (1) | CN112020744A (en) |
| DE (1) | DE112019002007T5 (en) |
| TW (1) | TW201944412A (en) |
| WO (1) | WO2019203019A1 (en) |
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- 2019-04-05 JP JP2020514076A patent/JP7282749B2/en active Active
- 2019-04-05 WO PCT/JP2019/015073 patent/WO2019203019A1/en active Application Filing
- 2019-04-05 CN CN201980015138.XA patent/CN112020744A/en active Pending
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Also Published As
| Publication number | Publication date |
|---|---|
| JP7282749B2 (en) | 2023-05-29 |
| WO2019203019A1 (en) | 2019-10-24 |
| DE112019002007T5 (en) | 2021-01-21 |
| JPWO2019203019A1 (en) | 2021-04-30 |
| TW201944412A (en) | 2019-11-16 |
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