JP4322048B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including a write drive circuit capable of flowing a current bidirectionally to a bit line in order to write data in a memory cell.
[0002]
[Prior art]
In recent years, MRAM (Magnetic Random Access Memory) has attracted attention as a non-volatile storage device with low power consumption. The MRAM is a storage device that performs non-volatile data storage using a plurality of thin film magnetic bodies formed in a semiconductor integrated circuit and can randomly access each of the thin film magnetic bodies.
[0003]
In the MRAM, when data is written, a write driving circuit that operates by supplying a predetermined power supply voltage causes a current to flow in the direction corresponding to the write data in the selected bit line, and the unselected bit line is in a floating state. It is said. Then, when a predetermined amount of current flows through the selected bit line, the magnetization direction of a ferromagnetic layer called a free magnetic layer in the memory cell to be written with data changes. Then, data is stored in the memory cell in a nonvolatile manner by utilizing the change in the resistance value due to the change in the internal state.
[0004]
In order to write data in the MRAM, it is necessary to flow a current bidirectionally through the bit line as described above. Therefore, in the conventional MRAM, a write drive circuit composed of a P-channel MOS transistor and an N-channel MOS transistor is arranged on both sides of each bit line, and from one write drive circuit to the other in accordance with write data. Data is written to the memory cell by passing a current through the drive circuit.
[0005]
On the other hand, Japanese Patent Laid-Open No. 2002-197851 discloses that the potential of one end of the word line is fixed and the potential of the other end is changed in order to prevent the electromigration phenomenon occurring in the word line and bit line in the MRAM. In the bit line, a technique for preventing the electromigration phenomenon is disclosed by changing the potential at both ends or the potential at at least one end to flow a current in the reverse direction after data writing to the wiring. (See Patent Document 1).
[0006]
[Patent Document 1]
JP 2002-197851 A
[0007]
[Problems to be solved by the invention]
In recent years, there has been an increasing need for miniaturization of semiconductor memory devices against the background of the portability of electronic devices. As described above, in a semiconductor memory device in which data is written to a memory cell by flowing a current bidirectionally to a bit line, generally, a write drive circuit that is a current driver is provided for each bit line and on both sides thereof. Has been placed. For this reason, the occupation area of the write drive circuit is large, and the total number of wirings is large due to the large number of write drive circuits. Therefore, in such a semiconductor memory device represented by MRAM, reduction of the area of the write drive circuit and reduction of the number of devices itself have been problems.
[0008]
In addition, when data is written to the memory cell by passing a current through the bit line, the current driving capability of the write driving circuit must be sufficiently ensured, which is sufficient to reduce the current driving capability due to the reduction of the write driving circuit. It is necessary to keep in mind. Here, from the viewpoint of securing the current driving capability, a load resistor (a gate disposed downstream) connected to the bit line when a current flows through the bit line regardless of whether or not the write driving circuit is reduced. It is also necessary to consider the influence of the voltage drop generated in the transistor). That is, the voltage drop caused by the load resistance acts to reduce the source-drain voltage of the driver transistor that constitutes the write drive circuit, so that the current drive capability also decreases due to this influence. Therefore, in consideration of these, the current driving capability of the write driving circuit must be sufficiently ensured.
[0009]
Furthermore, against the background of energy saving in recent years, in semiconductor memory devices, in addition to miniaturization, low power consumption has become a major issue. The MRAM described in JP-A-2002-197851 described above is useful for preventing electromigration and improving operational stability. However, as described above, in recent years, the size of semiconductor memory devices has been further reduced. Therefore, there is a demand for a semiconductor memory device that realizes stable operation and low power consumption after downsizing the semiconductor memory device.
[0010]
Accordingly, the present invention has been made to solve such a problem, and an object of the present invention is to provide a semiconductor memory device that can reduce the area of the write drive circuit and realize downsizing of the device.
[0011]
Another object of the present invention is to provide a semiconductor memory device in which the area of a write drive circuit is reduced to reduce the size of the device and further prevent a decrease in current drive capability.
[0012]
Still another object of the present invention is to provide a semiconductor memory device that further reduces power consumption by reducing the area of the write drive circuit to reduce the size of the device.
[0013]
[Means for Solving the Problems]
According to the present invention, a semiconductor memory device is provided corresponding to a plurality of memory cells arranged in a matrix, a plurality of bit lines provided corresponding to columns of the plurality of memory cells, and a plurality of bit lines. Each connected to one end of the corresponding bit line , A current flows in the direction corresponding to the logic level of the write data to the corresponding bit line Multiple write drive circuits Are provided corresponding to a plurality of bit lines, each being provided between the other end of the corresponding bit line and a constant potential node to which a voltage of a predetermined potential is applied, and corresponding bit lines at the time of data writing A plurality of connection circuits for connecting the other end of the corresponding bit line and a constant potential node in response to activation of a write bit line selection signal for instructing selection And with , Each of the plurality of write drive circuits receives a voltage of a first potential higher than a predetermined potential and a voltage of a second potential lower than the predetermined potential, and when the write data is at the first logic level, When a current flows from one end of the corresponding bit line to the other end based on the potential difference between the first potential and the predetermined potential, and the write data is at the second logic level complementary to the first logic level, Based on the potential difference between the potential and the second potential, a current is passed from the other end of the corresponding bit line to one end.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.
[0015]
[Embodiment 1]
FIG. 1 is a circuit diagram showing a configuration of a write drive circuit according to the present invention. Referring to FIG. 1, write drive circuit 1 includes a node ND1, a current driver 2, a gate potential control circuit 4, a precharge circuit 6, a constant potential node 8, and a load circuit 10.
[0016]
Current driver 2 includes a P channel MOS transistor P101, an N channel MOS transistor N101, a power supply node Vcc, and a ground node GND. P-channel MOS transistor P101 is connected between power supply node Vcc and node ND1, and receives a control voltage from NAND gate G101 at its gate. N-channel MOS transistor N101 is connected between node ND1 and ground node GND, and receives a control voltage from AND gate G102 at its gate.
[0017]
The operation of the current driver 2 is controlled by the gate potential control circuit 4 and bidirectionally connected to the node ND1 based on the potential difference between the power supply node Vcc and the constant potential node 8 and the potential difference between the constant potential node 8 and the ground node GND. Current is passed through. The potential of power supply node Vcc to which P channel MOS transistor P101 is connected changes according to the operating state of write drive circuit 1, as will be described later.
[0018]
Gate potential control circuit 4 includes a NAND gate G101 and an AND gate G102. The NAND gate G101 calculates a logical product of at least one drive condition signal and outputs a signal obtained by inverting the calculation result. The AND gate G102 outputs a signal obtained by calculating a logical product of at least one driving condition signal.
[0019]
The gate potential control circuit 4 can control the operation of the current driver 2 in accordance with the drive condition signal to form a tri-state state. That is, gate potential control circuit 4 includes a first state in which a current flows from current driver 2 to node ND1 by turning on and off P channel MOS transistor P101 and N channel MOS transistor N101, and P channel MOS transistor P101 and The second state in which current flows from the node ND1 to the current driver 2 by turning off and turning on the N channel MOS transistor N101, and the node ND1 by turning off both the P channel MOS transistor P101 and the N channel MOS transistor N101. A third state in which no current flows can be formed.
[0020]
Gate potential control circuit 4 operates based on voltages supplied from a power supply node and a ground node (not shown). The voltage supplied to the gate potential control circuit 4 also changes according to the operating state of the write drive circuit 1 as will be described later.
[0021]
Precharge circuit 6 includes an N channel MOS transistor N102 and a power supply node Vpre. N channel MOS transistor N102 is connected between power supply node Vpre and node ND1, and receives precharge signal PRE at its gate.
[0022]
The precharge circuit 6 precharges the node ND1 to a predetermined voltage when no current is supplied to the node ND1 by the current driver 2, and when the current is supplied to the node ND1, the N channel MOS transistor N102 It is turned off and inactivated.
[0023]
Constant potential node 8 is a node having a fixed potential, and the potential is set to a potential between a power supply voltage applied to power supply node Vcc and a ground voltage applied to ground node GND.
[0024]
The load circuit 10 connected between the node ND1 and the constant potential node 8 corresponds to an equivalent resistance that adjusts the magnitude of the current flowing through the node ND1. Specifically, the load circuit 10 corresponds to a switch transistor for connecting / disconnecting the constant potential node 8 to / from the node ND1. When the load circuit 10 is in the OFF state, the load circuit 10 has an extremely high resistance, and almost no current flows between the node ND1 and the constant potential node 8. On the other hand, when the load circuit 10 is in the ON state, the load circuit 10 has a low resistance, and a potential difference between the potential on the current driver 2 side and the potential on the constant potential node 8 is between the node ND1 and the constant potential node 8. Current flows.
[0025]
The load circuit 10 is provided when the write drive circuit 1 is used in a semiconductor memory device, and when the data is read and when the node ND1 is precharged by the precharge circuit 6, the constant potential node 8 is connected to the node. This is because it is necessary to separate from ND1.
[0026]
In write drive circuit 1, the voltage arrangement of each power supply node changes depending on whether or not current driver 2 supplies current to node ND1. When the current driver 2 does not pass current, the voltage arrangement further changes depending on whether or not the write drive circuit 1 is on standby. Hereinafter, the time when the write drive circuit 1 is inactivated and the current driver 2 does not flow current is referred to as “standby”, the write drive circuit 1 is activated, and the current The time when the driver 2 does not pass current is referred to as “standby”, and the time when the current driver 2 passes current is referred to as “selected”.
[0027]
Next, features of the write drive circuit 1 will be described. A first feature of the write drive circuit 1 is that a current driver 2 that allows current to flow bidirectionally to the node ND1 is arranged only on one side of the node ND1, and the other end side of the node ND1 has a potential by a constant potential node 8. It is to be fixed. Then, by controlling ON / OFF of P-channel MOS transistor P101 and N-channel MOS transistor N101 constituting current driver 2, power supply node Vcc is changed to constant potential node 8 having a potential lower than that of power supply node Vcc. A current can flow in the direction from the current driver 2 to the load circuit 10, and the constant potential node 8 having a potential higher than the potential of the ground node GND is directed to the ground node GND, that is, the load circuit 10 is directed to the current driver 2. Current can flow in the direction.
[0028]
The second feature of the write drive circuit 1 is that the P-channel MOS transistor P101 and the N-channel MOS transistor N101 constituting the current driver 2 are normally used in a peripheral circuit system that operates at a lower voltage than the current drive system. That is, the transistor is formed of a transistor having a gate insulating film having a film thickness equivalent to the film thickness.
[0029]
In the following, a transistor having a gate insulating film having such a film thickness is referred to as a “thin film transistor”, whereas a transistor that has been used in a normal current drive system is also referred to as a “thick film transistor”. .
[0030]
The current driver 2 is formed of a thin film transistor because the current driver 2 that allows current to flow bidirectionally to the node ND1 is disposed on one side of the node ND1, and thus occurs at both ends of the node ND1 as compared with the case where the current driver is disposed on both sides. This is to prevent a decrease in current driving force due to a small potential difference.
[0031]
That is, when the current driver is arranged on both sides of the node, the potential difference between the power supply node Vcc and the ground node GND becomes the current driving force. However, in write drive circuit 1, the potential difference between power supply node Vcc and constant potential node 8 having a higher potential than ground node GND, or constant potential node 8 and ground node GND having a lower potential than power supply node Vcc, The current driving force is determined by this potential difference, and the potential difference for generating the current driving force is smaller than in the case of the both-side arrangement.
[0032]
Therefore, in this writing drive circuit 1, the current driving capability is ensured by using a thin film transistor having a large current driving capability as a transistor constituting the current driver. Note that the problem of the breakdown voltage and leakage current increase of the gate insulating film due to the use of the thin film transistor is solved by a fourth feature point described later.
[0033]
A third feature of write drive circuit 1 is that when write drive circuit 1 is activated, the potential of power supply node Vcc is boosted. When a current is flowing from the current driver 2 to the constant potential node 8, the potential of the node ND 1 rises higher than the potential of the constant potential node 8 due to the influence of the voltage drop generated in the load circuit 10. Therefore, the source-drain voltage of P channel MOS transistor P101 is further reduced, and the current driving capability of write driving circuit 1 is further reduced.
[0034]
Therefore, in this write drive circuit 1, the current driver 2 is formed of a thin film transistor, and further, when the write drive circuit 1 is activated, the potential of the power supply node Vcc is boosted to prevent a decrease in the current drive capability. Is planned.
[0035]
In addition, the operating potential of gate potential control circuit 4 is boosted as the potential of power supply node Vcc is boosted. As a result, the gate potential of P channel MOS transistor P101 is also boosted, and when P channel MOS transistor P101 is turned on with the potential of power supply node Vcc being boosted, an excessive amount is generated between the source and gate of P channel MOS transistor P101. The potential difference is relaxed. This ensures the reliability of the gate insulating film.
[0036]
In the above description, the case where current flows from the current driver 2 side toward the constant potential node 8 side has been described. However, the same applies when current flows from the constant potential node 8 side toward the current driver 2 side. Can think. That is, when a current flows from the constant potential node 8 side to the current driver 2 side, the potential of the ground node GND is changed to be lower than the ground level in accordance with the activation of the write drive circuit 1, and the N channel MOS By increasing the potential difference between the drain and source of the transistor N101, it is possible to prevent the current driving capability from being lowered.
[0037]
A fourth feature of the write drive circuit 1 is that the node ND1 is precharged by the precharge circuit 6 during standby or standby when no current is passed through the node ND1. Power supply node Vcc is boosted in advance during standby, which is a stage before selection, and the gate potential of P channel MOS transistor P101 is also boosted accordingly. However, when the potential of the drain portion (node ND1) is at the ground level, an excessive electric field is generated between the gate and the drain and between the source and the drain in the P-channel MOS transistor P101 formed of the thin film transistor, and the gate insulating film may be destroyed. There is.
[0038]
Therefore, by precharging node ND1 to a predetermined potential by precharge circuit 6, the potential difference between the gate and drain and the source and drain in P channel MOS transistor P101 is alleviated. Thereby, the reliability of the gate insulating film of P channel MOS transistor P101 is ensured.
[0039]
P channel MOS transistor P101 is formed of a thin film transistor whose leakage current is larger than that of a thick film transistor, but the potential difference between the source and drain of P channel MOS transistor P101 can be suppressed by precharging node ND1. Therefore, the leakage current in P channel MOS transistor P101 is also suppressed.
[0040]
FIG. 2 is a diagram showing an operating state during standby of the write drive circuit 1 shown in FIG. Referring to FIG. 2, during standby, P channel MOS transistor P101 and N channel MOS transistor N101, which are current drivers, are turned off. Then, N channel MOS transistor N102 is turned on, and node ND1 is precharged to a predetermined potential. The load circuit 10 is in an OFF state, that is, a state where it is not operating.
[0041]
FIG. 3 is a diagram showing a voltage arrangement in the standby state of write drive circuit 1 shown in FIG. Referring to FIG. 3, both NAND gate G101 and AND gate G102 operate by receiving a power supply voltage of 1.5V and a ground voltage of 0V. Thereby, gate potentials Vg of P channel MOS transistor P101 and N channel MOS transistor N101 are 1.5V and 0V, respectively. Further, voltages of 1.5 V and 0.6 V are applied to the power supply nodes Vcc and Vpre, respectively. Since N-channel MOS transistor N102 is turned on, the potential of node ND1 becomes 0.6V according to the potential of power supply node Vpre. Potential V of constant potential node 8 ₈ Is fixed at 1.2V regardless of standby, standby and selection.
[0042]
Thus, at the time of standby, the node ND1 is precharged to a predetermined potential. Therefore, even if the P-channel MOS transistor P101 is constituted by a thin film transistor having a leak current larger than that of the thick film transistor, the potential difference between the source and drain of the P-channel MOS transistor P101 is suppressed to a small value. Leakage current at P101 is suppressed.
[0043]
FIG. 4 is a diagram showing an operation state during standby of write drive circuit 1 shown in FIG. The operation state of the write drive circuit 1 during standby is the same as the operation state during standby shown in FIG.
[0044]
FIG. 5 is a diagram showing a voltage arrangement at the time of standby of write drive circuit 1 shown in FIG. Referring to FIG. 5, the potential of power supply node Vcc is boosted from 1.5V to 2.5V during standby. Accordingly, the operating potential of NAND gate G101 is also boosted, and NAND gate G101 operates by receiving a power supply voltage of 2.5V and a ground voltage of 1.0V. As a result, gate potential Vg of P channel MOS transistor P101 becomes 2.5V. A predetermined voltage is applied to power supply node Vpre so that the potential difference between the gate-drain and source-drain of P-channel MOS transistor P101 does not exceed the breakdown voltage of the gate insulating film of P-channel MOS transistor P101. Here, a voltage of 0.6 V is applied as in the standby mode, and the voltage level of the node ND1 is 0.6 V.
[0045]
Thus, the potential received by power supply node Vcc is boosted to 2.5V during standby. Here, since the node ND1 is also precharged to a predetermined potential, the potential difference between the source and drain of the P-channel MOS transistor P101 is suppressed to be lower than the withstand voltage of the P-channel MOS transistor P101. Therefore, even if P channel MOS transistor P101 is formed of a thin film transistor, the reliability of the gate insulating film of P channel MOS transistor P101 is ensured.
[0046]
FIG. 6 is a diagram showing a first operation state when the write drive circuit 1 shown in FIG. 1 is selected. This first operation state is a state in which a current flows from the current driver 2 side to the constant potential node 8 side.
[0047]
Referring to FIG. 6, in the first operation state, P channel MOS transistor P101 is turned on and N channel MOS transistors N101 and N102 are turned off. Load circuit 10 is in an ON state, that is, an operating state, and a current flows from power supply node Vcc to constant potential node 8 through P channel MOS transistor P101, node ND1, and load circuit 10.
[0048]
FIG. 7 is a diagram showing a voltage arrangement in the first operation state of write drive circuit 1 shown in FIG. Referring to FIG. 7, the voltage levels received by NAND gate G101 and AND gate G102 and power supply node Vcc in the first operation state are the same as in standby. The gate potential Vg of P-channel MOS transistor P101 is 1.0 V in accordance with the ground potential of NAND gate G101. Potential V of constant potential node 8 ₈ Is 1.2V, and the potential of the node ND1 is about 1.7V due to the influence of the voltage drop caused by the equivalent resistance of the load circuit 10.
[0049]
Thus, in the first operating state, the potential of the node ND1 is the potential V of the constant potential node 8 that is higher than the ground potential. ₈ However, since the potential of power supply node Vcc is boosted to 2.5V, a sufficient potential difference is generated between the source and drain of P channel MOS transistor P101. Therefore, P channel MOS transistor P101 can operate in a saturation region, and a predetermined current driving capability is ensured.
[0050]
In order to secure current driving capability, the potential of power supply node Vcc is boosted to 2.5V, but the gate potential Vg of P-channel MOS transistor P101 also rises to 1.0V according to the ground potential of NAND gate G101. Therefore, a potential difference of 1.5 V is generated between the source and gate of the P-channel MOS transistor P101. Therefore, even if P channel MOS transistor P101 is formed of a thin film transistor, the reliability of the gate insulating film of P channel MOS transistor P101 is ensured.
[0051]
FIG. 8 is a diagram showing a second operation state when write drive circuit 1 shown in FIG. 1 is selected. This second operating state is a state in which a current flows from the constant potential node 8 side to the current driver 2 side.
[0052]
Referring to FIG. 8, in the second operation state, N channel MOS transistor N101 is turned on, and P channel MOS transistor P101 and N channel MOS transistor N102 are turned off. Load circuit 10 is in an ON state, that is, an operating state, and a current flows from constant potential node 8 to ground node GND through load circuit 10, node ND1, and N-channel MOS transistor N101.
[0053]
FIG. 9 is a diagram showing a voltage arrangement in the second operation state of write drive circuit 1 shown in FIG. Referring to FIG. 9, the voltage levels received by NAND gate G101 and AND gate G102 and power supply node Vcc in the second operation state are the same as in the standby state and the first operation state. N channel MOS transistor N101 has a gate potential Vg of 1.5 V in accordance with the power supply potential of AND gate G101. Potential V of constant potential node 8 ₈ Is 1.2V, and the potential of the node ND1 is about 0.8V due to the influence of the voltage drop caused by the equivalent resistance of the load circuit 10.
[0054]
Thus, in the second operation state, the potential of the node ND1 is the potential V of the constant potential node 8 which is lower than the power supply node Vcc. ₈ However, since the N-channel MOS transistor N101 is formed of a thin film transistor, a predetermined current driving capability is ensured.
[0055]
In the above description, node ND1 is precharged to 0.6 V during standby, but the precharge potential may be set to 1.5 V in accordance with the gate potentials of power supply node Vcc and P channel MOS transistor P101. As a result, even if the P channel MOS transistor P101 is configured by a thin film transistor having a large leakage current, the voltage difference between the source, drain and gate of the P channel MOS transistor P101 becomes 0. Therefore, the leakage current in the P channel MOS transistor P101 Can be set to zero.
[0056]
In the standby mode, the leakage current of N channel MOS transistor N101 is also taken into consideration so that the precharge potential of node ND1 becomes an intermediate potential between the potential applied to power supply node Vcc and the potential applied to ground node GND. A precharge potential may be set to.
[0057]
Further, in standby, the precharge potential may be increased in accordance with the increase in the potential of power supply node Vcc in consideration of the breakdown voltage of P channel MOS transistor P101. For example, if the breakdown voltage of the gate insulating films of P-channel MOS transistor P101 and N-channel MOS transistor N101 is about 1.5V, the precharge potential during standby is raised to about 1.2V, thereby causing P-channel MOS transistor P101. Further, the potential difference between the gate and drain and the source and drain of N channel MOS transistor N101 can be suppressed to within 1.5V. Thereby, the reliability of the gate insulating film of P channel MOS transistor P101 is ensured.
[0058]
Further, in order to further increase the current driving capability of N channel MOS transistor N101, the ground node is within the breakdown voltage range of the gate insulating film of N channel MOS transistor N101 as the potential of power supply node Vcc is boosted. The potential of GND may be lowered.
[0059]
Furthermore, in the first operating state, the gate potential of N channel MOS transistor N101 may be raised within a range not exceeding the threshold value in consideration of the breakdown voltage of the gate insulating film of N channel MOS transistor N101. This is possible by raising the source potential of the AND gate G102 that controls the gate potential of the N-channel MOS transistor N101. Therefore, for example, if the breakdown voltage of the gate insulating film of N channel MOS transistor N101 is about 1.5V, the gate potential of N channel MOS transistor N101 is reduced by setting the gate potential of N channel MOS transistor N101 to about 0.5V. The voltage difference between the drains is suppressed within 1.5V.
[0060]
Further, in the second operation state, the operating potential of NAND gate G101 and the potential of power supply node Vcc may be set to standby values in consideration of the breakdown voltage of the gate insulating film of P channel MOS transistor P101. For example, if the breakdown voltage of the gate insulating film of P-channel MOS transistor P101 is about 1.5V, the gate potential of P-channel MOS transistor P101 and the potential of power supply node Vcc are set to 1.5V during standby, thereby The potential difference between the gate and drain of the MOS transistor and between the source and drain can be suppressed within 1.5V.
[0061]
As described above, according to the write drive circuit 1, since the current driver 2 is arranged only on one side of the node ND1, the area occupied by the write drive circuit 1 in the device on which the write drive circuit 1 is mounted is large. And can contribute to miniaturization of the device.
[0062]
Further, by arranging the write drive circuit 1 on one side, signals such as data information can be concentrated on one side of the node, and the control of the write drive circuit 1 is facilitated.
[0063]
Furthermore, since the current driver 2 is formed of a thin film transistor, it is possible to prevent a decrease in the current driving force and ensure a predetermined current driving force.
[0064]
In addition, since the bit line is precharged by the precharge circuit 6 during standby and standby, the reliability of the gate insulating film of the driver transistor constituting the current driver 2 is ensured. In addition, since the gate leakage current and the source-drain leakage current are also greatly reduced, low power consumption is achieved.
[0065]
Further, since each state at the time of standby, standby and selection can be established, the present invention can be applied to a write drive circuit of a semiconductor memory device which requires such a state.
[0066]
[Embodiment 2]
FIG. 10 is a schematic block diagram showing the overall configuration of the MRAM according to the present invention. Referring to FIG. 10, MRAM 100 performs random access in response to a control signal CMD and an address signal ADD from the outside, and is selected as a memory cell selected as a data read or data write target (hereinafter also referred to as “selected memory cell”). The input data DIN is written or the output data DOUT is read.
[0067]
The MRAM 100 includes a control circuit 105 that controls the overall operation of the MRAM 100 in response to a control signal CMD, and a memory array 110 that includes memory cells MC arranged in a matrix.
[0068]
In memory array 110, word lines WL and write digit lines WDL are arranged corresponding to rows of memory cells, and bit lines BL and source lines SL are arranged corresponding to columns of memory cells. FIG. 10 shows a typical arrangement of one memory cell MC and the corresponding word line WL, write digit line WDL, bit line BL and source line SL.
[0069]
The MRAM 100 executes a row selection circuit 120 for performing row selection according to the row address RA indicated by the address signal ADD, and executes a column selection in the memory array 110 based on the column address CA indicated by the address signal ADD. Column decoder 125, and read / write control circuits 130 and 135.
[0070]
Read / write control circuits 130 and 135 collectively represent a circuit group for performing a data read operation and a data write operation on memory cells MC arranged in memory array 110.
[0071]
Hereinafter, secondary high voltage states (for example, power supply voltage) and low voltage states (for example, ground voltage) such as signals, signal lines, and data are also referred to as “H level” and “L level”, respectively.
[0072]
Next, the structure of the memory cell in the MRAM will be described.
FIG. 11 is a schematic diagram showing the configuration of the memory cell of the MRAM. In the memory cell of the MRAM, a thin film magnetic body using a magnetic tunnel junction (MTJ) is used. Hereinafter, a memory cell having a magnetic tunnel junction is referred to as an “MTJ memory cell”.
[0073]
Referring to FIG. 11, the MTJ memory cell includes a tunnel magnetoresistive element TMR whose electric resistance changes according to the value (“1” or “0”) of magnetically written storage data, and access transistor ATR. Including. Access transistor ATR is connected in series with tunneling magneto-resistance element TMR between write bit line WBL and read bit line RBL.
[0074]
At the time of data writing, a data write current in a direction corresponding to the write data flows through write bit line WBL, and further a current also flows through write digit line WDL. Access transistor ATR is turned off. At the time of data reading, the word line WL is activated and the access transistor ATR is turned on. When access transistor ATR is turned on, tunneling magneto-resistance element TMR is electrically coupled between write bit line WBL set at ground voltage GND and read bit line RBL receiving the supply of data read current.
[0075]
FIG. 12 is a conceptual diagram illustrating a data write operation to the MTJ memory cell. Referring to FIG. 12, tunneling magneto-resistance element TMR corresponds to a ferromagnetic layer (hereinafter, also simply referred to as “fixed magnetization layer”) FL having a fixed constant magnetization direction and a magnetic field applied from the outside. A ferromagnetic layer (hereinafter also simply referred to as a “free magnetic layer”) VL that is magnetized in a certain direction. A tunnel barrier (tunnel film) TB formed of an insulator film is provided between the fixed magnetic layer FL and the free magnetic layer VL. Free magnetic layer VL is magnetized in the same direction as fixed magnetic layer FL or in the opposite direction (antiparallel direction) to fixed magnetic layer FL according to the value of data to be written. A magnetic tunnel junction is formed by these fixed magnetic layer FL, tunnel barrier TB, and free magnetic layer VL.
[0076]
The electric resistance of tunneling magneto-resistance element TMR changes according to the relative relationship between the magnetization directions of fixed magnetic layer FL and free magnetic layer VL. Specifically, the electric resistance of the tunnel magnetoresistive element TMR becomes the minimum value Rmin when the magnetization direction of the fixed magnetization layer FL and the magnetization direction of the free magnetization layer VL are parallel, and the magnetization directions of both are opposite directions ( In the case of anti-parallel direction, the maximum value Rmax is obtained.
[0077]
At the time of data writing, word line WL is inactivated and access transistor ATR is turned off. In this state, in each of write bit line WBL and write digit line WDL, a data write current for magnetizing free magnetic layer VL flows in a direction according to the logic level of the write data. Then, a magnetic field corresponding to the current direction is generated in each of write bit line WBL and write digit line WDL, and the sum of these magnetic fields is applied to free magnetic layer VL. The free magnetic layer VL is parallel or antiparallel (opposite direction) to the fixed magnetic layer FL along the easy axis direction along the fixed magnetization direction of the fixed magnetic layer FL by the generated magnetic field. Magnetized.
[0078]
In order to rewrite the storage data of the MTJ memory cell, that is, the magnetization direction of the tunnel magnetoresistive element TMR, it is necessary to pass a data write current of a predetermined level or more to both the write digit line WDL and the write bit line WBL. The magnetization direction once written in tunneling magneto-resistance element TMR, that is, the storage data of the MTJ memory cell is held in a nonvolatile manner until new data is written.
[0079]
FIG. 13 is a conceptual diagram illustrating a data read operation from the MTJ memory cell. Referring to FIG. 13, at the time of data reading, access transistor ATR is turned on in response to activation of word line WL. Write bit line WBL is set to ground voltage GND. Thereby, tunneling magneto-resistance element TMR is electrically coupled to read bit line RBL while being pulled down by ground voltage GND.
[0080]
In this state, if the read bit line RBL is pulled up with a predetermined voltage, the current path including the read bit line RBL and the tunnel magnetoresistive element TMR is changed according to the electric resistance of the tunnel magnetoresistive element TMR, that is, the MTJ memory cell. A memory cell current Icell corresponding to the value of the stored data passes. The memory data is read from the MTJ memory cell by comparing the memory cell current Icell with a predetermined reference current.
[0081]
Thus, tunnel magnetoresistive element TMR changes its electric resistance in accordance with the direction of magnetization that can be rewritten by the applied data write magnetic field, so that electric resistances Rmax and Rmin of tunnel magnetoresistive element TMR are set to the values of stored data. By associating with (“1” and “0”), data can be stored in a nonvolatile manner.
[0082]
FIG. 14 is a circuit diagram showing a configuration of a main part of MRAM 100 shown in FIG. Referring to FIG. 14, a plurality of MTJ memory cells MC and dummy MTJ memory cells DMC are arranged in memory arrays 110a and 110b, respectively. Each of MTJ memory cell MC and dummy MTJ memory cell DMC includes a tunnel magnetoresistive element TMR and an access transistor ATR arranged in series between corresponding bit line BL and source line SL. The dummy MTJ memory cell DMC is a memory cell for generating a reference current to be compared with the memory cell current Icell flowing in the MTJ memory cell MC to be read when reading data.
[0083]
Read / write control circuit 130 includes a plurality of N channel MOS transistors N 2 and N 3 provided corresponding to a plurality of bit lines BL, a constant potential node 216, a power supply node Vccd, and a node 218. Each of N channel MOS transistors N2 forms a connection circuit for connecting a corresponding bit line to constant potential node 216. Each of N channel MOS transistors N2 is connected between corresponding bit line BL and constant potential node 216, and receives a write bit line selection signal WACT (not shown) at its gate. A fixed voltage of 1.2 V is applied to constant potential node 216. When write bit line selection signal WACT is activated, each N-channel MOS transistor N2 connects corresponding bit line BL to constant potential node 216. Here, write bit line selection signal WACT is a signal for instructing activation of bit line BL at the time of data writing.
[0084]
Each of N channel MOS transistors N3, together with power supply node Vccd, constitutes a precharge circuit for precharging corresponding bit line BL to a predetermined voltage. Each N channel MOS transistor N3 is connected between a corresponding bit line BL and a node 218 connected to power supply node Vccd, and receives an inverted signal / WACT (not shown) of write bit line selection signal WACT at its gate. . A voltage of 0.6 V is applied to power supply node Vccd. Each N channel MOS transistor N3 connects the corresponding bit line to the power supply node Vccd while the inversion signal / WACT is activated (while the write bit line selection signal WACT is deactivated). Connected to the node 218, the bit line BL is precharged to a potential of 0.6V.
[0085]
Read / write control circuit 130 includes a read column line RCSL, read selection gates RSG1 and RSG2, a data line pair DIO, sense amplifiers 202 to 206, a latch circuit 208, and an output buffer 210. These will be described in detail in the description of the operation of the MRAM 100 to be performed later.
[0086]
Read / write control circuit 135 includes a plurality of P-channel MOS transistors P1 and N-channel MOS transistors N1 and a plurality of write driver decoders BLDK provided corresponding to a plurality of bit lines BL, selector SEL1, power supply node Vcca, Vccb, N channel MOS transistor N52, and node 214 are included.
[0087]
P-channel MOS transistor P1 and N-channel MOS transistor N1 and write driver decoder BLDK provided for each bit line constitute a write drive circuit for supplying a data write current to the corresponding bit line BL. Each of P channel MOS transistor P1 and N channel MOS transistor N1 is formed of a thin film transistor. Each P-channel MOS transistor P1 is connected between a node 214 connected to the selector SEL1 and the corresponding bit line BL, and receives at its gate a control voltage from the corresponding write driver decoder BLDK. Each N-channel MOS transistor N1 is connected between the corresponding bit line BL and the ground node, and receives a control voltage from the corresponding write driver decoder BLDK at its gate.
[0088]
The P-channel MOS transistor P1 and the N-channel MOS transistor N1 that are current drivers constitute a current driver, and the write driver decoder BLDK is a control circuit that controls the operations of the P-channel MOS transistor P1 and the N-channel MOS transistor N1. Configure.
[0089]
Selector SEL1, power supply nodes Vcca and Vccb, and N channel MOS transistor N52 constitute a voltage supply circuit that supplies a voltage to a current driver formed of P channel MOS transistor P1 and N channel MOS transistor N1. Selector SEL1 is connected between power supply node Vcca and N-channel MOS transistor N52 and node 214.
[0090]
Voltages of 2.5 V and 1.5 V are applied to power supply nodes Vcca and Vccb, respectively. Selector SEL1 receives a voltage from power supply node Vcca and power supply node Vccb via N channel MOS transistor N52, selects power supply node Vcca during the active period (during standby and selection), and inactive period (during standby) ) Selects the power supply node Vccb and supplies a voltage to the node 214. N channel MOS transistor N52 connected between power supply node Vccb and selector SEL1 further reduces the voltage level of node 214 from 1.5V when power supply node Vccb is selected during the inactive period by selector SEL1. This is provided to reduce the leakage current between the source and drain in the P channel MOS transistor P1.
[0091]
Next, a data write operation and a read operation in MRAM 100 will be described. The data write operation will be described later with reference to FIG. 15 and thereafter, and first, the data read operation will be described.
[0092]
At the time of data reading, both N channel MOS transistors N2 and N3 are turned off. When data is read from the MTJ memory cell MC surrounded by the dotted line, the word line driver 120a activates the word line WL to which the MTJ memory cell MC is connected. At the same time, the dummy word line DWL to which the dummy MTJ memory cell DMC surrounded by the dotted line is connected is activated by the word line driver 120a. When the read column line RCSL is activated by a column decoder (not shown), the read selection gates RSG1 and RSG2 are turned ON, and the bit line connected to the selected bit line and the dummy MTJ memory cell DMC is read read gate RSG1. , RSG2 to be connected to the data line pair DIO.
[0093]
Then, a read current flows from data line pair DIO to target MTJ memory cell MC and dummy MTJ memory cell DMC, and voltages corresponding to the resistance values of MTJ memory cell MC and dummy MTJ memory cell DMC are generated at nodes ND101 and ND102. . The voltage difference between the nodes ND101 and ND102 is detected by the sense amplifiers 202 to 206, and the data stored in the MTJ memory cell MC is read to the data input / output terminal 212 via the latch circuit 208 and the output buffer 210. .
[0094]
Next, a case where data is written to the MTJ memory cell MC in the MRAM 100 will be described.
[0095]
FIG. 15 is a circuit diagram showing a configuration of a write drive circuit in MRAM 100 according to the second embodiment. FIG. 15 shows in detail the extracted part of the write drive circuit in the configuration of the MRAM 100 shown in FIG. The description overlapping with the description in FIG. 14 will not be repeated.
[0096]
Referring to FIG. 15, the write driver decoder BLDK includes a NAND gate G1 and an AND gate G2. NAND gate G1 operates by receiving a voltage supply from nodes 214 and 220. NAND gate G1 calculates a logical product of decode signal DKS received from column decoder 125 (not shown) and write bit line selection signal WACT received from control circuit 105 (not shown), and outputs a signal obtained by inverting the calculation result. The AND gate G2 outputs a signal obtained by calculating a logical product of the decode signal DKS and the write bit line selection signal WACT.
[0097]
N channel MOS transistor N2 provided between bit line BL and constant potential node 216 receives write bit line selection signal WACT at its gate. N channel MOS transistor N3 constituting a precharge circuit for precharging bit line BL is connected between power supply node Vccd and bit line BL, and receives an inverted signal / WACT of write bit line selection signal WACT at its gate.
[0098]
A circuit group including a current driver constituted by the P-channel MOS transistor P1 and N-channel MOS transistor N1 and the write driver decoder BLDK, N-channel MOS transistors N2 and N3, and a bit line BL corresponding thereto. Are repeatedly arranged corresponding to the plurality of bit lines BL.
[0099]
The selector SEL1 includes a P channel MOS transistor P60 and an N channel MOS transistor N60. The MRAM 100 further includes a selector SEL2 not shown in FIG. The selector SEL2 includes a P channel MOS transistor P62 and an N channel MOS transistor N62. The selectors SEL1 and SEL2 are shared in the circuit group.
[0100]
P-channel MOS transistor P60 and N-channel MOS transistors N60 and N52 are formed of thick film transistors that ensure the reliability of the gate insulating film even when a voltage of about 2.5 V is applied between the terminals. P channel MOS transistor P60 is connected between power supply node Vcca and node 214, and receives chip activation signal / ACT at its gate. N channel MOS transistor N60 is connected between N channel MOS transistor N52 and node 214, and receives chip activation signal / ACT at its gate.
[0101]
P channel MOS transistor P62 and N channel MOS transistor N62 are connected in parallel between node 214 and the ground node, and receive chip activation signal / ACT at its gate. Here, the P channel MOS transistor P62 is designed to have a threshold voltage of about 1.0V.
[0102]
In MRAM 100, during standby, chip activation signal / ACT and write bit line selection signal WACT are at H level and L level, respectively, P channel MOS transistor P1 and N channel MOS transistors N1 and N2 are turned off, and N The channel MOS transistor N3 is turned on. Therefore, bit line BL is precharged to a predetermined potential by power supply node Vccd and N channel MOS transistor N3. In selector SEL1, N channel MOS transistor N60 is turned on, and power supply node Vccb is selected. In selector SEL2, N channel MOS transistor N62 is turned on, and the voltage level of node 220 is at the ground level.
[0103]
When chip activation signal / ACT becomes L level and the memory array is activated, P channel MOS transistor P60 is turned on in selector SEL1, power supply node Vcca is selected, and the potential of node 214 rises to 2.5V. . Further, in the selector SEL2, the P channel MOS transistor P62 is turned ON. Here, as described above, since the threshold value of P channel MOS transistor P62 is designed to be 1.0V, when P channel MOS transistor P62 is turned ON, the potential of node 220 is clamped to 1.0V. .
[0104]
The state in which the memory array is activated and the bit line is not driven is referred to as a “standby state” in correspondence with the description given in the first embodiment.
[0105]
Then, when data of H level (“1”) is written into the selected MTJ memory cell MC after the memory array is activated, the write bit line selection signal WACT of the corresponding bit line becomes H level. N channel MOS transistor N2 provided between bit line BL and constant potential node 216 is turned on, and P channel MOS transistor P1 and N channel MOS transistor N1 are turned on and off by write driver decoder BLDK, respectively. Then, data write current + Iw flows in the direction from P channel MOS transistor P1 to constant potential node 216 via N channel MOS transistor N2.
[0106]
On the contrary, when L level (“0”) data is written to the MTJ memory cell MC, the P channel MOS transistor P1 and the N channel MOS transistor N1 are turned OFF and ON by the write driver decoder BLDK, respectively. Then, data write current -Iw flows in the direction from constant potential node 216 to N channel MOS transistor N1 via N channel MOS transistor N2.
[0107]
In this state, the write digit line driver 120b (not shown) activates the write digit line WDL to which the MTJ memory cell MC to be written is connected, and the bit line BL and the write digit line WDL through which the data write current flows are connected. Write data corresponding to the direction of the data write current is magnetically written into the MTJ memory cell MC arranged at the intersection.
[0108]
The state in which the data write current flows through the bit line BL is referred to as a “selected state” in correspondence with the description given in the first embodiment, and the data write currents + Iw and −Iw flow through the bit line BL. These states are referred to as “first operation state” and “second operation state”, respectively.
[0109]
16 to 24 are diagrams for explaining voltage arrangements during standby, standby, and selection of the write drive circuit shown in FIG.
[0110]
FIG. 16 is a circuit diagram schematically showing the configuration of the main part in order to explain the voltage arrangement in each write drive circuit shown in FIG. Referring to FIG. 16, voltage V1 corresponds to the voltage at node 214 shown in FIG.
[0111]
FIG. 17 is a diagram showing an operation state during standby of the write drive circuit shown in FIG. Referring to FIG. 17, at the time of standby, P channel MOS transistor P1 and N channel MOS transistor N1 which are current drivers are both turned OFF, and N channel MOS transistors N2 and N3 are turned OFF and ON, respectively.
[0112]
FIG. 18 is a diagram illustrating an example of a voltage arrangement in the standby state illustrated in FIG. Referring to FIG. 18, in the standby state, both NAND gate G1 and AND gate G2 operate by receiving a power supply voltage of 1.5V and a ground voltage of 0V. Voltages of 1.5V and 0.6V are applied to power supply nodes V1 and Vccd, respectively. Potential V of constant potential node 216 ₂₁₆ Is fixed at 1.2V regardless of standby, standby and selection.
[0113]
P channel MOS transistor P1 and N channel MOS transistor N1 are both OFF, and their gate potentials Vg are 1.5 V and 0 V, respectively, based on the operating voltages of NAND gate G1 and AND gate G2. Further, the potential VBL of the bit line BL is 0.6 V according to the potential of the power supply node Vccd.
[0114]
In this manner, the bit line BL is precharged to a predetermined potential during standby. Therefore, even if the P-channel MOS transistor P1 is composed of a thin film transistor having a leakage current larger than that of the thick film transistor, the potential difference between the source and drain of the P-channel MOS transistor P1 is suppressed to a small value. Leakage current at P1 is suppressed.
[0115]
FIG. 19 is a diagram showing an operation state during standby of the write drive circuit shown in FIG. Referring to FIG. 19, the operation state of the write drive circuit during standby is the same as the operation state during standby shown in FIG.
[0116]
FIG. 20 is a diagram showing an example of voltage arrangement in the standby state shown in FIG. Referring to FIG. 20, during standby, power supply node Vcca is selected by selector SEL1 shown in FIG. 15, so that voltage V1 is 2.5V. Further, the potential of the node 220 is 1.0V by the selector SEL2 shown in FIG. 15, and the NAND gate G1 operates by receiving a power supply voltage of 2.5V and a ground voltage of 1.0V. The AND gate G2 operates by receiving a power supply voltage of 1.5 V and a ground voltage of 0 V, as in the standby mode. The power supply node Vccd and the constant voltage node 216 are applied with voltages of 0.6 V and 1.2 V, respectively, as in the standby mode.
[0117]
P channel MOS transistor P1 and N channel MOS transistor N1 are both OFF, and their gate potentials Vg are 2.5 V and 0 V, respectively, based on the operating voltages of NAND gate G1 and AND gate G2. Further, the potential VBL of the bit line BL is 0.6 V according to the potential of the power supply node Vccd.
[0118]
Thus, at the time of standby, the potential of power supply node V1 and the gate potential of P channel MOS transistor P1 both rise to 2.5V. Here, since bit line BL is also precharged to 0.6 V, the potential difference between the gate and drain of P channel MOS transistor P1 and between the source and drain is alleviated, and the breakdown voltage of the gate insulating film of P channel MOS transistor P1 is reduced. Is kept lower. Therefore, the reliability of the gate insulating film of the P-channel MOS transistor P1 composed of thin film transistors is ensured.
[0119]
Further, the relaxation of the potential difference between the source and drain of the P channel MOS transistor P1 reduces the leakage current in the P channel MOS transistor P1.
[0120]
FIG. 21 is a diagram showing a first operation state when the write drive circuit shown in FIG. 16 is selected. Referring to FIG. 21, in the first operation state, P channel MOS transistor P1 and N channel MOS transistor N1 are turned on and off, respectively, and N channel MOS transistor N2 is turned on. N-channel MOS transistor N3 is turned off.
[0121]
FIG. 22 is a diagram showing an example of voltage arrangement in the first operation state shown in FIG. Referring to FIG. 22, the voltage received by NAND gate G1 and AND gate G2 in the first operation state and the voltage applied to power supply node V1 are the same as in the standby mode. The gate potential of P channel MOS transistor P1 is 1.0 V in accordance with the ground potential of NAND gate G1. Potential V of constant potential node 216 ₂₁₆ Is 1.2V, and the potential VBL of the bit line BL becomes about 1.7V due to the influence of the voltage drop generated in the N-channel MOS transistor N2.
[0122]
Thus, in the first operation state, the potential VBL of the bit line BL is equal to the potential V of the constant potential node 216 whose potential is higher than the ground potential. ₂₁₆ However, since the source potential of the P-channel MOS transistor P1 is boosted to 2.5V, a sufficient potential difference is generated between the source and drain of the P-channel MOS transistor P1. Further, the P-channel MOS transistor P1 is composed of a thin film transistor having a large current driving capability. Therefore, the current driving capability of P channel MOS transistor P1 is ensured.
[0123]
When the potential of power supply node V1 rises to 2.5V, gate potential Vg of P channel MOS transistor P1 rises to 1.0V in accordance with the ground potential of NAND gate G1, so that the source in P channel MOS transistor P1 -The voltage difference between the gates is relaxed. Therefore, even if P channel MOS transistor P1 is formed of a thin film transistor, the reliability of the gate insulating film of P channel MOS transistor P1 is ensured.
[0124]
FIG. 23 is a diagram showing a second operation state when the write driving circuit shown in FIG. 16 is selected. Referring to FIG. 23, in the second operation state, P channel MOS transistor P1 and N channel MOS transistor N1 are turned OFF and ON, respectively, and N channel MOS transistor N2 is turned ON. N-channel MOS transistor N3 is turned off.
[0125]
FIG. 24 is a diagram showing an example of voltage arrangement in the second operation state shown in FIG. Referring to FIG. 24, the voltages received by NAND gate G1 and AND gate G2 in the second operation state, and the voltage applied to power supply node V1 are the same as in the standby state. Potential V of constant potential node 216 ₂₁₆ Is 1.2V, and the potential VBL of the bit line BL becomes about 0.8V due to the influence of the voltage drop generated in the N-channel MOS transistor N2.
[0126]
Thus, in the second operation state, the potential VBL of the bit line BL is the potential V of the constant potential node 216 whose potential is lower than that of the power supply node V1. ₂₁₆ However, since the N channel MOS transistor N1 is formed of a thin film transistor, its current driving capability is ensured.
[0127]
In the above description, bit line BL is precharged to 0.6 V during standby, but the potential of power supply node Vccd may be set to 1.5 V in accordance with the gate potentials of power supply node V1 and P channel MOS transistor P1. Good. Thereby, in the standby state, the precharge potential of the bit line BL becomes 1.5 V, and even if the P channel MOS transistor P1 is configured by a thin film transistor in which the leak current becomes large, between the source, drain and gate of the P channel MOS transistor P1 Since the potential difference is 0, the leakage current can be reduced to 0 in the P-channel MOS transistor P1.
[0128]
In standby mode, the precharge potential of bit line BL becomes an intermediate potential between the potential applied to power supply node V1 and the potential applied to ground node GND in consideration of the leakage current of N channel MOS transistor N1. In this way, the precharge potential may be set.
[0129]
Further, in standby, the precharge potential may be raised in accordance with the rise in the potential of power supply node V1 in consideration of the breakdown voltage of the gate insulating film of P channel MOS transistor P1. For example, if the withstand voltage of P channel MOS transistor P1 and N channel MOS transistor N1 is about 1.5V, the precharge potential during standby is raised to about 1.2V, so that P channel MOS transistor P1 and N channel MOS transistor The potential difference between the gate and drain of the transistor N1 and between the source and drain is suppressed within 1.5V. Thereby, the reliability of the gate insulating film of P channel MOS transistor P1 is ensured.
[0130]
Further, in order to further increase the current driving capability of N channel MOS transistor N1, the potential of power supply node V1 is boosted and the potential of ground node GND to which N channel MOS transistor N1 is connected is set to N channel MOS transistor. It may be made lower than the ground potential within the range of the breakdown voltage of N1. In this case, a ground potential and a potential lower than the ground potential are selected for ground node GND in the same manner as a voltage supply circuit including selector SEL1, power supply nodes Vcca and Vccb and N-channel MOS transistor N52 that supplies a voltage to power supply node V1. A voltage supply circuit may be provided. In this case, this voltage supply circuit constitutes another voltage supply circuit.
[0131]
Furthermore, in the first operation state, the gate potential of N channel MOS transistor N1 may be raised within a range not exceeding the threshold value in consideration of the breakdown voltage of the gate insulating film of N channel MOS transistor N1. This is possible by raising the source potential of the AND gate G2 that controls the gate potential of the N-channel MOS transistor N1. Therefore, for example, if the breakdown voltage of N channel MOS transistor N1 is about 1.5V, the potential difference between the gate and drain of N channel MOS transistor N1 is set by setting the gate potential of N channel MOS transistor N1 to about 0.5V. Is suppressed within 1.5V.
[0132]
Further, in the second operation state, the operating potential of NAND gate G1 and the potential of power supply node V1 may be set to standby values in consideration of the breakdown voltage of P channel MOS transistor P1. For example, if the breakdown voltage of P channel MOS transistor P1 is about 1.5V, the gate potential of P channel MOS transistor P1 is set to 1.5V during standby by setting the gate potential of P channel MOS transistor P1 and the potential of power supply node V1 to 1.5V. The potential difference between the drain and the source-drain is suppressed within 1.5V.
[0133]
As described above, according to the MRAM 100 according to the second embodiment, since the write drive circuit is arranged only on one side of the bit line BL, the area occupied by the write drive circuit is greatly reduced, and the MRAM can be reduced in size. Can be realized.
[0134]
Further, since the driver transistor of the write drive circuit is formed of a thin film transistor, the current drive capability of the write drive circuit can be ensured.
[0135]
Further, since the bit line is precharged by the precharge circuit during standby and standby, the reliability of the gate insulating film of the driver transistor constituting the current driver is ensured. In addition, the gate leakage current and the source-drain leakage current can be greatly reduced.
[0136]
[Embodiment 3]
In the second embodiment, as shown in FIG. 15, each write driver decoder is arranged on the same side as the write driver decoder of the adjacent bit line with respect to the bit line. In the third embodiment, write driver decoders are alternately arranged on the left and right for each bit line.
[0137]
The overall configuration of the MRAM according to the third embodiment is the same as the overall configuration of the MRAM shown in FIG. 10, and description thereof will not be repeated.
[0138]
FIG. 25 is a circuit diagram showing a configuration of a write drive circuit in the MRAM according to the third embodiment. FIG. 25 is a diagram corresponding to FIG. 15 in the second embodiment, and similarly to FIG. 15, only a portion related to four adjacent bit lines among a plurality of bit lines is shown. The description of the same parts as those of the write drive circuit shown in FIG. 15 will not be repeated.
[0139]
Referring to FIG. 25, corresponding to bit line BLa, P channel MOS transistor P11 and N channel MOS transistor N11 forming a current driver, and NAND gate G11 and AND gate G21 forming write driver decoder BLDK1 Arranged on the first side of line BLa (left side of bit line BLa in FIG. 25). On the other hand, N channel MOS transistor N21 and N channel MOS transistor N31 constituting the precharge circuit are arranged on the second side of bit line BLa (the right side of bit line BLa in FIG. 25).
[0140]
In bit line BLb adjacent to bit line BLa, P channel MOS transistor P12 and N channel MOS transistor N12 constituting the current driver, and NAND gate G12 and AND gate G22 constituting write driver decoder BLDK2 are connected to bit line BLb. N channel MOS transistor N22 arranged on the second side and N channel MOS transistor N32 constituting the precharge circuit is arranged on the first side of bit line BLb.
[0141]
Similarly for the following bit lines, current drivers are alternately arranged on the left and right with respect to adjacent bit lines, and a write driver decoder, a precharge circuit, and a constant potential node are arranged corresponding to the current drivers.
[0142]
The current driver and the write driver decoder arranged on the first side of the corresponding bit line are supplied with voltages from the selectors SEL1 and SEL2, and the current driver and the write driver decoder arranged on the second side of the corresponding bit line The write driver decoder receives a voltage from selectors SEL3 and SEL4 having the same functions as selectors SEL1 and SEL2, respectively.
[0143]
It should be noted that the current driver and the write driver decoder arranged on the second side of the bit line are not separately provided with the selectors SEL3 and SEL4, and the current driver arranged on the second side of the bit line from the selectors SEL1 and SEL2 A configuration may be adopted in which wiring is provided to the write driver decoder to supply a voltage.
[0144]
As described above, according to the MRAM according to the third embodiment, the arrangement of the current drivers is arranged alternately on the left and right for the adjacent bit lines, thereby eliminating the complexity of the layout and improving the flexibility of layout design. To do.
[0145]
In each of the above embodiments, the transistors constituting the precharge circuit are N-channel MOS transistors, but may be constituted by P-channel MOS transistors. In the above, the N-channel MOS transistor is used because the precharge potential (0.6 V) is close to the threshold voltage of the P-channel MOS transistor. This is because there is a possibility that the line cannot be precharged.
[0146]
However, when it is necessary to increase the precharge potential due to the breakdown voltage of the current driver, the N-channel MOS transistor has a higher ON resistance. In this case, it is preferable to use the P-channel MOS transistor. desirable. When a P channel MOS transistor is used, the inverted signal / PRE of precharge signal PRE is received at the gate.
[0147]
In each of the above embodiments, the precharge potential is supplied by the precharge circuit. However, the bit line may be precharged using a constant potential node without providing a separate precharge circuit. That is, except when data is read, when the N channel MOS transistor that connects the bit line to the constant potential node is always ON, and all the driver transistors that constitute the current driver are OFF, the bit line is connected from the constant potential node. When one of the driver transistors is turned on by being precharged, the above function as the constant potential node may be achieved.
[0148]
The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiment but by the scope of claims for patent, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims for patent.
[0149]
【The invention's effect】
According to the present invention, since the write drive circuit that allows current to flow in the bit line bidirectionally is disposed only on one side of the bit line, the area occupied by the write drive circuit is greatly reduced. As a result, the semiconductor memory device Can be miniaturized.
[0150]
Further, by arranging the write drive circuit on one side, signals such as bit line selection information and data information can be concentrated on one side of the bit line, and the write drive circuit can be easily controlled.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a write drive circuit according to the present invention.
FIG. 2 is a diagram showing an operation state during standby of the write drive circuit shown in FIG. 1;
FIG. 3 is a diagram showing a voltage arrangement during standby of the write drive circuit shown in FIG. 1;
4 is a diagram showing an operation state during standby of the write drive circuit shown in FIG. 1; FIG.
FIG. 5 is a diagram showing a voltage arrangement during standby of the write drive circuit shown in FIG. 1;
6 is a diagram showing a first operation state when the write drive circuit shown in FIG. 1 is selected. FIG.
7 is a diagram showing a voltage arrangement in the first operation state of the write drive circuit shown in FIG. 1; FIG.
FIG. 8 is a diagram showing a second operation state when the write drive circuit shown in FIG. 1 is selected.
FIG. 9 is a diagram showing a voltage arrangement in the second operation state of the write drive circuit shown in FIG. 1;
FIG. 10 is a schematic block diagram showing an overall configuration of an MRAM according to the present invention.
FIG. 11 is a schematic diagram showing a configuration of an MRAM memory cell;
FIG. 12 is a conceptual diagram illustrating a data write operation to an MTJ memory cell.
FIG. 13 is a conceptual diagram illustrating a data read operation from an MTJ memory cell.
14 is a circuit diagram showing a configuration of a main part of the MRAM shown in FIG.
FIG. 15 is a circuit diagram showing a configuration of a write drive circuit in the MRAM according to the second embodiment;
16 is a circuit diagram schematically showing a configuration of a main part for explaining a voltage arrangement in each write drive circuit shown in FIG. 15;
17 is a diagram showing an operating state during standby of the write drive circuit shown in FIG. 16;
18 is a diagram showing an example of a voltage arrangement in the standby state shown in FIG.
FIG. 19 is a diagram showing an operation state at the time of standby of the write drive circuit shown in FIG. 16;
20 is a diagram showing an example of voltage arrangement in the standby state shown in FIG.
FIG. 21 is a diagram showing a first operation state when the write driving circuit shown in FIG. 16 is selected.
22 is a diagram showing an example of voltage arrangement in the first operating state shown in FIG. 21. FIG.
FIG. 23 is a diagram showing a second operation state when the write drive circuit shown in FIG. 16 is selected.
24 is a diagram showing an example of voltage arrangement in the second operation state shown in FIG. 23. FIG.
FIG. 25 is a circuit diagram showing a configuration of a write drive circuit in the MRAM according to the third embodiment.
[Explanation of symbols]
1 write drive circuit, 2 current driver, 4 gate potential control circuit, 6 precharge circuit, 8,216 constant potential node, 10 load circuit, 100 MRAM, 105 control circuit, 110 memory array, 120 row selection circuit, 120a word Line decoder, 120b write digit line decoder, 125 column decoder, 130, 135 read / write control circuit, 202-206 sense amplifier, 208 latch circuit, 210 output buffer, 212 data input / output terminal, ATR access transistor, BL, BLa BLb bit line, BLDK, BLDK1, BLDK2 write driver decoder, DIO data line pair, DWL dummy word line, DWDL dummy write digit line, FL pinned magnetization layer, G1, G101 NAND gate, G2, G102 AND , GND ground node, MC MTJ memory cell, ND1, ND101, ND102 node, RCSL read column selection line, RBL read bit line, RSG1, RSG2 read selection gate, SEL1 to SEL4 selector, SL source line, TB tunnel barrier, TMR tunnel magnetoresistive element, Vcc, Vcca to Vccd, Vpre power supply node, VL free magnetic layer, WACT write bit line selection signal, WBL write bit line, WDL write digit line, WL word line.

Claims (10)

A plurality of memory cells arranged in a matrix;
A plurality of bit lines provided corresponding to the columns of the plurality of memory cells;
A plurality of write drive circuits provided corresponding to the plurality of bit lines, each connected to one end of the corresponding bit line, and causing a current to flow in the direction corresponding to the logic level of the write data to the corresponding bit line When,
Provided corresponding to the plurality of bit lines, each provided between the other end of the corresponding bit line and a constant potential node to which a voltage of a predetermined potential is applied. A plurality of connection circuits for connecting the other end of the corresponding bit line and the constant potential node in response to activation of a write bit line selection signal for instructing line selection ;
Each of the previous SL plurality of write drive circuit receives the voltage and voltage of the predetermined second potential lower than the potential of the high first potential than the predetermined potential, the write data is a first logic In the case of level, a current is passed from the one end to the other end of the corresponding bit line based on the potential difference between the first potential and the predetermined potential, and the write data is complementary to the first logic level. A semiconductor memory device that causes a current to flow from the other end of the corresponding bit line to the one end based on a potential difference between the predetermined potential and the second potential at the second logic level.   2. The semiconductor memory device according to claim 1, wherein each of the plurality of write drive circuits is connected to an end of the corresponding bit line on the same side as a write drive circuit connected to an adjacent bit line. .   2. The semiconductor memory device according to claim 1, wherein each of the plurality of write drive circuits is connected to an end of the corresponding bit line opposite to a write drive circuit connected to an adjacent bit line. . Said provided corresponding to the plurality of bit lines, before SL Non the second higher the first of said write bit line selection signal bit lines, each of which the corresponding to the third potential lower than the potential than the potential further comprising a plurality of precharge circuits for precharging in response to the activation, the semiconductor memory device according to claim 1. Each of the plurality of connection circuits includes a first transistor;
Each of the plurality of precharge circuits includes a second transistor;
Said first and second transistor receives the write bit line select signal to the gate, when the write bit line selection signal is activated, is respectively turned on and off, the semiconductor memory according to claim 4 apparatus. A voltage supply circuit for supplying a voltage of the first potential to the plurality of write drive circuits;
The voltage supply circuit receives a third potential voltage higher than the predetermined potential and a fourth potential voltage higher than the third potential, and when the semiconductor memory device is inactivated, The third potential voltage is supplied as the first potential voltage to the plurality of write driving circuits, and when the semiconductor memory device is activated, the fourth potential voltage is changed to the first potential voltage. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is supplied to the plurality of write drive circuits as a voltage having a potential of 1. Each of the plurality of write drive circuits includes:
A current driver for passing a current through the corresponding bit line;
A control circuit for controlling the operation of the current driver,
When the semiconductor memory device is activated, the control circuit receives a second operating voltage higher than the first operating voltage received when the semiconductor memory device is inactive, and based on the second operating voltage, the current driver The semiconductor memory device according to claim 6 , which controls the operation of The current driver is
A first transistor connected between a first node to which the voltage of the first potential is applied and the corresponding bit line, and for passing a current from the first node to the corresponding bit line;
A second transistor connected between the corresponding bit line and a second node to which a voltage of the second potential is applied, and configured to flow current from the corresponding bit line to the second node; ,
The semiconductor memory device according to claim 7 , wherein the control circuit controls a gate potential of the first transistor based on the second operating voltage when the semiconductor memory device is activated. And further comprising another voltage supply circuit for supplying the voltage of the second potential to the plurality of write drive circuits,
The another voltage supply circuit receives a voltage of a fifth potential lower than the predetermined potential and a voltage of a sixth potential lower than the fifth potential, and the semiconductor memory device is inactivated. When the semiconductor memory device is activated, the fifth potential voltage is supplied to the plurality of write drive circuits as the second potential voltage as the second potential voltage. The semiconductor memory device according to claim 6 , wherein the semiconductor memory device supplies the plurality of write drive circuits as the voltage of the second potential.   Each of the plurality of memory cells has a magnetic body that is magnetized in a direction according to stored data, and is determined according to a direction of a current that flows in a bit line connected during data writing. The semiconductor memory device according to claim 1, wherein write data is stored according to the magnetization direction.

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