JP2007049752A - Logical processing circuit, semiconductor device and logical processing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce off-leakage current in an operation mode where a circuit actually is in operation. <P>SOLUTION: The logical processing circuit is constituted so that, for example, data held by flip-flops 11 to 13 at rising of a clock signal CK are processed by a logical gate circuit network 31, to which power is supplied during a low-level state period of the clock signal CK and its processing result is held in flip-flops 21 to 23, in a state with the power being always supplied to the flip-flops 11 to 13, 21, to 23 at each of front and rear stages. When power supply time to the logical gate circuit network 31 is set as the necessary minimum, the off-leak current at the logical gate circuit network 31 can be suppressed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a logic processing circuit as a CMOS type semiconductor integrated circuit in which data held in a front-stage flip-flop is processed by a logic gate circuit network and a processing result is held in a rear-stage flip-flop. In particular, a logic processing circuit that can reduce off-leakage current in a logic gate circuit network, a semiconductor device in which a chip on which the logic processing circuit is mounted is sealed inside a package, and also the semiconductor The present invention relates to a logical processing apparatus including a device as a component.

  In recent years, with the trend toward mobile devices, there has been a demand for further lower power consumption of LSI itself. On the other hand, with the evolution of CMOS (Complementary MOS) processes, in process generations such as 90 nm and 65 nm, the off-leakage current in MOS transistors increases, and it is also true that power consumption due to this has become negligible. is there. As countermeasures against this, until now, power is shut off in a standby mode in which MT (Multi Threshold) -CMOS is used or the clock is stopped.

  Incidentally, Patent Document 1 discloses a sequential circuit that is capable of high-speed operation with a low power supply voltage and capable of performing a reliable and stable power-down operation in order to reduce power consumption. Patent Document 2 discloses a master-slave flip-flop that has a function of reducing power consumption during standby and that does not lose stored data during standby.

Further, Patent Document 3 discloses a semiconductor integrated circuit device that can operate with a low power supply voltage when active in a semiconductor integrated circuit including a MOS transistor and can suppress power consumption caused by a leakage current during standby. Is disclosed. Furthermore, in Patent Document 4, there are no elements other than temporary storage elements (register elements and memory elements whose stored information disappears when the power supply voltage is cut off) in order to reduce power consumption during standby. The power supply voltage is not supplied.
Japanese Patent Application Laid-Open No. 07-271477 JP-A-11-284493 JP 2000-208713 A Japanese Patent Laid-Open No. 2001-251180

  However, in the operation mode in which the clock is input and the circuit is actually operating, it is actually impossible to reduce the off-leak current.

  Therefore, an object of the present invention is to provide a logic processing circuit capable of reducing off-leakage current in an operation mode in which a clock is input and the circuit is actually operated, and a chip on which the logic processing circuit is mounted. Another object of the present invention is to provide a semiconductor device sealed inside a package and a logic processing apparatus including the semiconductor device as a component.

  The logic processing circuit of the present invention includes a plurality of flip-flops including a front-stage flip-flop and a rear-stage flip-flop, and a logic gate circuit that processes data held in the front-stage flip-flop and stores a processing result in the rear-stage flip-flop One of the network and the low-level state period and the high-level state period of the clock signal is defined as a power-on period for supplying power to the logic gate circuit network, and the other is defined as a power-off period for cutting off the power. And switching means for switching between the power-on period and the power-off period, and in both the power-on period and the power-off period, the plurality of flip-flops are supplied with power, and the power-on period In synchronization with the switching from the power off period to the plurality of flip-flops, Each input data is stored, and only during the power-on period, the logic gate circuit processes the data held in the previous stage flip-flop, and the processing result is stored in the subsequent stage flip-flop. It is configured to output.

  According to the above configuration, for example, at the rising edge of the clock signal (synchronized with the switching from the power-on period to the power-off period), data is stored in the front-stage flip-flop, and processing from the logic gate network is performed in the rear-stage flip-flop. The result is held, and the data from the previous flip-flop can be processed while the power is supplied to the logic gate circuit only during the low level state period of the clock signal, that is, the L level state period. For example, when the low level state period is set as a time slightly longer than the minimum necessary time (the sum of the processing delay time in the logic gate network and the data setup time in the subsequent flip-flop), The off-leakage current in the logic gate network can be greatly reduced.

  A logic processing circuit capable of reducing off-leakage current in an operation mode in which a clock is inputted and the circuit is actually operated, and a semiconductor device in which a chip on which the logic processing circuit is mounted is sealed in a package A logic processing apparatus including the semiconductor device as a component is provided.

Hereinafter, an embodiment of the present invention will be described with reference to FIGS.
First, FIG. 1 shows a basic configuration of an example of a logic processing circuit according to the present invention. As shown in the figure, the power supply voltage V _DD is always supplied to the front-stage flip-flops 11 to 13 and the rear-stage flip-flops 21 to 23, while the logic gate circuit network 31 is interposed therebetween. Can supply a power supply voltage V _DD via a p-channel MOS transistor (hereinafter simply referred to as pMOS) 41 and an n-channel MOS transistor (hereinafter simply referred to as nMOS) 51 as a power cut Tr (Tr: transistor). Has been. When the power supply voltage V _DD is supplied to the logic gate network 31 depends on the state of the clock signal CK. In this example, the flip-flops 11 to 13 and 21 to 23 hold (capture) external data D11 to D13 and processing results D21 to D23 from the logic gate network 31 when the clock signal CK rises. Therefore, the power supply voltage V _DD is supplied to the logic gate circuit network 31 while the clock signal CK is in the L level state.

  While the clock signal CK is in the L level state, the pMOS 41 is turned on, and the nMOS 51 is also turned on via the inverter 61, so that the logic gate circuit 31 holds and outputs from the previous stage flip-flops 11-13. The processed data D11 to D13 are processed, and the processing result is also held in the subsequent flip-flops 21 to 23 at the next rising edge of the clock signal CK. Incidentally, in this example, power can be supplied to the logic gate network 31 via the pMOS 41 and the nMOS 51, but either one may be unnecessary and only the other may be ON / OFF controlled. Further, in this example, as the flip-flops 11 to 13 and 21 to 23, D-type flip-flops with rising edges (hereinafter simply referred to as DFFs) are assumed, but those with falling edges may be used. JK master-slave type flip-flops can be used.

  FIG. 2 also shows an operation timing chart in the above logic processing circuit. In this case, every time the clock signal CK rises, the external data D11 to D13 are transferred to the DFFs 11 to 13, respectively. It is supposed to be retained. The retained data D11 to D13 are then processed by the logic gate circuit network 31 after the clock signal CK transitions to the L level state. The processing results D21 to D23 from the logic gate network 31 are also taken into the DFFs 21 to 23 when the clock signal CK rises. Eventually, every time the clock signal CK rises, the data D11 to D13 are held in the DFFs 11 to 13, and simultaneously, the processing results D21 to D23 are held in the DFFs 21 to 23, and the data D11 to D13 are stored in the DFF11. If held at ˜13, the processing results D21 to D23 are held in the DFFs 21 to 23 after one cycle of the clock signal CK. Incidentally, in the figure, the mesh display indicates that the processing results D21 to D23 are in an indeterminate state.

  Therefore, since the processing results D21 to D23 need to be held in the DFFs 21 to 23 after being determined, the L level state period of the clock signal CK is not processed in the logic gate network 31. It is set as a time longer than the sum of the required time (processing delay time) and the data setup time in the subsequent flip-flop. However, if the off-leakage current is reduced in the intended purpose of the present invention, that is, in the operation mode in which the circuit is actually operating, the time is set slightly longer than the sum.

  Although the basic configuration and operation of the logic processing circuit have been described above, a configuration as shown in FIG. 3 is also conceivable. As shown in the figure, the entire logic gate circuit network 31 described above is divided into three along the processing direction, and the clock signal CK1 having the same frequency as the clock signal CK described above has a clock signal having a different phase, For example, two types of delayed clock signals CK2 and CK3 whose phases are shifted by 2π / 3 are created, while there is a new intermediate between the logic gate circuit portions 311, 312, 312 and 313 after the division into three. Stages DFF71 to 73 and 81 to 83 are interposed. Further, pMOS 411 to 413, nMOS 511 to 513, and inverters 611 to 613 are arranged around the logic gate network portions 311 to 313 as shown in the figure, and clock signals CK1 to CK3 are given to the logic gate network portions 311 to 313, respectively. ing.

  FIG. 4 also shows an operation timing chart in the above logic processing circuit. In this case, the external data D11 to D13 are held in the DFFs 11 to 13 every time the clock signal CK1 rises. It has become so. The held data D11 to D13 are then processed by the logic gate network portion 311 after waiting for the transition of the clock signal CK2 to the L level state, and the (intermediate) processing results D21 to D23 are processed by the clock signal CK2. Is held in the DFFs 71 to 73 at the time of rising. The processing results held in the DFFs 71 to 73 are also processed by the logic gate circuit portion 312 after waiting for the transition of the clock CK3 to the L level state, and the (intermediate) processing results D31 to D33 are clock signals. It is held in DFF 81-83 at the rising edge of CK3. The processing results held in the DFFs 81 to 83 are also processed by the logic gate network part 313 after waiting for the transition of the clock CK1 to the L level state, and the (final) processing results D41 to D43 are the clock signal CK1. Are held in the DFFs 21 to 23 at the time of rising.

  As a result, every time the clock signal CK1 rises, the data D11 to D13 are held in the DFFs 11 to 13, and simultaneously, the processing results D41 to D43 are held in the DFFs 21 to 23. The data D11 to D13 are stored in the DFF11. If held in ˜13, the processing results D41 to D43 are held in the DFFs 21 to 23 after one cycle of the clock signal CK. As described above, when the processing timings of the logic gate network portions 311, 312, 312, and 313 are shifted, the magnitude of the rush current (inrush current) can be suppressed as compared with the case of FIG. 1. Is. In addition, the time required for processing in each of the logic gate circuit portions 311 to 313 is generally not the same. However, if they are substantially the same, the L level state period in each of the clock signals CK1 to CK3 is almost the same. It will be set as the same time. As a matter of course, this time is set shorter than that in the clock signal CK.

Here, the DFF will be described. The internal configuration in one example is shown in FIG. 5A, and the relationship between the clock signals CK, CKI, and XCKI to the clocked inverter used as the constituent elements. Is shown in FIG. Prior to the description of these drawings (A) and (B), first, what is called a clocked inverter will be described. Its symbol display is shown in FIG. 6 (A), and a specific circuit configuration in one example is shown. As shown in FIG. That is, the clocked inverter 600 shown in FIG. 6A has a pMOS 601 and a CMOS inverter (consisting of a pMOS 602 and an nMOS 603) between the power supply voltage V _DD and the ground GND potential as shown in FIG. 6B. , The nMOS 604 is connected in series, and the CMOS inverter inverts the input signal IN only during the period in which the clock signals EN and XEN having the inversion relationship with each other are in the H level state and the L level state, respectively. As a result, the output signal OUT can be output in a low output impedance state.

  Returning to FIG. 5 again, if the description of the DFF is continued, the relationship among the clock signals CK, CKI, and XCKI is as shown in FIG. 5B. That is, the clock signal CK is inverted by the inverter 501 to obtain the clock signal XCKI, and the clock signal XCKI is further inverted by the inverter 502 to obtain the clock signal CKI. ing. Eventually, the clock signals CK and CKI are obtained as substantially the same.

  Here, the internal configuration of the DFF will be described in detail. The clocked inverter 503 is arranged as an input stage thereof. However, only when the clock signal CKI is in the L level state, the input is performed. The signal D is inverted by the clocked inverter 503 and then further inverted by the inverter 504. Eventually, when the clock signal CKI transitions to the H level state, the state of the input signal D immediately before the transition is stored and held by the inverter 504 and the clocked inverter 505. This storage state is taken out as Q output from the buffer gate 509 via the clocked inverter 506 and the inverter 507, but the storage state is assumed that the clock signal CKI subsequently transitions to the L level state. Are also stored and held by the inverter 507 and the clocked inverter 508. As a result, the DFF can hold and output the state of the input signal D immediately before the rising edge of the clock signal CK. Therefore, in the period in which the clock signal CK is in the H level state, even if an uncertain input voltage is input from a logic gate circuit network or a logic gate circuit network part to which power is not supplied, Since both the pMOS 601 and the nMOS 604 are in the OFF state and no through current is generated in the input stage, power saving can be achieved.

  Next, another configuration of the logic processing circuit will be described. FIG. 7 shows the configuration and FIG. 8 shows an operation timing chart thereof. As shown in the figure, the clock signal CK1 having the same frequency as the clock signal CK1 in FIG. 3 is sequentially passed through the delay gates 701 and 702 so that a part of the L level state period overlaps each other. Thus, clock signals CK2 and CK3 that are delayed little by little are generated from the clock signal CK1, and the logic gate circuit portions 311, 312, and 313 can be sequentially processed by these clock signals CK1, CK2, and CK3, respectively. It is in As a result, as in the case of FIG. 1, if the data D11 to D13 are held in the DFFs 11 to 13 at the rising edge of the clock signal CK1, the processing results D41 to D43 are obtained after one cycle of the clock signal CK1. It is held by DFF 21-23. Unlike the case of FIG. 1, such a power supply method is generally adopted as a circuit assuming that power is simultaneously supplied to each of the logic gate network portions 311, 312, and 313. Is considered to start from the first stage in the logic gate network part 311 and gradually move from the logic gate network part 311 to the last stage in the logic gate network part 313. A circuit portion or a circuit portion that has sufficient time before processing is performed does not need to be supplied with power, and the off-leakage current can be reduced more than that shown in FIG. Because it was.

  If another configuration different from the logic processing circuit is described, the configuration is shown in FIG. 9, and the operation timing chart is shown in FIG. As shown in FIG. 9, the overall configuration is almost the same as that shown in FIG. 7, but the L level state period in each of the clock signals CK2 and CK3 is set short. That is, in FIG. 7, the clock signals CK2 and CK3 are obtained directly from the delay gates 701 and 702, respectively, but in FIG. 9, one input is the original clock signals CK2 and CK3, and the other input, respectively. The clock signals CK2 and CK3 are obtained again from the two-input NAND gate with the clock signal CK1 as the clock signal CK1 (the function is the same as that of the two-input OR gate). As a result, compared with the clock signals CK2 and CK3 in FIG. The L level state period is set short, and the end timing of the L level state period of the clock signal CK3 coincides with the rising point of the clock signal CK1. Accordingly, the off-leakage current can be further reduced as compared with that shown in FIG.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment described above, and various modifications can be made without departing from the scope of the invention. Needless to say.

It is a figure which shows the basic composition in an example of the logic processing circuit by this invention. It is a figure which shows the operation | movement timing chart. It is a figure which shows the structure of the other example of the logic processing circuit by this invention. It is a figure which shows the operation | movement timing chart. It is a figure which shows the internal structure in an example of DFF (D type flip-flop). It is a figure which shows the specific circuit structure of a clocked inverter. It is a figure which shows the structure of the other example from which the logic processing circuit by this invention differs. It is a figure which shows the operation | movement timing chart. It is a figure which shows the structure of the further another example of the logic processing circuit by this invention. It is a figure which shows the operation | movement timing chart.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11-13 ... Pre-stage flip-flop, 21-23 ... Post-stage flip-flop, 71-73, 81-83 ... Intermediate stage flip-flop, 31 ... Logic gate network, 311-313 ... Logic gate circuit part, 41, 411- 413... P channel MOS transistor, 51, 511 to 513... N channel MOS transistor, 61, 611 to 613.

Claims (9)

A plurality of flip-flops including a front-stage flip-flop and a rear-stage flip-flop;
A logic gate circuit for processing data held in the preceding flip-flop and storing a processing result in the subsequent flip-flop;
One of the low-level state period and the high-level state period of the clock signal is defined as a power-on period for supplying power to the logic gate network, and the other is defined as a power-off period for cutting off the power. Switching means for switching between a power-on period and the power-off period;
With
In both the power-on period and the power-off period, the plurality of flip-flops are supplied with power,
In synchronization with switching from the power-on period to the power-off period, the plurality of flip-flops store data input to each of them,
Only during the power-on period, the logic gate network processes the data held in the preceding flip-flop and outputs the processing result to the subsequent flip-flop. The power-on period is set as a time larger than the sum of a processing delay time in the logic gate network and a data setup time in the subsequent flip-flop.
The logic processing circuit according to claim 1. The plurality of flip-flops are D-type flip-flops;
The logic processing circuit according to claim 1. The input stage of the D-type flip-flop is configured as a clocked inverter.
The logic processing circuit according to claim 3. When the logic gate network is divided into n (n: an integer greater than or equal to 2) along the processing direction, (n-1) types of delayed clock signals having different phases from the clock signal are generated, and n An intermediate stage flip-flop is interposed between each logic gate network part of
The clock signal is given to the front flip-flop and the rear flip-flop as a clock signal,
The clock signal supplies power to the final stage logic gate network part,
The (n-1) types of delayed clock signals are supplied as clock signals to the corresponding intermediate stage flip-flops, and power is sequentially supplied to the corresponding non-final stage logic gate circuit portions by the delayed clock signals. The
The logic processing circuit according to claim 1. When the logic gate network is divided into n (n: an integer of 2 or more) along the processing direction, the switching timing to the power-on period so that the power-on period slightly overlaps the previous one. (N-1) types of delayed clock signals are generated from the above clock signals,
Each of the n logic gate network portions is supplied with the corresponding delayed clock signal and the power having the switching timing slightly shifted according to the clock signal.
The logic processing circuit according to claim 1. The (n-1) types of delayed clock signals are created such that the greater the shift in the switching timing with respect to the clock signal, the shorter the power-on period.
The logic processing circuit according to claim 6.   A semiconductor device in which a chip on which the logic processing circuit according to claim 1 is mounted is sealed inside a package.   A logic processing apparatus comprising the semiconductor device according to claim 8.

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