JPS6020837B2 - Storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high speed, integrated storage device.

As a load for secondary high-speed memory cells, a resistor element and a diode in parallel have been mainly used.

In the holding state, a small current is passed through the resistor element to reduce power consumption, and when reading or writing memory cell information, a large current is passed through the diode to increase speed. However, in this configuration, as integration progresses, the proportion occupied by the resistor element portion increases, which is a drawback for high-density integration or low power consumption. Therefore, a memory cell has been proposed that uses a diode as a load, the value of which can be controlled depending on manufacturing conditions.

Since this memory cell does not require a resistive element, the cell area is reduced, and as the diode area becomes smaller due to higher density integration, the current decreases, resulting in lower power consumption. However, when this memory cell is used, manufacturing variations in diode characteristics cannot be compensated for in circuitry by using a conventional read/write control circuit. Therefore, even in a memory cell whose only load is this diode, a dedicated read/write control circuit is required that can compensate for manufacturing variations in diode characteristics and fluctuations due to temperature characteristics. Therefore, the present invention incorporates a circuit that combines a diode of the same type as the load of the memory cell and a constant current circuit into a secondary read/write control circuit as a read/write control circuit for a memory cell with only a diode as a load. It is an object of the present invention to provide a memory zero bag fixing system capable of compensating for variations in diode characteristics between lots and between chips.

The drawings will be explained in detail below. FIG. 1 shows an example of a memory device according to the invention, in which multi-emitter transistors T2 and T3 have their bases and collectors cross-connected to each other, each collector of which is connected to a transistor L, respectively.
, T3 are connected to each other through forward load diodes D2 and D3, respectively, the connection point 5 of which is connected to the word W, and the emitters of each of the transistors L, common are connected to each other, and this connection point 6 is connected to a constant current circuit 131.

These transistors T2, T3, diodes D2, D3
, a constant current circuit 13 constitutes a memory cell 11 of an emitter-coupled flip-flop. The other emitter of transistor T2 is connected to the emitter of transistor T, and its connection point 2 is connected to constant current circuit 12'.

The base 1 of the transistor T, through its emitter base and the forward diode D, is connected to the terminal 1 of the reference voltage VR.
2 and is also connected to the constant current circuit 1. The transistor T, the diode D, and the constant current circuit 1 constitute a reference voltage generation circuit 13. Similarly, the other emitter of the transistor T3 is connected to the emitter of the transistor L, its successor point 7 is connected to the constant current circuit 14, and the base 8 of the transistor T4 is connected to the reference voltage VR through its base emitter and forward diode ○4. It is connected to the terminal 14, and a constant current source is also connected thereto. A transistor T4, a diode D4, and a constant current circuit constitute a reference voltage generation circuit 15. Further, the transistors T, T4 of these control circuits 13, 15 and the transistors L, T3 of the memory cell 1'1 constitute a crab flow switching circuit, respectively.
The collectors of the transistors T, , L are connected to the power supply terminal 16, respectively. Next, memory operation in the configuration shown in FIG. 1 will be explained.

Memory operations include m memory retention, ■ reading, . It is divided into three parts: plot. First, for memory retention, the potential of the word line W0 is set lower than the reference voltage VR of the terminals 12 and 14. Therefore, the base potentials of the transistors T2 and T3 are both lower than the base potential of the transistors T, T4, so each read current IR/W of the constant current circuits and 14 flows through the transistors T, T4, respectively, and the memory cell 1
It doesn't flow to 1. Then, only the holding current lsT flows through the memory cell 11 in response to the constant current cycle. This holding current l
sT flows to the ON (conducting) transistor among the transistors L and T3. Next, in order to read the information of this memory cell 11, the base potential of the transistors L and T3 is raised by raising the potential of the word line W1, and the control circuit transistors T, . It is sufficient if it can be compared with the base potential of L.

Now transistor L is ON (conducting) and transistor T3
Assume that the line is OFF (non-guided). If the base potentials of transistors T2 and T3 are Vb2 and V is Vb3,
<VQ. Further, the base potential of the transistors T, , T4 is a reference voltage, which is set as Vr. At the time of holding, Vb3 - Vb2 < Vr, but at the time of reading, the potential of the word line W0 is increased to make VA<Vr<Vb2. At this time, in order to maintain a well-balanced (almost equal) voltage margin between the upper and lower sides, Vr is referred to as raw beef. In this way, the read current IR/W flowing through the transistor T is switched to the transistor L, but the read current IR/W flowing through the transistor T4 remains unchanged. In this way, information on the memory cell 11 can be known from changes in the collector currents of the transistors T, . Next, the penetration operation will be explained.

The potential of the word line W+ during writing is the same as that during reading. Consider turning the transistor T3 from OFF to ON. To do this, the reference voltage VR on the side of the diode D4 is lowered to lower the base potential of the transistor T4, thereby lowering the emitter potential of the transistor L.
Therefore, the voltage between the beta semiconductors of the transistor T3 is increased to turn on the transistor T3. Then, the potential of the collector of the transistor T3, that is, the base potential of the transistor L decreases, and the transistor T2 changes from ON to OFF. The write operation is then completed by returning the reference voltage VR on the diode D4 side to its original state. The memory operation has been described above, but in order to accurately know information about memory cells, the base potentials (reference reference voltages) of transistors T and L must be between the base potentials of transistors L and T3. However, the slave has a reference voltage of V
Since R was directly at the base potential of the transistor L, T4, the diode D2. If the characteristics of D3 change due to manufacturing variations or temperature changes, the noise margin will decrease, and in extreme cases, the holding reference voltage V of transistors T, T4 will decrease.
r is each base voltage Vb2 and V of transistors T2 and T3
If it falls out of between b, normal operation will no longer be possible. Therefore, in order to solve this drawback, in the present invention, reference voltage generation circuits 13 and 15 consisting of the same diodes as the load diodes D2 and D3 of the memory cell 11 and a constant current circuit are included in the read/write control circuit, thereby reducing the variation in diode characteristics. Even if this occurs between manufacturing lots, this can compensate if there is little variation within the chip.

The effect will be explained with reference to FIG. FIG. 2 shows the current-voltage characteristics of the diode.

1N and IF are ON and OFF of memory cell 11, respectively.
This is the current flowing through the diode of the side transistor.

At that time, the voltage drops across the diodes are assumed to be VN and VF.
Furthermore, if the voltage drop across the diode when the reference voltage lr is applied is Vr, then if the potential of the word line W0 and the reference voltage VR are equal, the relationship VN>Vr>VF in FIG. 2 remains as Vb2, Vr, Vb3. is replaced by the relationship . The value of the reference voltage Vr can be independently determined by the reference current lr. Furthermore, even if the diode characteristics vary between chips, the diode characteristics of diodes D3 and D4 will change in the same way as shown in Figure 2, so VN, Vr, and VF will change in parallel, so the noise margin will always remain the same. dripping In this way, by including the diodes 3 and D4 and the constant current circuit in the control circuit, variations in diode characteristics between chips can be compensated for, and the reference current Vr can always be set between VQ and V wide. A specific example of the read/write control circuit shown in FIG. 1 is shown with the same reference numerals attached to parts corresponding to those in FIG.

Conventional read/write control circuit 18 and memory cell 11
A reference voltage generation circuit 13, 1 is connected between the write control terminal of
5 is inserted. When the write command signal WE is applied as a low level to the read/write switching terminal 19 in the control circuit 18, the base of the transistor T5 becomes low level and turns FF, and its emitter causes the base of the transistor T6 to become low level. Therefore, in the fin flow switching circuit 21 made up of transistors L and T7, the transistor L side is turned on, and the fin flow switching circuit 22 made up of transistors T8 and T9 is turned on.
becomes operational. In this state, data input terminal 2
When penetration data is applied to transistor T, for example as a high level "1". turns ON, and the emitter output causes the base potential of the transistor T9 to rise above the reference potential VR2 of the base of the transistor T8, and the transistors ~ turn ON'. The collector potential of transistor T9 drops, which causes transistors T, . The collector current of D is reduced, and the emitter potential of the diode D is lowered to a constant voltage by the constant voltage circuit 24.
, I can give it to you. Therefore, the potential at the base or emitter of transistor T falls, transistor T2 is turned on, and "1" is driven into Mori cell 11. When a low level "0" is applied to the data input terminal 23, the transistor T.o is turned off and the transistor T8 is turned on.The collector current on the side of the transistor T is reduced and its emitter potential is lowered, which is controlled by the constant voltage circuit 25. The voltage is further lowered to a certain level and applied to the diode D4, and as a result, the transistor T3 is turned on, and "0" is written into the memory cell 11. At the time of reading, the read/write switching terminal 19 is set to high level, the transistor T5 is turned on, and the transistor T3 is turned on. L is turned on, transistor T7 is turned off, the fly current switching circuit 22 is rendered inoperable, a high potential is applied to the bases of transistors T, .

Note that 26 to 28 are constant current circuits, and in this example, Schottsky diodes are used as diodes D and D4. As explained above, when using a flip-flop type memory cell whose load is a diode with exponential characteristics, the diode characteristics can be improved by using a circuit containing a diode with the same characteristics as the load in its read/write control circuit. Can compensate for manufacturing variations and fluctuations.

[Brief explanation of the drawing]

FIG. 1 is a connection diagram showing an embodiment of the memory device according to the present invention, FIG. 2 is a current-voltage characteristic diagram for explaining the principle of compensating for variations and fluctuations in diode characteristics, and FIG. 3 is a diagram showing the memory device according to the present invention. It is a connection diagram showing a specific example. D,,D2,D3,D4: Diode, T,,T2,T
3, L: Transistor, 1,, 12, 13, L, 15:
constant current circuit, VR,, VR2, VR3, VR4: reference voltage, 11: memory cell, 13, 15: reference voltage generation circuit, 18: read/write control circuit, 19: read/write switching terminal,
23: Data input terminal. O figure ne figure 2 figure ne 3 figure

Claims (1)

[Claims] 1 The output of a read/write control circuit is applied to the control terminal of a flip-flop type memory cell whose load is a diode with exponential current/voltage characteristics, and read/write control is performed by controlling the output potential. In the storage device, a reference voltage generation circuit consisting of a diode having the same current/voltage characteristics as the diode and a DC connection of a constant current circuit is inserted between the memory cell and the control circuit, and the reference voltage is generated by the output of the control circuit. A memory device configured to control a generated output voltage of a generating circuit so that the generated output voltage is applied to a control terminal of the memory cell.