JP2595876B2 - Semiconductor memory circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory circuit,
In particular, the present invention relates to a semiconductor memory circuit having a PNP load type bipolar configuration.

[0002]

2. Description of the Related Art A PNP load type memory cell is, for example, an SB type.
Compared with a memory cell of a D load type, it has advantages such as a smaller area, a higher resistance to soft errors, and a lower power consumption. Therefore, it is used for a RAM requiring relatively high integration. However, since the PNP transistor is used in a saturated state in the PNP load type memory cell, there is a disadvantage that the writing speed is low.

In a PNP load type memory cell, as shown in FIG. 4, a memory cell of a flip-flop configuration is constituted by PNP transistors Q1 and Q2 and output transistors Q3 to Q6. Here, C1 to C4
Is a parasitic capacitance of the memory cell, and Q7 and Q8 are write transistors.

In a PNP load type memory cell, PN
P transistor Q1 and output transistor Q3, PNP
Transistor Q2 and output transistor Q4 each constitute a PNPN half-cell, and cross-connect each other's base and collector to hold data.

The output transistor Q3 and the writing transistor Q7, and the output transistor Q4 and the writing transistor Q8 constitute a current switch circuit with the current sources IRW1 and IRW2, respectively. These write transistors Q7,
By changing the base signals WCA and WCB of Q8,
Writing to the memory cell is performed.

Writing to a PNP load type memory cell can be explained by charging and discharging of charges in the parasitic capacitances C1 to C4. Here, the writing of the inverted data immediately after the reading where the writing condition is the strictest will be described below.

If it is assumed that the memory cell is in the read state in the initial state of writing to the memory cell, the left P
A read current is flowing through the half cell of the NPN configuration, and the PNP
Transistor Q1 is in the ON state in the deep saturation region. A read current flows from the write transistor Q8 to the right bit line DB.

In this state, the cell base potential CA holds a low level, the cell base potential CB holds a high level, and the base signals WCA and WCB are located at an intermediate potential therebetween.

At this time, a large amount of charge is accumulated in the diffusion capacitance corresponding to the forward bias of the PNP transistor Q1 in the parasitic capacitance C1, and the PNP transistor Q is stored in the parasitic capacitance C2.
A small amount of charge is stored in the diffusion capacitance corresponding to the forward bias of 2.

Also, the parasitic capacitance C3 has a cell base potential C
A large amount of charge is accumulated in the diffusion capacitance corresponding to the potential difference between A and CB, and the cell base potentials CA and CB are stored in the parasitic capacitance C4.
Slight charges are stored in the diffusion capacitance corresponding to the potential difference between the two.

In the first half region t1 of the write operation of the memory cell, the base signal WCA is set to a higher level than the cell base potential CB to write the inverted data, and the base signal WC
B is set to a lower level than the cell base potential CA.

In the half cell having the PNPN configuration on the right side, since the base signal WCB goes low, the output transistor Q
4 is turned on, but this write current first
, C4. As the charging of the parasitic capacitance C2 progresses, the base current of the PNP transistor Q2 becomes dominant. As a result, the cell base potential CB decreases to a low level.

In the bit line DA on the left side, the write transistor Q7 is turned on at once and the write current is switched, but since the accumulated charge of the parasitic capacitance C1 at the time of saturation is maintained, the cell base potential CB keeps the low level. It remains.

As described above, the PNP transistors Q1, Q
2 is in the ON state, and the period until both the cell base potentials CA and CB become low level is the first half region t1 of the write operation of the memory cell.

In the latter half region t2 of the write operation of the memory cell, the PNP transistor Q1 must be turned off in order to complete the write, so that the parasitic capacitance C3,
It is necessary to charge C4 and discharge the parasitic capacitance C1. These charge and discharge currents are supplied from the collector of PNP transistor Q2.

The charge and discharge change the cell base potential CA from a low level to a high level. The period from the first half region t1 of the memory cell write operation to the transition of the cell base potential CA to the high level is the second half region t2 of the memory cell write operation.

When the charging and discharging of the parasitic capacitances C1 to C4 are completed, the writing of the inverted data to the memory cells is completed.

As described above, the write operation is performed in accordance with the parasitic capacitances C1 to C1.
Since it is equivalently expressed as the movement of charge and discharge of C4, as a countermeasure to speed up the write operation, it is conceivable to accelerate the charge and discharge.

Therefore, a method of shortening the write time by increasing the current at the time of writing over the current at the time of reading has been considered. This method is disclosed in JP-A-58-704.
There is a technique disclosed in US Pat.

As a method of speeding up the write operation,
As shown in FIG. 5, memory cells (MC) are controlled by current switch circuits 5, 6 connected to bit lines DA, DB.
There is a method of switching the current flowing from 7-1 to 7-m so that the current flowing from the memory cells 7-1 to 7-m at the time of writing is larger than the current at the time of reading.

In this case, the bit lines DA and DB are connected to the constant current sources IR1 and IR2 via the bit line selection switches QSW1 and QSW2.
, And connected to write current sources IW1 and IW2 via current switch circuits 5 and 6.

The write control unit 10 generates a write pulse signal WP
And the write data signal WD is the write control circuit (WC) 3
The write timing and information are transmitted to the memory cells 7-1 to 7-m in accordance with the write control signals WCA and WCB converted in step (1).

Further, the write control unit 10 uses the current switch control signals WIA and WIB obtained by converting the write pulse signal WP and the write data signal WD by the current switch control circuit (WI) 4 to switch the current switch circuits 5 and 6.
Control.

The conversion of the write pulse signal WP and the write data signal WD into the write control signals WCA and WCB and the current switch control signals WIA and WIB by the write control circuit 3 and the current switch control circuit 4 is for amplitude and level conversion only. Done.

The write control signals WCA and WCB and the current switch control signals WIA and WIB have the same timing at the leading and trailing edges as shown in FIG.
Is switched to increase the write current of the memory cells 7-1 to 7-m. In addition, 8-1 to 8-n are each a memory cell 7-1.
7 to 7-m.

[0026]

In a write operation of a memory cell which is equivalently expressed by charging and discharging of a parasitic capacitance, a current amplification factor β _PNP of a PNP transistor has a great influence. In the first half region t1 of the write operation, the parasitic capacitance C3 must be discharged in order to change the cell base potential CB from the high level to the low level. Therefore, it is better that the supply from the collector of the PNP transistor Q1 in the ON state is smaller, that is, the current amplification factor β _PNP is smaller.

On the other hand, in the latter half region t2 of the write operation, the discharge of the parasitic capacitance C1 and the charging of the parasitic capacitance C3 are supplied from the collector of the PNP transistor Q2 which is already turned on in order to change the cell base potential CA to the high level. There is a need to.

Therefore, it is desirable that the current amplification factor β _PNP is large in the latter half region t 2 of the write operation. That is, in order to speed up the write operation, the current amplification rate β
_{The PNP} is required to have conflicting characteristics between the first half region t1 of the write operation and the second half region t2 of the write operation.

However, the P employed in the memory cell
The characteristic of the NP transistor is that, as the current increases in a large current range, the current amplification factor β _PNP decreases. Therefore, in the conventional method in which the write current is increased at the same timing as the write pulse, the write current increases and the current always increases during the write period. The amplification factor β _PNP is small. Therefore, the writing operation becomes faster in the first half region t1 of the writing operation, but becomes slower in the second half region t2 of the writing operation.

At present, in the breakdown of the write time, the latter half region t2 of the write operation is dominant. Therefore, considering the write time in total, even if the current at the time of write is greatly increased, it is further increased. There is a problem that it is difficult to increase the speed.

In the conventional method, the forward voltage VBE of the word driver output transistor and the PNP transistor in the memory cell increases, and the memory cell potential decreases accordingly. In the latter half region t2 of the write operation, even after the charging and discharging of the memory cell are completed, the potential in the memory cell does not recover to a normal level due to the potential drop, and remains in a lowered state.

When the writing operation is returned to the reading operation in this state, a time until the lowered high-level memory cell potential recovers and stabilizes, that is, a so-called recovery time must be sufficiently taken. There is a problem that the write cycle time increases. further,
There is also a problem that the output waveform produces ringing.

It is an object of the present invention to provide a semiconductor memory circuit which can solve the above-mentioned problems, can speed up the write operation, and can shorten the total write cycle time.

[0034]

A semiconductor memory circuit according to the present invention is a semiconductor memory circuit in which data is written by a write current flowing in a memory element in response to a write pulse signal, wherein the write current is stored in the memory. and means for increasing than the current flowing during reading of data to the device, the write current to increase the time of the write current in a shorter time than the pulse width of the write pulse signal
Control means for controlling the increase to end in the first half area of the data write operation .

Another semiconductor memory circuit according to the present invention comprises a pair of drive transistor elements each having a base and a collector cross-connected to each other, a PNP transistor element connected as a load to the collector of the drive transistor, and A plurality of memory cells each arranged in a matrix, a pair of bit lines to which the emitters of the drive transistor elements of the memory cells in the same column among the plurality of memory cells are commonly connected, and a pair of the bit lines. A pair of write transistors each having an emitter connected thereto, and a current source for supplying a current to each of the pair of bit lines, and applying a pulse signal to the bases of the pair of write transistors to form the pair of write transistors A semiconductor memory circuit for controlling writing to the memory cell by turning on and off the memory cell. And means for increasing than the current at the time of reading the write current side of the bit line to flow a current from the memory cell during the write, the time for increasing the write current of the pulsed signal applied to the base of the write transistor Shorter than the pulse width ,
Means for controlling the increase to end in the first half area of the data write operation .

[0036]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of one embodiment of the present invention. Referring to FIG. 5, an embodiment of the present invention is similar to that of FIG.
And the same components are denoted by the same reference numerals. The operation of these same components is the same as the operation of the conventional example.

The gate circuit 20 of the pulse generation circuit 2 generates a non-inverted signal and an inverted signal from the input write pulse signal WP, outputs the non-inverted signal WP1 to the AND circuit 22, and converts the inverted signal into a delay circuit ( (Delay) 21.

The delay circuit 21 delays the inverted signal input from the gate circuit 20 by a predetermined time, and outputs the delayed signal WP2 to the AND circuit 22. The AND circuit 22 performs an AND operation on the normal signal WP1 from the gate circuit 20 and the signal WP2 delayed by the delay circuit 21, generates a signal WP3 having a pulse width shorter than the write pulse signal WP, and performs current switch control. Output to the circuit 4. The timing chart of FIG. 2 shows the operation of generating the signal WP3 by the AND circuit 22.

The current switch control circuit 4 converts the signal WP3 from the pulse generation circuit 2 and the write data signal WD into current switch control signals WIA and WIB, and outputs them to the current switch circuits 5 and 6.

The current switch circuits 5, 6 are controlled by current switch control signals WIA, WIB, and increase the current of one of the bit lines DA, DB during a write operation on the memory cells 7-1 to 7-m. At this time, the increase time of the current is shorter than the write time because the pulse width of the signal WP3 from the pulse generation circuit 2 is shorter than the write pulse signal WP.

That is, the speed is increased by increasing the current in the first half region t1 of the write operation. Therefore, the pulse generation circuit 2 is not used until the first half region t1 of the write operation is completed.
From the signal WP3. This signal WP
Since the pulse 3 is unnecessary in the second half region t2 of the write operation, the pulse is ended immediately after the first half region t1 of the write operation is completed.

FIG. 3 is a circuit diagram showing the configuration of another embodiment of the present invention. In the drawing, another embodiment of the present invention has the same configuration as that of the embodiment of the present invention shown in FIG. 1 except that one current switch circuit 9 is used, and the same components are denoted by the same reference numerals. It is. The operation of these same components is the same as the operation of the conventional example.

The current switch control circuit 4 generates current switch control signals WIA and WIB at the same level when reading data from the memory cells 7-1 to 7-m so that the currents flowing through the bit lines DA and DB are the same. To be.

When writing to the memory cells 7-1 to 7-m, the current switch control circuit 4 generates one of the current switch control signals WIA and WIB based on the pulse of the signal WP3 from the pulse generation circuit 2. One of the transistors Q9 and Q10 of the current switch circuit 9 is turned on for a time shorter than the writing time. As a result, the current flowing through one of the bit lines DA and DB is increased for a time shorter than the write time.

As described above, the memory cells 7-1 to 7 are controlled by the pulse generation circuit 2 and the current switch control circuit 4.
By controlling the write current to increase only in the first half region t1 of the write operation for -m, the write operation in the first half region t1 of the write operation can be sped up, and the write operation in the second half region t2 of the write operation can also be sped up. can do.

Further, since the transition of the potential of the memory cells 7-1 to 7-m to a normal level can be accelerated in a DC manner, the recovery time can be shortened, and the total write cycle time is greatly reduced. be able to.

[0048]

As described above, according to the present invention, a write current flowing through a memory element in response to a write pulse signal flows for a time shorter than the pulse width of the write pulse signal when data is read from the memory element. By increasing the current, the write operation can be sped up and the total write cycle time can be shortened.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of one embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of generating a pulse signal by the AND circuit of FIG. 1;

FIG. 3 is a circuit diagram showing a configuration of another embodiment of the present invention.

FIG. 4 is a diagram for explaining a write operation of a PNP load type memory cell.

FIG. 5 is a circuit diagram showing a configuration of a conventional example.

FIG. 6 is a timing chart showing a write control signal and a current switch control signal of FIG. 5;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 write control unit 2 pulse generation circuit 3 write control circuit 4 current switch control circuit 5, 6, 9 current switch circuit 7-1 to 7-m memory cell 8-1 to 8-n memory cell column

Claims (4)

(57) [Claims] 1. A semiconductor memory circuit in which data is written by a write current flowing in a memory element in response to a write pulse signal, wherein the write current is made larger than a current flowing when data is read from the memory element. means and said write increase time of the write current in a shorter time than the pulse width of the write pulse signal
Current increase ends in the first half of the data write operation
And a control means for controlling the operation of the semiconductor memory circuit. 2. The control means performs a logical operation on the write pulse signal and a signal obtained by inverting and delaying the write pulse signal, and generates a signal for controlling an increase time of the write current from the operation result. 2. The semiconductor memory circuit according to claim 1, comprising: 3. A drive transistor element having a base and a collector cross-connected to each other, and a PNP transistor element connected as a load to the collector of the drive transistor, each of which is arranged in a matrix. A plurality of memory cells, a pair of bit lines in which the emitters of the driving transistor elements of the memory cells in the same column among the plurality of memory cells are connected in common, and a pair of write lines in which the emitters are respectively connected to the pair of bit lines A transistor and a current source for supplying a current to each of the pair of bit lines, and applying a pulse-like signal to the bases of the pair of write transistors to turn on and off the pair of write transistors, A semiconductor memory circuit for performing write control, wherein said memory cell is And means for increasing than the current at the time of reading the write current side of the bit line to flow a Luo current, shorter than the pulse width of the pulse signal giving the time of increasing the write current to the base of the write transistor
The write current increases before the data write operation.
Means for controlling to end in a half area . 4. The control means performs a logical operation on the pulse signal and a signal obtained by inverting and delaying the pulse signal, and controls a time for increasing the write current based on the operation result. 4. The semiconductor memory circuit according to claim 3, comprising: