JPH0517640B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a write circuit in a semiconductor memory device, and particularly to a write circuit suitable for a bipolar memory.

[Background technology]

When operating a write circuit inside an IC based on a control signal such as a write enable signal supplied from outside the memory, it is necessary to prevent the write circuit from being operated erroneously due to noise in the control signal. . Therefore, as shown by the symbol S in FIG. 1, by passing the write enable signal and this through two stages of delay gates G ₁ and G ₂ ,
By performing an appropriate logic (for example, wired OR) with the signal WE1 which has been given an appropriate delay, a signal WE2 from which the noise component has been removed from the write enable signal is formed as shown in FIG.
A two-stage shrink circuit designed to prevent writing of erroneous data has already been proposed by the applicant.

By the way, when a memory is constructed in which a write amplifier is operated by the output signal of this two-stage shrink circuit to write data to a memory cell, the number of gates in the input path of the address signal to the memory cell is As shown in the figure, only two stages, an address buffer 1 and a word line driver 2, are required. On the other hand, the number of gates in the write control signal input path is two stages in the two-stage shrink circuit S and one stage in the write amplifier, resulting in a total of three stages.

Therefore, if the address buffer 1 and driver 2 are made faster in order to improve the memory write speed, the timing of the write pulse will be relatively delayed due to the delay in the two-stage shrink circuit. As a result, it was found that the address hold time t _WHA from the rise of the write pulse to the switching of the address signal could not be taken sufficiently, resulting in the inconvenience that the speed of the memory could not be realized.

[Purpose of the invention]

The present invention was made against the background as described above. In a semiconductor memory equipped with a shrink circuit that cuts noise in a write control signal, the number of gates from the write control signal input terminal to the memory cell is determined by address input. By making the number of gates from the terminal to the memory cell the same and making the delay time equal between the address input system and the write control signal input system as seen from the memory cell, it has excellent noise resistance and enables high-speed memory. The purpose of the present invention is to provide a write circuit that can perform the following steps.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the present invention has a current switch circuit operated by a potential difference between a write control signal and a reference voltage, an emitter follower driven by receiving the output thereof, and a capacitor in the circuit. Noise in the write control signal can be cut by connecting a reference voltage generation circuit that receives the output level and changes the reference voltage after an appropriate amount of time following changes in the write control signal. In addition, the present invention provides a shrink circuit that can be configured as a single-stage gate circuit, thereby achieving the above object by equalizing the number of gates, that is, the delay time, in the address input system and the write control signal input system. .

The present invention will be specifically explained below using the drawings.

〔Example〕

FIG. 3 shows, as an example, an embodiment in which the present invention is applied to a bipolar static RAM (random access memory).

In the figure, 1 is an address buffer that receives an address signal _A This is a word line drive circuit that brings the corresponding word line W to the selection level.

In the memory cell array 3, a large number of flip-flop type memory cells MC, of which only one is illustrated in the drawing, are arranged in a matrix. Each memory cell is connected to a pair of data lines d and a standby line ST through which a standby current flows.

Although not shown, this memory includes an address buffer that receives a Y-system address signal supplied from the outside, and a corresponding pair of data lines d in the memory cell array 3 based on the output of this address buffer. , is provided.

Further, in the figure, 4 is a shrink circuit that receives a write enable signal which is a write control signal supplied from the outside and cuts noise, 5 is a data input buffer, and 6 is an output from the above shrink circuit 4 and data input buffer 5. This is a write amplifier that performs a desired write operation based on a signal.

The Shrink circuit 4 includes a pair of transistors Q ₁ and Q ₂ whose emitters are commonly connected, and a constant current source 4 a connected between the common emitters of the transistors Q ₁ and Q ₂ and a power supply voltage V _EE . and the collectors of the above transistors Q ₁ and Q ₂ and the power supply voltage V _CC
A current switch circuit CS ₀ consisting of resistors R ₁ and R ₂ each connected between the (ground level) and
have. Then, the connection node n ₁ between the collector of the transistor Q ₁ and the resistor R ₁ and the power supply voltage
A resistor R ₃ and diodes D ₁ and D ₂ are connected between V _EE and a voltage that is two steps higher than the threshold voltage of diodes D ₁ and D ₂ than V _EE and the power supply voltage V _CC . A voltage obtained by dividing the potential difference by the resistance ratio of the resistors R ₁ and R ₃ is generated at the node n ₁ '.
The potential of this node n ₁ ' is applied to the base of a transistor Q ₃ whose collector is grounded, and the emitter voltage of this transistor Q ₃ is applied as a reference voltage V _BB to the base of one transistor Q ₂ of the current switch circuit CS ₀ . is being applied. The emitter of the transistor _Q3 is drawn to _VEE by a constant current source 4b. And the above transistor R ₁ ,
A reference voltage generation circuit 41 is constituted by R ₃ , diodes D ₁ and D ₂ , transistor Q ₃ and constant current source 4b. On the other hand, the base of the other transistor _Q1 of the current switch circuit _CS0 is connected to an IC.
A write enable signal WE supplied from the outside is applied. Therefore, the current switch circuit _CS0 is configured to switch the current path using the reference voltage _VBB applied to the base of the transistor _Q2 as a threshold. That is, when the write enable signal is higher than the reference voltage V _BB , current flows through the transistor Q ₁ , and when the write enable signal becomes lower than the reference voltage V _BB , the current in the transistor Q ₁ is cut off, and the transistor
Current begins to flow through Q ₂ .

Moreover, in the shrink circuit of this embodiment, the current flowing through the resistor R ₁ is shunted to the transistor Q ₁ and the reference voltage generation circuit ₄₁ . The generated reference voltage _VBB is changed depending on whether the In other words, when the write enable signal is set to high level and transistor Q ₁ is turned on, the voltage drop across resistor R ₁ is large, so the level of node n ₁ , that is, n ₁ ', is low, and the reference voltage V _BB is lower than this. is further lowered by the voltage between the base and emitter of transistor _Q3 . This allows the write enable signal to
The potential difference between the high level of WE and the reference voltage V _BB can be made larger than in the case of a normal ECL interface, which reduces noise when the write enable signal is at a high level (when not writing).
Margins can be expanded significantly. On the other hand, when the write enable signal is set to low level and transistor Q ₁ is turned off, the voltage drop across resistor R ₁ becomes small, and the level at node n ₁ ' rises.
The reference voltage V _BB is made higher than when transistor Q ₁ is turned on. Therefore, in the circuit of this embodiment, the noise margin is not impaired even when the write enable signal is at a low level (during writing). As a result of the above, in the circuit of this embodiment, the noise margin during non-writing is greatly improved in terms of direct current, as shown in FIG. 2d.

Moreover, in this embodiment, there is also a delay between the node n ₁ ' in the reference voltage generation circuit 41 and the power supply voltage V _CC (ground level) in order to expand the noise margin during non-writing in terms of AC. Capacitor C ₁ for
is provided. This capacitor C ₁ is changed by the write enable signal, and the transistor Q ₁
is charged and discharged when the collector voltage of the battery changes accordingly. Therefore, the node n ₁ ' does not fluctuate following the fluctuation of the collector voltage of the transistor Q ₁ , and the reference voltage V _BB generated according to the potential of the node n ₁ ' also begins to fluctuate with a delay.
Therefore, a time difference occurs between the change in the write enable signal _WE and the change in the reference voltage _VBB , which fluctuates accordingly, as shown in Fig. 2d, and the current switch circuit _CS0 is affected by noise in the write enable signal. You will no longer pick up. As a result, an output signal WE1 from which noise components are removed from the write enable signal is obtained from the emitter follower _EF0 , which is composed of a transistor _Q4 driven by the collector voltage of the transistor _Q2 and a constant current source 4c.

Moreover, according to the reference voltage generation circuit as described above, for an interface consisting of an ECL circuit,
It becomes possible to match temperature fluctuations and power supply voltage dependence.

As the delay capacitor C ₁ , for example, a bipolar transistor is formed, its base is connected to the node n ₁ ', and its emitter or emitter and collector are connected to the power supply voltage V _CC , thereby reducing the PN of the transistor. Parasitic capacitance between junctions can be used.

Next, the light amplifier 6 consists of three emitter-coupled transistors, as shown in FIG.
Current switch circuit CS ₁ containing Q ₁₁ to Q ₁₃ and 2 connected to the collectors of transistors Q ₁₂ and Q ₁₃
It consists of two emitter followers, EF ₁ and EF ₂ . And the above transistors Q ₁₁ to _{Q 13}
The output signal of the Shrink circuit 4 is based on the base of
WE1 and the output din of the data input buffer 5 are applied, respectively. In addition, the above Emitsuta
A pair of common data lines CD in the memory cell array 3 are connected to output nodes N ₁ and N ₂ of followers EF ₁ and EF ₂ ,
A CD is connected.

This write amplifier 6 uses a write enable signal.
When WE is leveled, the transistor
_Q11 is turned on and current flows through transistor _Q12
The currents between and Q ₁₃ are cut off. As a result, the collector voltages of transistors _Q12 and _Q13 are both set to V _CC (ground level), and transistor _Q14
and Q ₁₅ is turned on. Therefore, current flows through emitter followers EFF ₁ and EF ₂ and the output node N ₁
and the level of _N2 rises, and the common data line CD,
Both CDs are set to high level.

The level of the common data line CD is applied as a reference voltage to the bases of a pair of transistors Q ₂₁ and Q ₂₂ whose emitters are connected to the data line d in the memory cell array 1. Furthermore, the high level of the common data line CD is higher than the base potentials V _C0 and V _C1 of the transistors Q ₀₀ and Q ₀₁ in the memory cell MC when the word line is not selectively driven, and the word line is selected. Base potential inside memory cell MC when driven
The circuit constants are set in advance to be between V _C0 and V _C1 .

Therefore, when the word line W is set to the selection level by the word line drive circuit 2 during reading when the write enable signal is set to high level,
The transistor in the memory cell connected to this
The base potentials V _C0 and V _C1 of Q ₀₀ and Q ₀₁ rise, and a large current begins to flow into the data line d or through the transistors that are turned on. On the other hand, at the time of reading (when is high), the outputs of the write amplifier 6 are both set to high level, so that both transistors _Q21 and _Q22 connected to the common data line CD are turned on. As a result, a current flows from inside the memory cell MC to the data line d or connected to the turned-on transistor Q ₀₀ or Q ₀₁ in the memory cell MC, and flows to the data line connected to the turned-off transistor. is transistor Q ₂₁ or
Current begins to flow from the sense amplifier 7 through _Q22 .

The sense amplifier 7 detects and amplifies this difference, thereby reading the data held in the memory cell MC.

On the other hand, when the write enable signal is temporarily set to low level as shown in Figure 2a, during that time,
The transistor _Q11 in the write amplifier 6 is cut off, and the current switch circuit _CS1 operates according to whether the input data Din is high or low at that time.
A current path is formed only in one of transistors _Q12 and _Q13 . Therefore, current flows only through one transistor of the emitter followers EF ₁ and EF ₂ , the potential of one of the nodes N ₁ or N ₂ decreases, and either the common data line CD becomes the high or low level of the input data Din. The low level is set according to the The low level of this data line CD or the word line W is set to the selection level and the memory cell
Base potential V _C0 of transistors Q ₀₀ and Q ₀₁ in MC,
The circuit constants are determined so that the potential V C0 is much lower than the lower potential V _C0 when V _C1 is increased.

Therefore, for example, assume that the state of the memory cell MC during information retention is such that the transistor Q ₀₀ is turned on and the transistor Q ₀₁ is turned off by the current flowing to the standby line ST (V _CO <V _C1 ). At this time, assume that the common data line is set high and CD is set low. Then, the base potential of the transistor _Q22 is made lower than the base potential _VCO of the turned-off transistor _Q01 in the memory cell MC.
Therefore, a current flows from the transistor Q ₀₁ in the memory cell MC to the data line d by being drawn by the constant current source, and as a result, the collector voltage of the transistor Q ₀₁ , that is, the base potential of the transistor Q ₀₀ begins to decrease. As a result, the transistor Q ₀₀
The current decreases, the collector voltage, that is, the base potential of transistor _Q01 rises, and the current increases further, and the flip-flop forming the memory cell is suddenly reversed, and the opposite information is written.

In this way, in the above embodiment, the shrink circuit 4
is the current switch circuit CS ₀ and emitter follower
It consists of a single-stage gate circuit consisting of EF ₀ . Therefore, the number of gates in the address signal input system from the address input terminal to the memory cell is two stages: the address buffer 1 and the driver in the word line drive circuit 2. There are two stages: the shrink circuit 4 and the write amplifier 6. As a result, the address force seen from the memory cell and the delay time of the write pulse input are equal, and the address hold time t _WHA from the rise of the write pulse until the address signal switches is sufficient. Become.

Note that the single-stage gate shrink circuit is not limited to the configuration as in the above embodiment.

〔effect〕

As explained above, the present invention includes a current switch circuit operated by a potential difference between a write control signal and a reference voltage, and a capacitor, and a change in the write control signal in response to the level of an appropriate node in the current switch circuit. A shrink circuit that cuts noise in the write control signal is configured by a reference voltage generation circuit that generates a reference voltage that changes with a little delay than the current switch circuit, and an output stage that is driven by the output of the current switch circuit. Therefore, the noise margin during non-writing is increased, making it difficult for noise to be added to the output, and there is also a time difference between the fluctuation of the writing control signal and the accompanying fluctuation of the reference pressure, making it difficult to pick up noise. Writing of incorrect data due to noise is prevented.

Furthermore, by using the shrink circuit configured as a single-stage gate as described above, the number of gates from the input terminal of the write control signal to the memory cell can be reduced.
Since the number of gates from the address signal input terminal to the memory cell is the same as that of the memory cell, the address input delay time seen from the memory cell is equal to the write pulse input delay time. A sufficient address hold time _tWHA can be taken without unnecessary delay. As a result, it is possible to improve the writing speed and realize a high-speed memory.

Although the invention made by the present inventor has been specifically explained based on the examples above, the present invention is not limited to the above examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of a bipolar memory, FIG. 2 is a waveform diagram of a write enable signal and signals derived from it, showing the action of a shrink circuit, and FIG. 3 is a diagram of a semiconductor memory device to which the present invention is applied. FIG. 2 is a circuit configuration diagram showing an example. 1...Address input buffer, 3...Memory cell array, 4...Shrink circuit, 41...Reference voltage generation circuit, 5...Data input buffer, 6...Write amplifier,...Write control signal (write enable signal), MC...Memory cell, CS ₀ ...Current switch circuit, EF ₀ ...Output stage (emitter follower).

Claims (1)

[Claims] 1. A semiconductor memory device equipped with a shrink circuit for compressing noise in a write control signal supplied from the outside, in which the number of gate stages from the signal input terminal of the write control system including the shrink circuit to the memory cell array section is: The shrink circuit is configured to have the same number of gate stages from the address signal input terminal to the memory cell array section, and the shrink circuit includes a current switch circuit operated by a potential difference between a write control signal and a reference voltage;
In response to the level of a predetermined node in the current switch circuit including a capacitor, the current switch circuit changes with a delay of at least the width of the noise on the signal than the change in the write control signal, and has a noise margin according to the level of the input signal. 1. A write circuit in a semiconductor memory device, comprising an ECL circuit including a reference voltage generation circuit that generates a reference voltage that increases the reference voltage.