JPH0778482A - Semiconductor storage circuit - Google Patents

Abstract

PURPOSE:To perform a writing operation at high speed and to shorten the time of a total writing cycle. CONSTITUTION:A gate circuit 20 of a pulse generating circuit 2 generates a forward signal and an inversion signal from an inputted write pulse signal WP to output to an AND circuit 22 and a delay circuit 21 respectively. The delay circuit 21 delays the inversion signal by a prescribed time and outputs the delaied signal WP2 to the AND circuit 22. The AND circuit 22 ANDs the forward signal WP1 and the signal WP2 delayed by the delay circuit 21 to generate a signal WP3 having a pulse width shorter than the write pulse signal WP and outputs it to a current switch control circuit 4. The current switch control circuit 4 converts the signal WP3 from the pulse generating circuit 2 and a write data signal WD into current switch control signals WIA, WIB to output to a current switch circuits 5, 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory circuit,
In particular, it relates to a semiconductor memory circuit having a PNP load type bipolar structure.

[0002]

2. Description of the Related Art A PNP load type memory cell is, for example, an SB.
Compared with the D-load type memory cell, it has an advantage that it has a smaller area, is resistant to soft errors, and consumes less power. Therefore, it is used for a RAM that requires relatively high integration. However, since the PNP load type memory cell uses the PNP transistor in a saturated state, it has a disadvantage that the writing speed is slow.

In the PNP load type memory cell, as shown in FIG. 4, the PNP transistors Q1 and Q2 and the output transistors Q3 to Q6 form a flip-flop type memory cell. Where C1 to C4
Is a parasitic capacitance of this memory cell, and Q7 and Q8 are write transistors.

In the PNP load type memory cell, PN is used.
P transistor Q1 and output transistor Q3, PNP
The transistor Q2 and the output transistor Q4 each form a half cell having a PNPN structure, and data can be held by cross-connecting the base and collector of each other.

The output transistor Q3 and write transistor Q7, the output transistor Q4 and write transistor Q8 form a current switch circuit together with the current sources IRW1 and IRW2, respectively. These write transistors Q7,
By changing the base signals WCA and WCB of Q8,
Writing to the memory cell is performed.

Writing to the PNP load type memory cell can be explained by charging and discharging the charges of the parasitic capacitances C1 to C4. Here, the writing of inverted data immediately after the read under the severest write condition will be described below.

When the memory cell is in the read state in the initial state of writing to the memory cell, P on the left side
A read current is flowing in the half cell of the NPN structure,
Transistor Q1 is in the deep saturation region ON state. A read current is flowing from the write transistor Q8 to the right bit line DB.

In this state, the cell base potential CA holds the low level, the cell base potential CB holds the high level, and the base signals WCA and WCB are located at the intermediate potential between them.

At this time, a large amount of charge is accumulated in the diffusion capacitance corresponding to the forward bias of the PNP transistor Q1 in the parasitic capacitance C1, and the parasitic capacitance C2 is in the PNP transistor Q.
A small amount of electric charge is stored in the diffusion capacitance corresponding to the forward bias of 2.

Further, the parasitic capacitance C3 has a cell base potential C.
A large amount of charge is accumulated in the diffusion capacitance corresponding to the potential difference between A and CB, and the parasitic capacitance C4 is stored in the cell base potentials CA and CB.
A small amount of charge is accumulated in the diffusion capacitance corresponding to the potential difference between the two.

In the first half region t1 of the write operation of the memory cell, the base signal WCA is set to a level higher than the cell base potential CB in order to write the inverted data, and the base signal WC is set.
B is set to a lower level than the cell base potential CA.

In the half cell of the PNPN structure on the right side, since the base signal WCB becomes low level, the output transistor Q
4 turns on, but this write current is the parasitic capacitance C3
, C4 discharge current. As the charging of the parasitic capacitance C2 progresses, the base current of the PNP transistor Q2 becomes dominant. As a result, the cell base potential CB drops to low level.

In the bit line DA on the left side, the write transistor Q7 is turned on at once and the write current is switched, but since the accumulated charge of the parasitic capacitance C1 at the time of saturation is still held, the cell base potential CB continues to be low level. It is still done.

As described above, the PNP transistors Q1 and Q
The period until 2 is turned on and the cell base potentials CA and CB are both at the low level is the first half region t1 of the write operation of the memory cell.

In the second half region t2 of the write operation of the memory cell, the PNP transistor Q1 must be turned off in order to complete the write, and therefore the parasitic capacitance C3,
It is necessary to charge C4 and discharge the parasitic capacitance C1. These charge and discharge currents are supplied from the collector of PNP transistor Q2.

Due to these charging and discharging, the potential of the cell base potential CA changes from low level to high level. The period from the first half region t1 of the write operation of the memory cell to the transition of the cell base potential CA to the high level is the second half region t2 of the write operation of the memory cell.

When the above-mentioned charging and discharging of the parasitic capacitances C1 to C4 are completed, the writing of the inverted data to the memory cells is completed.

As described above, the write operation is performed with the parasitic capacitance C1.
Since it is equivalently expressed as the movement of charging and discharging of C4, acceleration of charging and discharging can be considered as a measure for speeding up the writing operation.

Therefore, a method has been considered in which the write time is shortened by increasing the write current more than the read current. This method is disclosed in JP-A-58-704.
There is a technique disclosed in Japanese Patent Publication No. 83.

As a method of speeding up this writing operation,
As shown in FIG. 5, the memory cells (MC) are formed by the current switch circuits 5 and 6 connected to the bit lines DA and DB.
There is a method in which the current flowing from the memory cells 7-1 to 7-m at the time of writing is made larger than the current at the time of reading by switching the current flowing from 7-1 to 7-m.

In this case, the bit lines DA and DB pass through the bit line selection switches QSW1 and QSW2 and the constant current sources IR1 and IR2.
And write current sources IW1 and IW2 via current switch circuits 5 and 6.

The write controller 10 uses the write pulse signal WP.
And the write data signal WD is the write control circuit (WC) 3
The write timing and information are transmitted to the memory cells 7-1 to 7-m by the write control signals WCA and WCB converted by.

Further, the write control section 10 uses the current switch control signals WIA and WIB obtained by converting the write pulse signal WP and the write data signal WD by the current switch control circuit (WI) 4 into the current switch circuits 5 and 6.
To control.

The conversion of the write pulse signal WP and the write data signal WD into the write control signals WCA and WCB and the current switch control signals WIA and WIB by the write control circuit 3 and the current switch control circuit 4 is intended only for amplitude and level conversion. Done.

As shown in FIG. 6, the write control signals WCA, WCB and the current switch control signals WIA, WIB have the same timing on the front and rear edges, so that the current switch circuits 5, 6 within this time period.
Are switched to increase the write current of the memory cells 7-1 to 7-m. Incidentally, 8-1 to 8-n are the memory cells 7-1, respectively.
7-m is a memory cell column.

[0026]

The current amplification factor β _PNP of the PNP transistor greatly influences the write operation of the memory cell, which is equivalently represented by charging and discharging of the parasitic capacitance. In the first half region t1 of the write operation, the parasitic capacitance C3 must be discharged in order to change the cell base potential CB from the high level to the low level. Therefore, it is better that the supply from the collector of the PNP transistor Q1 in the ON state is smaller, that is, the current amplification factor β _PNP is smaller.

On the other hand, in the latter half region t2 of the write operation, the discharge of the parasitic capacitance C1 and the charge of the parasitic capacitance C3 are supplied from the collector of the PNP transistor Q2 which is already in the ON state in order to change the cell base potential CA to the high level. There is a need to.

Therefore, it is desirable that the current amplification factor β _PNP is large in the latter half region t2 of the write operation. That is, in order to speed up the write operation, the current amplification factor β in the large current region
_{The PNP} is required to have contradictory characteristics in the first half area t1 of the write operation and the second half area t2 of the write operation.

However, P used in the memory cell
The characteristic of the NP transistor is that the current amplification factor β _PNP decreases as the current increases in the large current region. Therefore, in the conventional method of increasing the write current at the same timing as the write pulse, the write current increases, so that the current is always maintained during the write period. The amplification rate β _PNP is small. Therefore, the write operation becomes faster in the first half area t1 of the write operation, but becomes slower in the second half area t2 of the write operation.

At present, the latter half region t2 of the write operation is more dominant in the breakdown of the write time. Therefore, considering the write time as a whole, even if the current at the time of write is greatly increased. There is a problem that speeding up is difficult.

Further, in the conventional method, the forward voltage VBE of the word driver output transistor and the PNP transistor in the memory cell is increased, and the memory cell potential is decreased accordingly. In the latter half region t2 of the write operation, even after the charge and discharge of the memory cell are completed, the potential drop does not restore the potential in the memory cell to the normal level, but remains in the lowered state.

When the write operation is returned to the read operation in this state, a so-called recovery time, which is the time until the lowered potential of the memory cell on the high level side is restored and becomes stable, has to be taken sufficiently, and the total amount is reduced. There is a problem that the write cycle time increases. further,
There is also a problem that the output waveform causes ringing.

Therefore, an object of the present invention is to solve the above problems, to provide a semiconductor memory circuit capable of speeding up a write operation and shortening a total write cycle time.

[0034]

A semiconductor memory circuit according to the present invention is a semiconductor memory circuit in which data is written by a write current flowing through a memory element in response to a write pulse signal. It is provided with means for increasing the current flowing when reading data from the element and control means for controlling the increase time of the write current to be a time shorter than the pulse width of the write pulse signal.

Another semiconductor memory circuit according to the present invention comprises a pair of drive transistor elements each having its base and collector cross-connected to each other, and a PNP transistor element connected as a load to the collector of the drive transistor. A plurality of memory cells, each of which is arranged in a matrix; a pair of bit lines to which the emitters of the drive transistor elements of the memory cells of the same column among the plurality of memory cells are commonly connected; and the pair of bit lines. A pair of write transistors having emitters connected to each other, and a current source for supplying a current to the pair of bit lines, respectively. The pair of write transistors is provided by applying a pulsed signal to the bases of the pair of write transistors. Is a semiconductor memory circuit that turns on and off to control writing to the memory cell. A means for increasing the write current of the bit line on the side that allows a current to flow from the memory cell at the time of the write operation than the current at the read time, and a pulsed signal for giving the time for increasing the write current to the base of the write transistor. And a means for controlling the pulse width to be shorter than the pulse width.

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention. In FIG. 5, one embodiment of the present invention is shown in FIG. 5 except that a pulse generation circuit (PG) 2 is provided in the write control unit 1.
The configuration is the same as that of the conventional example shown in FIG. 3, and the same components are designated by the same reference numerals. The operation of those same constituent elements is similar to the operation of the conventional example.

The gate circuit 20 of the pulse generating circuit 2 generates a normal signal and an inverted signal from the input write pulse signal WP, outputs the normal signal WP1 to the AND circuit 22, and delays the inverted signal by a delay circuit ( Delay) 21 is output.

The delay circuit 21 delays the inverted signal input from the gate circuit 20 for a predetermined time, and outputs the delayed signal WP2 to the AND circuit 22. The AND circuit 22 ANDs the normal signal WP1 from the gate circuit 20 and the signal WP2 delayed by the delay circuit 21 to generate a signal WP3 having a pulse width shorter than the write pulse signal WP to control the current switch. Output to circuit 4. The timing chart of FIG. 2 shows the operation of generating the signal WP3 by the AND circuit 22.

The current switch control circuit 4 converts the signal WP3 from the pulse generation circuit 2 and the write data signal WD into current switch control signals WIA, WIB and outputs them to the current switch circuits 5, 6.

The current switch circuits 5 and 6 are controlled by the current switch control signals WIA and WIB, and increase one of the currents of the bit lines DA and DB at the time of write operation to the memory cells 7-1 to 7-m. At this time, the increase time of the current is shorter than the writing time because the pulse width of the signal WP3 from the pulse generating circuit 2 is shorter than the write pulse signal WP.

That is, since it is the first half region t1 of the write operation that is speeded up by the increase of the current, the pulse generation circuit 2 continues until the first half region t1 of the write operation is completed.
A pulse of signal WP3 from is required. This signal WP
Since the pulse of 3 is unnecessary in the second half area t2 of the write operation, the pulse is finished immediately after the first half area t1 of the write operation is finished.

FIG. 3 is a circuit diagram showing the configuration of another embodiment of the present invention. In the figure, the other embodiment of the present invention has the same configuration as that of the embodiment of the present invention shown in FIG. 1 except that one current switch circuit 9 is used, and the same components are designated by the same reference numerals. There is. The operation of those same constituent elements is similar to the operation of the conventional example.

The current switch control circuit 4 creates the current switch control signals WIA and WIB to be at the same level when reading from the memory cells 7-1 to 7-m so that the currents flowing through the bit lines DA and DB are the same. To be

Further, the current switch control circuit 4 creates one of the current switch control signals WIA and WIB on the basis of the pulse of the signal WP3 from the pulse creation circuit 2 when writing to the memory cells 7-1 to 7-m, One of the transistors Q9 and Q10 of the current switch circuit 9 is turned on for a time shorter than the writing time. As a result, the current flowing through one of the bit lines DA and DB is increased for a time shorter than the write time.

As described above, the pulse generation circuit 2 and the current switch control circuit 4 allow the memory cells 7-1 to 7-7.
By controlling the write current to increase only in the first half region t1 of the write operation for -m, the write operation in the first half region t1 of the write operation can be speeded up, and the write operation in the second half region t2 of the write operation is also speeded up. can do.

Further, since the transition of the potentials of the memory cells 7-1 to 7-m to the normal level can be accelerated in a DC manner, the recovery time can be shortened and the total write cycle time can be greatly shortened. be able to.

[0048]

As described above, according to the present invention, the write current flowing in the memory element in response to the write pulse signal flows when the data is read from the memory element for a time shorter than the pulse width of the write pulse signal. By increasing the current more than the current, the write operation can be speeded up and the total write cycle time can be shortened.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a timing chart showing a pulse signal generation operation by the AND circuit of FIG.

FIG. 3 is a circuit diagram showing a configuration of another embodiment of the present invention.

FIG. 4 is a diagram for explaining a write operation of a PNP load type memory cell.

FIG. 5 is a circuit diagram showing a configuration of a conventional example.

6 is a timing chart showing a write control signal and a current switch control signal of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 write control unit 2 pulse creation circuit 3 write control circuit 4 current switch control circuit 5, 6, 9 current switch circuit 7-1 to 7-m memory cell 8-1 to 8-n memory cell column

Claims (4)

[Claims] 1. A semiconductor memory circuit in which data is written by a write current flowing through a memory element in response to a write pulse signal, wherein the write current is made larger than a current flowing when data is read from the memory element. 2. A semiconductor memory circuit comprising: means for controlling an increase time of the write current to be a time shorter than a pulse width of the write pulse signal. 2. The means for logically operating the write pulse signal and a signal obtained by inverting and delaying the write pulse signal, and generating a signal for controlling the increase time of the write current from the operation result. The semiconductor memory circuit according to claim 1, further comprising: 3. A pair of drive transistor elements each having a base and a collector cross-connected to each other, and a PNP transistor element connected as a load to the collector of the drive transistor, each arranged in a matrix. A plurality of memory cells, a pair of bit lines to which the emitters of the drive transistor elements of the memory cells of the same column among the plurality of memory cells are connected in common, and a pair of writing in which the emitters are connected to the pair of bit lines, respectively. A transistor and a current source for supplying a current to each of the pair of bit lines, and by applying a pulsed signal to the bases of the pair of write transistors, the pair of write transistors is turned on / off to turn on / off the memory cell. A semiconductor memory circuit for performing write control, comprising: Means for increasing the write current of the bit line on the side where the current flows from the read current, and the time for increasing the write current is shorter than the pulse width of the pulsed signal given to the base of the write transistor. A semiconductor memory circuit including means for controlling. 4. The control means logically operates the pulse-shaped signal and a signal obtained by inverting and delaying the pulse-shaped signal, and controls the time for increasing the write current based on the operation result. 4. The semiconductor memory circuit according to claim 3, comprising: