JPH07153275A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To shorten a writing time by generating a writing pulse in which a device characteristic of a memory cell is corrected. CONSTITUTION:A memory cell characteristic correction delay circuit 51 comprises a delay stage DEL1 which delays an output signal of a delay circuit 50, a delay stage DEL2 which delays an output signal of the DEL1, and a buffer stage DEL3 which delays an output signal of the DEL2. The DEL1 has circuit constitution equivalent delay to a writing amplifier, and an input clock is delayed by passing through the DEL1 during an equal time in which writing data is amplified by a writing amplifier. The DEL2 has circuit constitution DMS which imitates to the one memory cell of a memory cell array, and correction of a writing pulse in which a device characteristic of the memory cell is considered can be performed by arranging the DEL2. In the DEL2, a signal from the DMS can be read out through transfer MOSs 39, 41, this read-out signal is transmitted to the DEL 3, and transmitted to an AND circuit 52 as an output signal of the circuit 51.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and further to a write pulse generation technique for controlling the operation of a write amplifier in the semiconductor memory device, which is applied to, for example, a static random access memory (abbreviated as SRAM). And effective technology.

[0002]

2. Description of the Related Art For example, in an SRAM having a plurality of static memory cells arranged in a matrix, the select terminals of the memory cells are connected to word lines in each row direction.
Data input / output terminals of memory cells are coupled to complementary data lines (also referred to as complementary bit lines) in each column direction. Each complementary data line is commonly connected to the complementary common data line via a Y selection switch circuit including a plurality of column selection switches which are coupled to the complementary data line in a one-to-one relationship. In such an SRAM, a write amplifier for taking in write data to the memory cell from the outside is provided. The operation of this write amplifier is controlled by a write pulse obtained by delaying the clock by a predetermined time. A write pulse generation circuit for generating such a write pulse has a delay circuit in which a switching node of a bipolar ECL (emitter coupling logic) is provided with a capacitor, is connected in multiple stages, and its delay output and an input to the delay stage are connected. It is configured by combining an AND circuit that obtains a logical product with a clock.

An example of a document describing SRAM is "LSI Handbook (starting from page 500)" issued by Ohmsha on November 30, 1984.

[0004]

However, as described above, the delay circuits each having a capacitor attached to the switching node of the bipolar ECL are coupled in multiple stages, and the logical product of the delay output and the input clock to the delay stage is obtained. In the write pulse generating circuit formed by combining the AND circuits for obtaining the above, when the memory cell formed by the CMOS transistor is applied, it is difficult to generate the write pulse that compensates for the device characteristic of the MOS transistor. Become. Therefore, when a memory cell is composed of MOS transistors, it is necessary to make the operation margin at the time of writing relatively large, which is the main factor that hinders the shortening of the writing time. Have been found by others.

An object of the present invention is to provide a technique for reducing the write time by generating a write pulse that compensates for the device characteristics of the memory cell.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, a write pulse generation circuit for generating a pulse for operation control of a write amplifier is constituted by including a memory characteristic compensating means for compensating for a signal delay characteristic caused by the structure of a memory cell. . At this time, the memory characteristic compensating means can be configured to include a delay circuit having a storage node equivalent to the memory cell. Furthermore, in a specific aspect, the memory characteristic compensation means is
A storage node having the same structure as the storage node of the memory cell,
A first port capable of taking in a signal to the storage node; and a second port capable of reading out a signal taken into the storage node via the first port, and a signal given from the first port The output can be delayed and output from the second port.

[0009]

According to the above means, the memory cell characteristic compensating means compensates the signal delay characteristic caused by the configuration of the memory cell when generating the pulse signal for controlling the operation of the write amplifier. This makes it possible to generate a write pulse in which the device characteristics of the memory cell are compensated, and it is possible to shorten the write time by eliminating the need to secure a margin more than necessary.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 shows a static RAM which is an embodiment of the present invention. Although not particularly limited, the SRAM shown in the figure is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.

In FIG. 3, reference numeral 6 denotes a memory cell array in which a plurality of static memory cells are arranged in a matrix. Select terminals of the memory cells are connected to word lines in each row direction, and data input / output terminals of the memory cells are column columns. Each direction is coupled to a complementary data line. Each complementary data line is commonly connected to the complementary common data line via a Y selection switch circuit 9 including a plurality of column selection switches coupled to the complementary data line in a one-to-one relationship.

Address signals A0-A input from the outside
Among n, A0 to Am are transmitted to the X decoder 4 via the address buffers 1-0 to 1-m arranged correspondingly. Address signals Am + 1 to An are transmitted to Y decoder 8 via address buffers 1-m + 1 to 1-m arranged corresponding to them. The X driver 5 drives the word line corresponding to the input address signal to the selection level based on the decoded output of the X decoder 4. When a predetermined word line is driven, the memory cell coupled to this word line is selected. The Y decoder 8 also generates a selection signal for the Y selection switch circuit 9 corresponding to the address signal supplied thereto. This selection signal is transmitted to the Y selection switch circuit 9 via the Y driver 2. Then Y
By the selection operation of the selection switch circuit 9, the data line is selectively conducted to the common data line. At this time, the potential of the complementary common data line is amplified by the read amplifier 11 and can be output to the outside. Further, when write data is externally applied to the write amplifier 10, the complementary common data line is driven according to the write data, whereby the data is written to a predetermined memory cell via the complementary data line selected by the address signal. The corresponding charge information is accumulated.

The write amplifier 10 is controlled by a write pulse generation circuit 12. The write pulse generating circuit 12 is not particularly limited, but the system clock C
A signal (write pulse) for activating the write amplifier is generated based on LK. The write pulse and the write enable signal WE * for instructing the write operation from the outside are input to the WE driver 3, and the logical product of them is obtained here. Although not particularly limited, when the write pulse is asserted to the high level and the write enable signal WE * is asserted to the low level, data can be taken in. That is, the data applied to the data external terminal is amplified by the write amplifier 10 and transmitted to the complementary common data line. The writing time to the memory cell is restricted by the width of this writing pulse. If the write pulse width is too narrow, the write time will be insufficient and the write will be insufficient. Therefore, it is necessary to optimize the write pulse width in consideration of the characteristics of the memory cell. In the present embodiment, the write amplifier 10
The write pulse generation circuit 12 for activating the memory cell includes a memory characteristic compensating means for generating a write pulse in which the device characteristic of the memory cell included in the memory cell array 6 is compensated. Specifically, as will be described below, this means is formed by a delay circuit equivalent to an actual memory cell, in other words, a circuit simulating the memory cell, thereby optimizing the write time. .

Next, a detailed configuration of each part will be described.

FIG. 4 shows a detailed configuration example of the memory cell array 6.

In FIG. 4, a plurality of static memory cells forming the memory cell array 6 have the same structure. That is, as shown representatively in the same figure, the memory cell MS includes an inverter formed of a p-channel type MOS transistor Q10 and an n-channel type MOS transistor Q14, a p-channel type MOS transistor Q20 and an n-channel type MOS transistor Q16. Is connected in a loop shape and is connected to complementary data lines D1A and D1B * via n-channel MOS transistors Q13 and Q15, respectively. The control terminals of the MOS transistors Q13 and Q15 are coupled to the corresponding word lines (W1, W2, ...), and when the word line is driven to the selection level, the MOS transistors Q13 and Q15 coupled thereto are turned on. It has become so. A negative potential VEE with respect to the ground GND is supplied as an operation power source of the memrist MS. As described above, the memory cell of the SRAM of this embodiment is
Although it is composed of MOS transistors, other circuit parts are formed of bipolar transistors except for a pseudo memory cell DMS described later.

FIG. 1 shows a configuration example of a write pulse generation circuit 12 which generates a write pulse for controlling the operation of the write amplifier 10.

The write pulse generation circuit 12 has a delay circuit 50 for delaying the clock CLK and a memory cell characteristic compensation delay circuit 51 for compensating the delay output.
And an AND circuit 5 for obtaining a logical product of the output signal of the memory cell characteristic compensation delay circuit 51 and the input clock.
Including 2 and. Clock C input to the delay circuit 50
LK is not particularly limited, but the input clock CLK
Are clocks of complementary levels. Then, after such an input clock CLK is delayed by the delay circuit 50, further compensated for the memory cell characteristic by the memory cell characteristic compensation delay circuit 51 in the subsequent stage, and signal-delayed, the AND circuit 52 takes the logical product, A write pulse having a predetermined pulse width is generated. This output pulse is transmitted to the write amplifier 10 shown in FIG.

According to the conventional technique, the write pulse is obtained by connecting delay circuits each having a capacitor attached to the switching node of the bipolar ECL in multiple stages, and the logical product of the delay output and the input clock to the delay stage. It is generated by obtaining, but when the one formed by the CMOS transistor is applied to the memory cell,
Due to the difference in characteristics between the MOS transistor and the bipolar transistor, it becomes difficult to generate a write pulse that compensates for the device characteristics of the MOS transistor. Therefore,
In this embodiment, by providing the memory cell characteristic compensation delay circuit 51, it is possible to generate a write pulse in which the memory characteristic is compensated.

FIG. 2 shows a memory cell characteristic compensation delay circuit 51.
The detailed circuit configuration of is shown.

As shown in FIG. 2, the memory cell characteristic compensation delay circuit 51 includes a first delay stage DEL1 for delaying the output of the delay circuit 50 of FIG. 1 and the first delay stage DEL1. The first delay stage DEL1 is arranged in the latter stage.
A second delay stage DEL2 for delaying the output signal of
Further, it includes a buffer stage DEL3 which is arranged after the second delay stage DEL2 and delays the output signal of the second delay stage DEL2.

The first delay stage DEL1 has a circuit equivalent to the circuit configuration of the write amplifier 10 shown in FIG. 1, that is, a circuit configuration simulating the write amplifier 10. That is, the first delay circuit DE simulating the write amplifier 10
By passing through L1, the input clock CLK is delayed by a time equal to the time when write data is received by the write amplifier 10.

The first delay stage DEL1 is constructed as follows.

Npn type bipolar transistors 21, 2
2 is provided, and its emitter electrode has a constant current source 35,
36 are joined. The emitter electrodes of the npn-type bipolar transistors 21 and 22 are respectively coupled to the base electrodes of the npn-type bipolar transistors 23 and 24 in the subsequent stage and the npn-type bipolar transistors 31 and 32 in the output stage. The npn-type bipolar transistors 23 and 24 and the npn-type bipolar transistors 31 and 32 are differentially coupled, and their emitter electrodes are coupled to the constant current sources 34 and 33. Also,
The collector electrodes of the npn-type bipolar transistors 23 and 24 are load resistors 25 and 26 and the capacitor 2 respectively.
7 and 28 are coupled to the ground GND, and npn-type bipolar transistors 29 and 30 in the subsequent stage are connected.
Is coupled to the base electrode of the. The emitter electrodes of the npn bipolar transistors 29 and 30 are
The second delay stage DEL2 is coupled to the collector electrodes of the n-type bipolar transistors 31 and 32.
Signal output to.

The second delay stage DEL2 has a circuit configuration simulating one memory cell MS in the memory cell array 6. By disposing such a second delay stage DEL2, it is possible to compensate the write pulse in consideration of the device characteristics of the memory cell MS.

The second delay stage DEL2 is composed of MOS transistors as follows.

The inverter composed of the p-channel type MOS transistor 43 and the n-channel type MOS transistor 44 and the inverter composed of the p-channel type MOS transistor 45 and the n-channel type MOS transistor 46 are connected in a loop to form the memory. Pseudo memory cells DMS corresponding to the memory cells MS in the cell array 6 are formed. In addition, complementary data lines D1A, D1B * and D2 in the memory cell array 6 are also provided.
Pseudo data line pair DA, DB corresponding to A, D2B *, etc.
* Is provided, which is the transfer MOS4
0 and 42 are coupled to the storage node of the pseudo memory cell DMS. Then, constant current sources 71 and 72 are coupled to the pseudo complementary data lines DA and DA *, respectively, and npn bipolar transistors 38 and 47 are coupled to the npn bipolar transistors 38 and 47.
The base electrode of the first delay stage DEL1 is coupled to the output terminal of the first delay stage DEL1.
The pseudo pseudo complementary data lines DA and DA * can be driven based on the output of.

Further, in this second delay stage DEL2,
Transfer MOSs 39 and 41 are provided as a second port, and signals can be read from the pseudo memory cell DMS via the transfer MOSs 39 and 41. The drain electrodes of the tri-state MOS 39, 40, 41, 42 are the word lines W1 and W of the memory cell array 6.
2 is connected to the pseudo word line DWL simulating 2. This pseudo word line DWL is not particularly limited, but is always at high level. Therefore, tri-state MOS4
Immediately after writing a signal to the pseudo memory cell DMS via 0, 42, the read operation from the pseudo memory cell DMS is enabled via the tri-state MOS 39, 41. That is, immediately after the logic state of the storage node of the pseudo memory cell DMS is inverted in accordance with the output signal of the first delay stage DEL1, the logic inversion state can be read via the transfer MOSs 39 and 41. it can. Therefore, it is possible to delay the write pulse according to the characteristics of the actual memory cell MS. The read signal is then transmitted to the buffer stage DEL3.

The buffer stage DEL3 is constructed as follows. Differentially coupled npn-type bipolar transistors 61 and 63 are provided, and resistors 64 and 6 are provided as loads thereof.
5 are provided. The collector electrodes of the npn-type bipolar transistors 61 and 63 are coupled to the base electrodes of the npn-type bipolar transistors 66 and 67 in the subsequent stage to enable differential signal transmission. The emitter electrodes of the npn bipolar transistors 66 and 67 are coupled to the negative-side power supply VTT via the resistors 68 and 69, so that signals can be output from the emitter electrodes. The output out of the buffer stage DEL3 is transmitted to the AND circuit 52 shown in FIG. 1 as an output signal of the memory cell characteristic compensation delay circuit 51.

According to the above embodiment, the following operational effects can be obtained.

(1) In order to generate the operation control pulse of the write amplifier by including the memory cell characteristic compensation delay circuit 51 as the memory characteristic compensation means for compensating the signal delay characteristic caused by the configuration of the memory cell MS. By configuring the write pulse generation circuit 12 of, the signal delay characteristic due to the configuration of the memory cell MS is compensated in the generation of the write pulse. By thus compensating for the signal delay characteristic, the write time to the memory cell MS can be optimized, and it is not necessary to secure a margin more than necessary, so that the write time is shortened. be able to. For example, the maximum value of the write pulse width can be shortened by about 10% of the cycle time, and in that case, the write cycle time can be shortened by 300 ps (picosecond). Such an effect is particularly useful in SRAMs that require high speed.

(2) A memory having the action and effect of the above (1) by applying a delay circuit equivalent to the memory cell MS and delaying the write pulse for controlling the operation of the write amplifier 10 by the delay circuit. Characteristic compensation means can be formed.

(3) A pseudo memory cell DMS including a storage node having the same structure as the storage node of the memory cell MS is provided to form a first port capable of taking in a signal to the storage node of the pseudo memory cell DMS. Transfer M
The OSs 40 and 42 are provided, and the transfer MOSs 39 and 41 for forming the second port capable of reading the signal taken into the storage node via the first port are provided. Since the read operation is enabled, the delay characteristic of the write pulse due to the original configuration of the memory cell MS can be accurately compensated. In particular, since the pseudo memory cell DMS is formed in the same step as the actual memory cell MS, it has the same characteristics as the actual memory cell MS, and is therefore extremely effective as a memory cell characteristic compensation means.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and it goes without saying that various modifications can be made without departing from the scope of the invention. Yes.

For example, the structure of the pseudo memory cell DMS is as follows.
It can be appropriately changed according to the actual configuration of the memory cell MS.

In the above description, SRA, which is the field of application behind the invention made mainly by the present inventor, is the background.
Although the case of application to M has been described, the present invention is not limited to this and can be applied to various semiconductor memory devices.

The present invention can be applied on the condition that at least a write amplifier for writing data in a memory cell is included.

[0038]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, since the memory cell characteristic compensating means compensates the signal delay characteristic due to the configuration of the memory cell, it is possible to generate the write pulse in which the device characteristic of the memory cell is compensated. As described above, since it is possible to generate a write pulse that compensates for the device characteristics of the memory cell, it is not necessary to secure a margin more than necessary, and the write time can be shortened accordingly.

[Brief description of drawings]

FIG. 1 is a main logical configuration diagram of a write pulse generation circuit included in an SRAM which is an embodiment of the present invention.

FIG. 2 is a detailed configuration circuit diagram of a memory cell characteristic compensation delay circuit included in the write pulse generation circuit.

FIG. 3 is an overall configuration block diagram of the SRAM.

FIG. 4 is a detailed configuration circuit diagram of a memory cell included in the SRAM.

[Explanation of symbols]

 1-0 to 1-m address buffer 2 Y driver 3 WE driver 4 X decoder 5 X driver 6 memory cell array 8 Y decoder 9 Y selection switch circuit 10 write amplifier 11 read amplifier 50 delay circuit 51 memory cell characteristic compensation delay circuit DEL1 1 delay stage DEL2 2nd delay stage DEL3 buffer stage

Claims (3)

[Claims] 1. A semiconductor memory device including a write amplifier for writing data to a memory cell, and a write pulse generation circuit for generating a write pulse for controlling the operation of the write amplifier. Is a semiconductor memory device including a memory characteristic compensating means for compensating a signal delay characteristic caused by the configuration of the memory cell. 2. A semiconductor memory device comprising a write amplifier for writing data to a memory cell, and a write pulse generation circuit for generating a write pulse for controlling the operation of the write amplifier. Includes a memory characteristic compensating means for compensating for a signal delay characteristic caused by the configuration of the memory cell, and the memory characteristic compensating means includes a delay circuit having a storage node equivalent to the memory cell. And semiconductor memory device. 3. A semiconductor memory device comprising a write amplifier for writing data to a memory cell, and a write pulse generation circuit for generating a write pulse for controlling the operation of the write amplifier. Includes memory characteristic compensating means for compensating a signal delay characteristic due to the configuration of the memory cell, the memory characteristic compensating means including a memory node having a configuration equal to the memory node of the memory cell, and A first port capable of receiving a signal; and a second port capable of reading a signal captured by the storage node via the first port, and delaying the signal supplied from the first port A semiconductor memory device characterized in that it can be output from a second port.