JPH11126482A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which the writing efficiency of a memory node is improved. SOLUTION: This device is provided with memory cell arrays 7-9, word driver circuits 1-3 outputting row selection signals 117-119 to each memory cell, differential amplifier blocks 4-6 amplifying and outputting a data signal read out to a bit line, a YSW driver circuit 10 outputting a column selection signal 116, differential amplifier power source signal generating circuits 11-13 outputting differential amplifier power source signals 107/108, 109/110, 111/112 to differential amplifier blocks 4-6, a differential amplifier start signal generating circuit 14 outputting a differential amplifier start signal 113, a differential amplifier activation signal generating circuit 15 outputting a differential amplifier activation signal 114 activating each differential amplifier power source signal generating circuit, and restoring one shot signal generating circuit 16 outputting an one shot pulse signal at the time of fall of the differential amplifier activating signal 114.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device.

[0002]

2. Description of the Related Art FIG. 9 is a block diagram showing a configuration around a memory cell array in an example of a conventional semiconductor memory device. As shown in FIG. 9, in this conventional example, the memory cell arrays 7, 8, and 9 provided in three blocks and the data held in each of these memory cell arrays are read out by the repetitive configuration of the memory cells. In order to output row selection signals 117, 118 and 119 for driving gate electrodes of arbitrary cell transistors to corresponding memory cell arrays, word driver circuits 1, 2 and 3 provided in three blocks are provided.
And differential amplifier blocks 4, 5 and 6 for amplifying and outputting the data signal of the storage node read to the bit line to the power supply level in correspondence with each of the memory cell arrays.
A YSW driver circuit 10 for generating and outputting a column selection signal 116 for transmitting a data signal on an arbitrary digit line pair in a bit line pair on which differential amplification is performed to a read / write input / output terminal; , A word activation start signal 106 and a row control signal reset signal 106, and a differential amplifier start signal generating circuit 14 for generating and outputting a differential amplifier start signal 113, a differential amplifier start signal 113 and an active area A differential amplifier activating signal generating circuit 15 for generating and outputting a differential amplifier activating signal 114 for activating each differential amplifier power signal generating circuit in response to the input of the selection signal 104; Upon receiving the signal 114 and the corresponding power supply signal generation circuit selection signals 101, 102 and 103, the differential amplifier block 4 Correspond to 5 and 6, respectively differential amplifier power signal generator circuit 11, 12 and 13 outputs a differential amplifier power signal 107/108, 109/110 and 111/112, and includes.

FIG. 10 is a circuit diagram showing a configuration of a differential amplifier power signal generating circuit 11 arranged corresponding to the differential amplifier block 4 in FIG. 9, and FIG. FIG. 12 is a block diagram showing the configuration of the differential amplifier start signal generation circuit 14. FIG. 13 is a block diagram showing the configuration of the differential amplifier start signal generation circuit 14. FIG. 3 is a circuit diagram illustrating a configuration.

In the following description of the operation, only the memory cell array 7, the corresponding word driver circuit 1, the differential amplifier block 4, and the differential amplifier power supply signal generation circuit 11 are extracted, and the differential circuit associated therewith is extracted. The operation including the amplifier start signal generation circuit 14 and the differential amplifier activation signal generation circuit 15 will be described. Other memory cell arrays 8 and 9 and the word driver circuit 2 corresponding to these memory cell arrays 8 and 9 will be described. , 3, differential amplifier blocks 5, 6 and differential amplifier power signal generation circuit 1
Descriptions of the operations 2 and 13 will be omitted to avoid duplication.

First, FIG. 9, FIG. 10, FIG. 11, FIG. 12, and FIG.
The operation of the conventional example will be described with reference to the operation timing diagrams of (d), (e), (f), (g) and (h). First, the differential amplifier start signal generation circuit 14 shown in FIG. 12 receives the input of the word activation start signal 105 and the row control signal reset signal 106 (FIG. 14).
(See (a) and (c)), inverter 57, NAND
The logic processing of the circuit 58 and the inverter 59 is performed, and the output thereof is connected to cascade-connected delay circuits 60 and 61,
The signals are input to delay circuits 62 and 63 which are also connected in cascade. The delayed output signals of delay circuits 60 and 61 are PMO
The gates of S transistor 64 and PMOS transistor 66 are input to the gates, and the delay output signals of delay circuits 62 and 63 are input to the gate of PMOS transistor 65. A differential amplifier start signal 113 is output from the differential amplifier start signal generation circuit 14 via these PMOS transistors and the inverter 67 (FIG. 14).
14 (a), (c) and (d), as apparent from FIGS. 14 (a), (c) and (d), corresponding to the input of the falling of the row control signal reset signal 106 and the rising of the word activation start signal 105, The differential amplifier start signal 113 rises to “H” level and is output (see FIG. 14D).

The differential amplifier start signal 113 is input to the differential amplifier activation signal generation circuit 15, and the differential amplifier activation signal generation circuit 15 also receives the "H" level active region selection signal 104. 14 (see FIG. 14B), and as shown in FIG. 13, these differential amplifier start signal 113 and active area selection signal 104 are NAN.
The logical product is obtained by the D circuit 68, and the output signal is inverted by the inverter 69 and output as the "H" level differential amplifier activation signal 114 (FIG. 14 (e)).
), And is input to the differential amplifier power signal generation circuit 11. The differential amplifier power supply signal generation circuit 11 having the configuration shown in FIG. 10 receives the input of the “H” level power supply signal generation circuit selection signal 101 and the above-described “H” level differential amplifier activation signal 114. , A NAND circuit 49 and an inverter 50 output a logical processing signal.
The transistor 53 forms a differential amplifier pair. The drain is input to the gate of the NMOS transistor 52 that functions to supply the ground potential of the differential amplifier power signal 108. The logical processing output signal from the NAND circuit 49 is PMOS transistor 5 which functions to supply the power supply level of differential amplifier power supply signal 107
3 is input to the gate. Initially, the PMOS transistor 53 and the NMOS transistor 52 forming the differential amplifier pair are not in the ON state until the differential amplifier activation signal 114 becomes “H” level. And differential amplifier power signal 1 at each drain of NMOS transistor 52
07 and 108 indicate that both the power supply signal generation circuit selection signal 101 and the differential amplifier activation signal 114 are "L".
Between the levels, the PMOS transistor 53 and the NMOS transistor 52 are in a floating state while the potential of the balanced power supply level _Vb is maintained when the NMOS transistor 52 is in the balanced state. After that, FIG.
As shown in (e), the differential amplifier activation signal 114
Rises to the “H” level, both the PMOS transistor 53 and the NMOS transistor 52 that have been in the OFF state are turned ON, and the potential level of the power supply voltage V _CC is changed via the PMOS transistor 53 to the differential amplifier power supply. It is output as the level of the signal 107 and
The ground potential level is output as differential amplifier power supply signal 108 via S transistor 52.

Next, FIGS. 9 and 10 and FIGS. 15 (a), (b), (c), (d), (e),
(F), (g), (h), (i), (j), (k),
Referring to the operation timing diagrams of (l), (m) and (n), the bit line pair 30-0 shown in FIG.
The operation when writing cell data “H” level to storage node C _S0 inside memory cell 33-0 will be described. Needless to say, the operation of the other bit line pairs 30-2 to 30-n relating to the storage nodes inside the memory cells is exactly the same. When writing cell data to storage node C _S0 , cut-off signal 126 at “H” level
, A pair of NMOS transistors each having the cut-off signal 126 as a gate input are in an ON state. The row selection signal 117 output from the word driver circuit 1 (see FIG. 9: the row selection signal 117 includes
When the row selection signal 117-0 included in the row selection signals 117-0 to 117-k is input at the “H” level (see FIG. 15A), the YSW driver circuit 10 The input column selection signal 116 (FIG. 9)
Reference: The column selection signal 116 includes the column selection signal 11
When the column selection signal 116-0 included in 6-0 to 116-n becomes “H” level (FIG. 15)
(See (d)), the "H" level data signal 120 and the "L" level data signal 121 at the read / write input / output terminals are supplied to the digit contacts 128 and 129 through the differential amplifier contacts 130 and 131, respectively ( 15 (e), (f), (j), (k),
(Refer to (l) and (m)), “H” level cell data is supplied to the storage node C _S0 via the cell transistor CT ₀ via the digit contact 128 to which the cell transistor CT ₀ is connected. (FIG. 15 (n)
reference). Then, after a while, the row selection signal 117
−0 transitions to the “L” level, and when the row selection signal 117-0 transitions to the “L” level, the value of the “H” level supplied to the storage node C _S0 changes to the storage data signal. Is stored in the storage node C _S0 (see FIG. 15).
(See (n)), and the operation of writing the “H” level cell data into the storage node C _S0 ends. Then, after the data writing is completed, the precharge signal 127 is prepared in preparation for the writing or reading operation in the next cycle.
A predetermined standby potential is supplied to the digit line pair 30-0 via the balance circuit 32 having the input as the input.

[0008]

In the above-mentioned conventional semiconductor memory device, when writing the retained data signal to the storage node, the resistance of the contact hole is increased due to the miniaturization of the semiconductor chip. As a result, the efficiency of writing data to the storage node is reduced, so that a sufficient amount of electric charge cannot be supplied to the storage node, and there is a disadvantage that a data writing failure is likely to occur.

Further, in order to avoid this drawback, when performing sufficient data writing, there arises a drawback that the operating frequency must be lowered, and there is a drawback that it is not possible to meet the demand for high-speed operation.

[0010]

According to the present invention, there is provided a semiconductor memory device comprising a differential amplifier and an amplifier associated with an arbitrary number of memory cell arrays.
In a semiconductor memory device including a peripheral circuit block that supplies a predetermined differential amplifier power signal to a block, in a certain period before and after a data write operation performed on a storage node in the memory cell, A differential amplifier power signal correction means for raising the potential level of the differential amplifier power signal supplied to the differential amplifier block to a higher potential level than the normal power voltage level and supplying the same to at least the peripheral circuit; It is characterized by being provided in a block.

The differential amplifier power signal correction means receives an input of a signal for activating the differential amplifier,
A restore one-shot signal generation circuit may be configured to generate and output a restore one-shot pulse signal having a pulse width for a certain period before and after the end of the data write operation and a higher potential level than the normal potential level. .

Further, for the differential amplifier block,
As a peripheral circuit block for supplying a predetermined differential amplifier power signal, a differential amplifier start signal generating circuit for receiving a word activation start signal and a row control signal reset signal, generating and outputting a differential amplifier start signal, A differential amplifier activation signal generating circuit that receives the differential amplifier start signal and the active region selection signal, generates and outputs a differential amplifier activation signal, and receives the differential amplifier activation signal. And a restore one-shot signal generating circuit for generating and outputting a restore one-shot pulse signal, and inputting the differential amplifier activation signal and the restore one-shot pulse signal, and respectively corresponding to an arbitrary number of differences. And an arbitrary number of differential amplifier power supply signal generation circuits for generating and outputting a predetermined differential amplifier power supply signal to the operational amplifier block. The restore one-shot signal generation circuit further includes a first delay circuit that delays and outputs the differential amplifier activation signal by a predetermined time, and a first inverter that inverts and outputs a delay output signal of the delay circuit. , And a first NOR circuit that performs a logical sum of the inverted output signal of the inverter and the differential amplifier activation signal and outputs the result.

Further, the differential amplifier power signal generation circuit includes:
Receiving a power signal generation circuit selection signal for selecting the differential amplifier power signal generation circuit, the differential amplifier activation signal and the restore one-shot pulse signal, and receiving the power signal generation circuit selection signal; A first NAND circuit that outputs a logical product of the differential amplifier activation signal and a second NAND circuit that inverts and outputs the differential amplifier activation signal
And an AND of the power supply signal generation circuit selection signal, the restore one-shot pulse signal, and the inverted output signal of the second inverter.
A first type 1 conductivity type field effect transistor having a source supplied with a normal power supply voltage and a gate receiving an output signal of the second NAND circuit; A third inverter for inverting and outputting an output signal; a drain connected to a second output terminal of the differential amplifier power signal; a gate to which an inverted output signal of the third inverter is input; A first type 2 conductivity type field effect transistor to which a potential is supplied;
A fourth signal for inverting and outputting the power signal generation circuit selection signal;
And the drain is connected to the drain of the first type 1 conductivity type field effect transistor, the inverted output signal of the fourth inverter is input to the gate, and the source is the first type 2 conductivity type field effect transistor. A second second conductivity type field effect transistor connected to the drain of the first field effect transistor; a drain connected to the drain of the first first conductivity type field effect transistor;
A second type conductive field effect transistor, connected to the gate of the second type conductive field effect transistor, and having a source supplied with balanced power, a balanced type power source supplied to the drain, and a gate connected to the second type conductive field effect transistor. A second second conductivity type field effect transistor connected to the gate of the second second conductivity type field effect transistor and having a source connected to the drain of the first second conductivity type field effect transistor; A power supply voltage higher than a normal power supply voltage level is supplied to a source, an output signal of the first NAND circuit is input to a gate, and a drain is a first output terminal of the differential amplifier power supply signal. , A fifth inverter for inverting and outputting an output signal of the first NAND circuit, and a source connected to the first first conductivity type. A third first-type conductive element connected to a drain of the field-effect transistor, a gate to which an inverted output signal of the fifth inverter is input, and a drain connected to a first output terminal of the differential amplifier power signal; And a field-effect transistor.

The differential amplifier start signal generating circuit receives the row control signal reset signal, inverts and outputs the sixth inverter, and outputs the word activation start signal and the sixth inverter. A third NAND circuit that takes the logical product of the inverted output signal and outputs the result, a seventh inverter that inverts and outputs the output signal of the third NAND circuit, and an inverted output signal of the seventh inverter. A second delay circuit for delaying the output, third and fourth delay circuits connected in cascade and delaying and outputting the inverted output signal of the seventh inverter, and a normal power supply voltage at the source. A fourth type 1 conductivity type field effect transistor, which is supplied to the gate and receives the delayed output signal of the second delay circuit, and a source which is a drain of the fourth type 1 conductivity type field effect transistor. Connected to down, the gate fourth
A fifth type 1 conductivity type field effect transistor to which a delay output signal of the delay circuit is input, and a source connected to the fifth first type.
Connected to the drain of a seed conductivity type field effect transistor,
A sixth type 1 conductivity type field effect transistor having a gate to which a delay output signal of the second delay circuit is input and a drain connected to the ground potential, and an input terminal having the fourth type 1 conductivity type. A drain of the field effect transistor and a connection point between the fifth type 1 conductivity type field effect transistor;
And an eighth inverter that outputs the differential amplifier start signal from an output terminal. The differential amplifier activation signal generation circuit may include the differential amplifier start signal and the differential amplifier active signal. And a ninth inverter for inverting and outputting an output signal of the fourth NAND circuit.

[0015]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. As shown in FIG. 1, in the present embodiment, three blocks of memory cell arrays 7, 8, and 9 are provided.
And outputting row selection signals 117, 118 and 119 for driving the gate electrodes of arbitrary cell transistors to the corresponding memory cell arrays when reading the stored data stored in each of the memory cell arrays. Therefore, word driver circuits 1, 2, and 3 provided in three blocks and a differential amplifier for amplifying and outputting a data signal of a storage node read to a bit line to a power supply level corresponding to each of the memory cell arrays are output. Amplifier·
Blocks 4, 5 and 6 and a column select signal 116 for transmitting a data signal on an arbitrary digit line pair in a bit line pair performing a differential amplification operation to a read / write input / output terminal, and output the same. A differential amplifier start signal generating circuit 14 which receives a word activation start signal 106 and a row control signal reset signal 106, generates and outputs a differential amplifier start signal 113, and a differential amplifier Upon receiving the start signal 113 and the active area selection signal 104, the differential amplifier activation signal generation circuit 15 generates and outputs a differential amplifier activation signal 114 for activating each differential amplifier power signal generation circuit.
And a restore one-shot signal generating circuit 16 that receives the input of the differential amplifier activation signal 114 and outputs a one-shot pulse signal 115 when the differential amplifier activation signal 114 falls, Signals 114, one-shot pulse signal 115, and corresponding power supply signal generation circuit selection signals 101, 102, and 103 are input, and differential amplifier power supplies are supplied to differential amplifier blocks 4, 5, and 6, respectively. Signals 107/108, 1
And a differential amplifier power supply signal generation circuit 11, 12 and 13 for outputting 09/110 and 111/112. As is clear from the comparison with the conventional example of FIG. 9, in the present embodiment, unlike the conventional example, a restore one-shot signal generation circuit 16 is newly added. The output one-shot pulse signal 115 is input to each differential amplifier power supply signal generation circuit.

FIG. 2 is a diagram showing a differential amplifier and a differential amplifier in FIG.
FIG. 3 is a circuit diagram showing a configuration of a differential amplifier power signal generation circuit 11 arranged corresponding to the block 4, and FIG.
FIG. 4 is a circuit diagram showing the configuration of the differential amplifier start signal generation circuit 14; FIG. 13 is a configuration diagram of the differential amplifier activation signal generation circuit 15; FIG. 6 is a circuit diagram showing a configuration of the restore one-shot signal generation circuit 16. As shown in FIG.

In the following description of the operation, only the memory cell array 7, the corresponding word driver circuit 1, the differential amplifier block 4, and the differential amplifier power supply signal generation circuit 11 are extracted as in the case of the conventional example. The operation including the differential amplifier start signal generation circuit 14, the differential amplifier activation signal generation circuit 15, and the restore 1 shot signal generation circuit 16 related thereto will be described, and the other memory cell arrays 8 and 9 will be described. The description of the operations of the word driver circuit, the differential amplifier block, the differential amplifier power signal generation circuit, and the like corresponding to these memory cell arrays will be omitted to avoid duplication.

In the following, first, the configuration diagrams of FIGS. 1, 2, 3, 4, 5, and 6, and FIGS.
With reference to the operation timing diagrams of (b), (c), (d), (e), (f), (g), and (h), the operation of the circuit components around the memory cell in the present embodiment Will be described.

First, in the differential amplifier start signal generating circuit 14 shown in FIG.
And the row control signal reset signal 106 (see FIGS. 7A and 7C), the inverter 34, the NAN
The logic processing of the D circuit 35 and the inverter 36 is performed,
The output is input to a delay circuit 37 and cascade-connected delay circuits 38 and 39. The delay output signal of the delay circuit 37 is input to the gates of the PMOS transistor 40 and the PMOS transistor 42, and the delay circuits 38 and 3
9 is input to the gate of the PMOS transistor 41. The differential amplifier start signal 113 is output via these PMOS transistors and the inverter 43. As is apparent from FIGS. 7A, 7C and 7D, the row control signal reset signal 106 is set to "L". In response to the “L” level input and the rise of the word activation start signal 105 to the “H” level, the differential amplifier start signal 113 rises to the “H” level and is output, and the row control signal reset signal 106 outputs the “H” level. At the point of time when the signal rises to the “level”, the signal is transferred to the “L” level and output (see FIG. 7D).

The differential amplifier start signal 113 is input to the differential amplifier activation signal generation circuit 15, and the “H” level active region selection signal 104 is also supplied to the differential amplifier activation signal generation circuit 15. 5 (see FIG. 7B), and as shown in FIG. 5, the differential amplifier start signal 113 and the active area selection signal 104
The logical product is obtained in the circuit 44, and the output signal is inverted in the inverter 45 and output as the "H" level differential amplifier activation signal 114. Then, at the time when the differential amplifier start signal 113 falls to the “L” level, the signal is shifted to the “L” level and output (FIG. 7).
(D) and (e)). The differential amplifier activation signal 114 is input to the restore 1 shot signal generation circuit 16 and the differential amplifier power signal generation circuit 11,
In the restore 1 shot signal generation circuit 16 shown in FIG.
Is delayed by a delay circuit 46, and its delayed output signal is inverted by an inverter 47 and input to one input terminal of a NOR circuit 48 as a "L" level delayed inverted signal 132 (see FIG. 7F). You. Further, the delayed inverted signal 132 is the differential amplifier start signal 1
13 in response to the "L" level transition, the differential amplifier activation signal 114 rises to "H" level in response to the time when it falls to "L" level, and is input to the NOR circuit 48 (FIG. 7 (d) ), (E) and (f)). Therefore, on the other hand, the other input terminal of the NOR circuit 48
The differential amplifier activation signal 114 at the “H” level is directly input, and the logical sum of these two signals is taken and output. During the state of the “H” level, the output level remains at the “L” level, and when the differential amplifier activation signal 114 falls to the “L” level, the output level changes to the “H” level. The signal rises and then falls to the "L" level again in response to the time when the inverted inverted signal 132 rises to the "H" level, and the one-shot pulse signal 11
5 (see FIGS. 7 (d), (e), (f) and (g)).

The one-shot pulse signal 115 is input to the corresponding differential amplifier power supply signal generation circuit 11, and as shown in FIG. And 18, inverters 19 to 21 and 28, and PMOS transistor 2
2, 27 and 29, and NMOS transistors 23-2
6, the “H” level power supply signal generation circuit selection signal 101, the “H” level differential amplifier activation signal 114, and the one-shot pulse signal 1
15, the logical product output signal of the power supply signal generation circuit selection signal 101 and the differential amplifier activation signal 114 by the NAND circuit 17 is output to the PMOS transistor 22.
And NM inverted by the inverter 21
The signal is input to the gate of the OS transistor 26. Also, N
Power supply signal generation circuit selection signal 10 by AND circuit 18
1. Differential amplifier activation signal 114 by inverter 19
And the logical product output signal of the one-shot pulse signal 115 and the one-shot pulse signal 115 are output as an “L” level inverted pulse signal 133 generated by inverting the one-shot pulse signal 115 (FIG. 7E, FIG. g) and (h)), the gate of the PMOS transistor 27, and the PMOS transistor 29 inverted by the inverter 28.
Input to the gate. As a result, the PMOS transistor 27 is turned on while the inverted pulse signal 133 is being input, and the PMOS transistor 29 is turned off while the inverted pulse signal 133 is being input. On the other hand, the power supply signal generation circuit selection signal 101 is directly input to the inverter 20, inverted, and input to the gates of the NMOS transistors 23, 24 and 25.

PMOS transistor 22 and NMOS
Transistor 26 forms a differential amplifier pair. When power supply signal generation circuit selection signal 101 is at "L" level, these PMOS transistor 22 and NMO
The S transistor 26 is in the OFF state, and the N
MOS transistors 23 to 25 are in the ON state,
The floating state is maintained while the potential level of the balanced power supply voltage _Vb is maintained. As described above, when the power supply signal generation circuit selection signal 101 and the differential amplifier activation signal 114 are input at the “H” level,
Both the PMOS transistor 22 and the NMOS transistor 26 are turned on. Therefore, the power signal generation circuit selection signal 101 and the differential amplifier activation signal 114 are set to “H”.
During the level input, the differential amplifier power supply signal 108 is always kept at the ground potential. Meanwhile, PMO
Time period during which the S transistor 29 is turned on, that is, NA
The inversion pulse signal 133 is not output from the ND circuit 18,
While the output is maintained at the “H” level, the PMOS transistor 29 is turned on,
When the potential level of the power supply voltage V _CC is
2, through the PMOS transistor 29 which is in the ON state, is output as it is as the level of the differential amplifier power supply signal 107, and the ground potential level is
The signal is output as a differential amplifier power signal 108 through the NMOS transistor 26. When the inverted pulse signal 133 is output from the NAND circuit 18 in response to the input of the one-shot pulse signal 115, the PMOS transistor 27 is turned on in the time zone of the pulse width, and the power supply voltage V _CC Of the power supply voltage V _H higher than the potential level of the differential amplifier power supply signal 107 via the PMOS transistor 27 as it is, and the ground potential level is NMO.
Through the S transistor 26, the differential amplifier power signal 10
8 is output. These differential amplifier power signals 10
7 and 108 are supplied to a differential amplifier included in the differential amplifier block 4 corresponding to the memory cell 7.

That is, in the present embodiment, the differential amplifier power signal 107 output from the differential amplifier power signal generation circuit 11 is controlled by the one-shot pulse signal 115 output from the restore one-shot signal generation circuit 16. is, the one in the period of the pulse width of the shot pulse signal 115 only, as the potential level of the signal of the voltage V _H on the high potential than the potential level of the power supply voltage V _CC, the differential amplifier block 4 inside the differential The power is supplied to the amplifier, and at other times, the normal power supply voltage V _CC
Is supplied to the differential amplifier in the differential amplifier block 4 as a signal having the potential level of This is a feature of the present invention, whereby the potential level of the differential amplifier power supply signal 107 is set to a normal level for a certain certain period immediately before the end of data writing to the storage node of the memory cell array 7. Can be made higher than the potential level of the power supply voltage, and the writing efficiency for the storage node can be further improved. This is an operation function commonly applied to the differential amplifiers in each bit line pair in the memory cell array 7, and corresponds to the differential amplifier blocks 8 and 9 corresponding to other memory cell arrays. The same is true for the peripheral circuits that perform the operations.

Next, FIG. 8 and FIG.
(A), (b), (c), (d), (e), (f),
(G), (h), (i), (j), (k), (l),
With reference to the operation timing diagrams of (m), (n) and (o), the bit line pair 30-0 shown in FIG.
The operation when writing cell data “H” level to storage node C _S0 inside memory cell 33-0 will be described. When writing cell data to the storage node C _S0 , a pair of NMOS transistors having the gate input of the cutoff signal 126 via the “H” level cutoff signal 126 are in an ON state. The row selection signal 117 output from the word driver circuit 1 (see FIG. 3: the row selection signal 117 includes row selection signals 117-0 to 117-k).
Are included in the row selection signal 117-0.
Is input at the “H” level (see FIG. 8A).
A column selection signal 116-0 included in a column selection signal 116 input from the YSW driver circuit 10 (see FIG. 3: the column selection signal 116 includes the column selection signals 116-0 to 117-n). When the signal goes to the “H” level (see FIG. 8D), the “H” -level data signal 120 and the “L” -level data signal 121 at the read / write input / output terminal are respectively supplied to the differential amplifier contact 130.
And 131 through digit contacts 128 and 12
9 (FIGS. 8 (e), (f), (k), (l),
(See (m) and (n)), "H" level cell data is supplied to the storage node C _S0 via the cell transistor CT ₀ through the digit contact 128 to which the cell transistor CT ₀ is connected. (See FIG. 8 (o)). Then, after a while, the row selection signal 117-
The level of “0” changes to “L” level, but immediately before the row selection signal 117-0 changes to “L” level, the differential amplifier activation signal 114 changes to “L” level,
At the time when the one-shot pulse signal 115 is output as the “H” level, as described above, the differential amplifier power supply signal 107 has a higher potential level than the normal power supply voltage V _CC. As a result, the storage node C _S0
Changes to a higher level than the normal power supply voltage V _CC . Then, after a while, the row selection signal 117-0 goes to the “L” level, but when the row selection signal 117-0 goes to the “L” level,
“H” level value supplied to storage node C _S0 , that is,
The potential level of the normal supply voltage V _CC voltage V _H on the high potential than is retained as stored data signals in the storage node C _S0 (see FIG. 8 (o)), to the storage node C _S0 "H" level The cell data write operation ends. After completion of the data writing, a predetermined standby potential is applied to the digit line pair 30-0 via the balance circuit 32 to which the precharge signal 127 is input, in preparation for the writing or reading operation in the next cycle. Is supplied.

[0026]

As described above, according to the present invention, the voltage level of the differential amplifier power supply voltage signal is changed for a predetermined period within a certain period before and after the end of writing to the storage node of the memory cell array. By setting the potential higher than the normal power supply voltage level, there is an effect that writing efficiency for the storage node can be improved without sacrificing access.

In addition, since the amount of charge held in the storage node of the memory cell array increases due to the above-described effect, charge leakage from the storage node is reduced, and the charge holding characteristic is improved. is there.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a circuit diagram showing a differential amplifier power signal generation circuit in the embodiment.

FIG. 3 is a block diagram showing a differential amplifier block and a memory cell array.

FIG. 4 is a circuit diagram showing a differential amplifier start signal generation circuit.

FIG. 5 is a circuit diagram showing a differential amplifier activation signal generation circuit.

FIG. 6 is a circuit diagram showing a restore one-shot signal generation circuit. But

FIG. 7 is an operation timing chart (1) of the embodiment.

FIG. 8 is an operation timing chart (2) of the embodiment.

FIG. 9 is a block diagram showing a conventional example.

FIG. 10 is a circuit diagram showing a differential amplifier power signal generation circuit in the conventional example.

FIG. 11 is a block diagram showing a differential amplifier block and a memory cell array.

FIG. 12 is a circuit diagram showing a differential amplifier start signal generation circuit in a conventional example.

FIG. 13 is a circuit diagram showing a differential amplifier activation signal generation circuit.

FIG. 14 is an operation timing chart (1) of the conventional example.

FIG. 15 is an operation timing chart (2) of the conventional example.

[Explanation of symbols]

1 to 3 Word driver circuit 4 to 6 Differential amplifier 7 to 9 Memory cell array 10 YSW driver circuit 11 to 13 Differential amplifier power signal generation circuit 14 Differential amplification start signal generation circuit 15 Differential amplifier activation signal generation circuit 16 Restore 1 SHOT signal generation circuit 17, 18 NAND circuit 19 to 21, 28, 34, 36, 45, 47, 50, 5
1, 57, 59, 67, 69 Inverter 22, 27, 29, 53 PMOS transistor 23 to 26, 52, 54 to 56 NMOS transistor 30-1 to 30-n Bit pair 31 Differential amplifier circuit 32 Balance circuit 33-1 ~ 33-k memory cell 35,44,49,58,68 NAND circuit 37-39,46,60-63 delay circuit 48 NOR circuit 101-103 power signal generation circuit selection signal 104 active area selection signal 105 word activation start signal 106 Row control signal reset signal 107 to 112 Differential amplifier power signal 113 Differential amplifier start signal 114 Differential amplifier activation signal 115 1 shot pulse signal 116, 116-0 to 116-n Column selection signal 117 to 119, 117 , 117-0 to 117-k
Row selection signal 120-125 Data signal 126 Cut-off signal 127 Precharge signal 128, 129 Digit contact 130, 131 Differential amplifier contact 132 Delayed inverted signal 133 Inverted pulse signal C _S0 storage node CT ₀ cell transistor

Claims (7)

[Claims] In a semiconductor memory device including a peripheral circuit block for supplying a predetermined differential amplifier power signal to a differential amplifier block associated with an arbitrary number of memory cell arrays, a storage node in the memory cell Within a certain period before and after the end of the data write operation performed for
A differential amplifier power signal correction means for raising the potential level of the differential amplifier power signal supplied to the differential amplifier block to a higher potential level than the potential level of a normal power supply voltage and supplying the same to at least the peripheral device; A semiconductor memory device characterized by being provided in a circuit block. 2. The differential amplifier power supply signal correction means receives a signal for activating the differential amplifier and sets a pulse width to a predetermined period before and after the end of the data write operation.
And a restore 1 for generating and outputting a restore 1 shot pulse signal having a higher potential level than the normal potential level
2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is configured as a shot signal generation circuit. 3. A word activation start signal and a row control signal reset signal are inputted to the differential amplifier block as a peripheral circuit block for supplying a predetermined differential amplifier power signal, and the differential amplifier start signal is supplied to the differential amplifier block. A differential amplifier start signal generating circuit that generates and outputs a differential amplifier start signal and an active area selection signal, and generates and outputs a differential amplifier activation signal; The restore 1 which receives the differential amplifier activation signal, generates and outputs a restore one-shot pulse signal,
A shot signal generation circuit, and the differential amplifier activation signal and the restore one-shot pulse signal are input, and a predetermined differential amplifier power signal is generated for an arbitrary number of corresponding differential amplifier blocks. 3. The semiconductor memory device according to claim 1, further comprising: an arbitrary number of differential amplifier power signal generation circuits that output the signals. 4. A first delay circuit, wherein the restore one-shot signal generation circuit delays and outputs the differential amplifier activation signal by a predetermined time, and a first delay circuit that inverts and outputs a delay output signal of the delay circuit. 4. The inverter according to claim 2, further comprising: an inverter; and a first NOR circuit that outputs a logical sum of an inverted output signal of the inverter and the differential amplifier activation signal and outputs the result. 5.
The semiconductor memory device according to claim 1. 5. A power supply signal generation circuit selection signal for selecting the differential amplifier power supply signal generation circuit, the differential amplifier activation signal, and the restore one-shot pulse. A first NAND circuit that receives a signal input and performs a logical product of the power supply signal generation circuit selection signal and the differential amplifier activation signal and outputs the result; and inverts and outputs the differential amplifier activation signal. A second inverter, a second NAND circuit for performing an AND operation of the power supply signal generation circuit selection signal, the restore one-shot pulse signal, and an inverted output signal of the second inverter, and a normal source. Power supply voltage is supplied to the gate and the second
A first type conductivity type field effect transistor to which an output signal of the NAND circuit is input, a third inverter that inverts and outputs an output signal of the second NAND circuit, and a differential amplifier whose drain is A first second terminal connected to a second output terminal of a power supply signal, an inverted output signal of the third inverter is input to a gate, and a ground potential is supplied to a source;
A fourth field-effect transistor for inverting and outputting the power supply signal generation circuit selection signal;
And a drain connected to the drain of the first type 1 conductivity type field effect transistor, an inverted output signal of the fourth inverter input to the gate, and a source connected to the first type 2 conductivity type field effect transistor. A second second conductivity type field effect transistor connected to the drain of the first field effect transistor; a drain connected to the drain of the first first conductivity type field effect transistor; and a gate connected to the second second conductivity type field effect transistor. A third second-conductivity-type field-effect transistor connected to the gate of the two-conductivity-type field-effect transistor and supplied with balanced power to the source;
A fourth second-conductivity-type field effect transistor connected to the gate of the second-conductivity-type field-effect transistor, and having a source connected to the drain of the first second-conductivity-type field-effect transistor; Is supplied with a power supply voltage higher than a potential level of a normal power supply voltage, an output signal of the first NAND circuit is input to a gate, and a drain is connected to a first output terminal of the differential amplifier power supply signal. A second first-conductivity-type field-effect transistor connected thereto; a fifth inverter for inverting and outputting an output signal of the first NAND circuit; a source having the first first-conductivity-type field-effect transistor A third first-type conductive element connected to a drain of the transistor, an inverted output signal of the fifth inverter input to a gate, and a drain connected to a first output terminal of the differential amplifier power signal; The semiconductor memory device according to claim 3, characterized in that it is configured with a field effect transistor. 6. A sixth inverter which receives the row control signal reset signal, inverts the row control signal reset signal, and outputs the inverted signal, and the word activation start signal and the sixth inverter. Third NAND for taking AND of inverted output signal and outputting
A seventh inverter for inverting and outputting an output signal of the third NAND circuit; a second delay circuit for delaying and outputting an inverted output signal of the seventh inverter; A third and a fourth delay circuit for delaying and outputting an inverted output signal of the seventh inverter; a normal power supply voltage being supplied to a source;
A fourth type 1 conductivity type field effect transistor to which a delay output signal of the delay circuit is input; a source connected to the drain of the fourth type 1 conductivity type field effect transistor; A fifth type 1 conductivity type field effect transistor to which a delay output signal of the delay circuit is input; a source connected to the drain of the fifth type 1 conductivity type field effect transistor; A sixth type 1 conductivity type field effect transistor, to which a delay output signal of the circuit is input and a drain connected to the ground potential; an input terminal having a drain of the fourth type 1 conductivity type field effect transistor; An eighth inverter connected to a connection point of a fifth type-one field effect transistor of the first type and outputting the differential amplifier start signal from an output terminal. The semiconductor memory device according to claim 3. 7. The differential amplifier activation signal generating circuit according to claim 1,
A fourth NAND circuit that outputs a logical product of the differential amplifier start signal and the differential amplifier activation signal, and a ninth inverter that inverts and outputs an output signal of the fourth NAND circuit; 4. The semiconductor memory device according to claim 3, comprising: