KR970011024B1 - Semiconductor memory device - Google Patents

Abstract

None.

Description

Semiconductor memory

1 is a block diagram showing an embodiment of the present invention.

2 and 2 are circuit diagrams showing one specific embodiment thereof.

3 is a timing diagram showing an example of the operation thereof.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having an insulated gate field effect transistor (hereinafter referred to as MOSFET) as a main circuit component.

There are two types of semiconductor memory devices, such as RAM (Random Access Memory). In the dynamic RAM, the number of elements constituting the memory cell for storing information is smaller than that of the static type, so it is easier to increase the capacity than the static RAM.

However, the main amplifier conventionally used in a dynamic semiconductor memory device is not suitable for high speed and low power consumption because an active load circuit or the like is not used and a CMOS latch configuration is used. Moreover, since the number of elements becomes large, it is not suitable for high integration.

Thus, the present inventors considered a main amplifier having a low number of elements as a high speed and low power consumption.

It is an object of the present invention to provide a semiconductor memory device having a main amplifier with high speed and low power consumption. The dynamic semiconductor memory device of the present invention has a main latch for amplifying the voltage difference between common complementary data line pairs and a CMOS latch structure, and has a precharge MOSFET for shorting the common complementary data line pairs to delay an intermediate voltage.

According to the present invention, the voltage of the common complementary data line can be amplified at high speed to the power supply voltages Vcc and 0V, and can be precharged at a medium voltage Vcc / 2 at high speed.

It will be described below in detail with examples of the present invention.

1 shows a block diagram of one embodiment of the present invention.

In the same drawing, each circuit block surrounded by a dotted line is formed on one semiconductor substrate by a manufacturing technology of a known Complementary Metal Oxide Semiconductor (CMOS) integrated circuit, and the terminal , And Vcc and Vss are external terminals thereof. Between the terminals Vcc and Vss, a power supply voltage is supplied from a suitable external power supply not shown.

Indicated by the circuit symbol M-ARY is a memory array, which is composed of known 1MOS memory cells arranged in a matrix. Each memory cell consists of one MOSFET and one capacitor. Although not particularly limited in this embodiment, the memory array is in a folded bit line construction. In a memory array of a flooded bit line system, each memory cell is a pair of complementary data lines D extending in parallel to each other on a semiconductor substrate so as to be clearly shown in FIGS. 2A and 2B, Each input and output node is combined on either side of the.

The circuit symbol PC1 denotes a data line precharge circuit, which receives the precharge pulse Φ _pa1 and complements the data line D, It is constituted by a MOSFET that shorts the gap.

Marked with the circuit symbol SA is a sense amplifier. As shown in FIG. 2A, a sense amplifier SA is used for power switches provided on a plurality of unit circuits each consisting of a CMOS latch circuit, respectively, on the power supply voltage Vcc side and the ground potential Vcc side of the circuit. It is composed of MOSFETs. A pair of input / output nodes of the sense amplifiers have corresponding complementary data lines D, Is coupled to The power switch MOSFETs provided on the power supply voltage Vcc side and the ground potential Vss side of the circuit are timing signals. The ON and OFF are controlled by

Designated by the circuit symbol C-SW is a column switch, which combines only a pair of complementary data lines to be selected in accordance with a column select signal supplied from a column address decoder C-DCR described below to a common complementary data line.

The circuit symbol A-ADB is an X address buffer, which receives an external address signal via terminals A _{0 to} A ₁ and receives an internal complementary address signal. To form.

Designated by the circuit symbol Y-ADB is a Y address buffer, which receives an external address signal from terminals A _{1 + 1 to} A _j and receives an internal complementary address signal. Form,

The circuit symbol R-DCR denotes a row address decoder, which is a complementary address signal. To form the word line selection signal of M-ARY. This word line selection signal is transmitted to M-ARY in synchronization with timing pulse .phi.x.

The circuit symbol C-DCR denotes a column address decoder, which is the complementary address signal. To form a data line selection signal to be supplied to M-ARY.

This data line selection signal is transmitted to the column switch C-SW in synchronization with the timing pulse wave.

The circuit symbol PC2 is a precharge circuit for precharging the common data line, and is composed of a MOSFET which receives the precharge pulse phi _pc2 and shorts the common complementary data line.

This is the main amplifier indicated by circuit symbol MA. The main amplifier MA has the same circuit configuration as the sense amplifier SA. That is, the main amplifier MA is composed of a CMOS latch circuit, a power switch MOSFET provided on each of the power supply voltage Vcc side and the ground potential side of the circuit. The pair of input / output nodes of the CMOS latch circuit are respectively coupled to the pair of common complementary data lines. Each power switch MOSFET has a timing signal The ON / OFF is controlled by

The circuit symbol DOB denotes a data output buffer circuit for timing signals. In response, the read data and the corresponding data supplied to the main amplifier MA are sent to the external terminal I / O. In addition, the timing signal at the time of writing This causes the data output buffer DOB to be inoperative. In addition, the timing signal Φ _HZ causes the output of the DOB to become high impedance at the time of reading. The timing signal Φ _HZ is mainly used for performing the regeneration operation. The memory shown in Fig. 1 is configured to execute a regeneration operation in response to a change in the address signal in the read operation state. When the output signal of the data output buffer DOB is made high impedance by the timing signal 硏 π, several semiconductors The wired OR logic can be easily formed between the outputs of the storage device.

The circuit, which is indicated by the symbol DIB passes light data, which is supplied as a data input buffer, in response to a timing signal Φ _RW to the terminal I / O to the common data line. At the time of read, the timing signal Φ _RW causes the DIB to become inoperative.

In this embodiment, the various timing signals are formed by the following circuit blocks.

Although the circuit symbol EGTx is not particularly limited, it is an internal address signal. Is an edge trigger circuit that detects the rising or falling edge of the address signal.

The circuit symbol EGT _Y is not particularly limited, but may be internal address signal. Is an edge trigger circuit that detects the rising or falling edge of the address signal.

These edge trigger circuits EGTx and EGT _Y are not particularly limited, but an exclusive-OR circuit that receives the internal address signals a _{0 to a 1} and a _{1 + 1 to a j} and their delay signals, as described below, and their outputs And an edge detection pulse Φ _EX , Φ _EY synchronized with the timing of the change when at least one level of the internal address signals a _{0 to a 1} and a _{1 + 1 to a j} changes. Form each.

By clearly distinguishing the edge detection pulse Φ _EX representing the transient of the row address signal and the edge detection pulse Φ _EY representing the transient of the column address signal, generation of a timing signal to be corresponded to the transient of the row address signal and It is easy to generate a timing signal that should correspond to the transient of the column address signal.

Shown by the circuit symbol TG is a timing generating circuit, which forms various timing signals and the like as described above. The timing generation circuit TG has a write enable signal from an external terminal in addition to the edge detection pulses Φ _EX and Φ _EY. And chip select signal Is received to form the series of timing pulses.

2 and 2, a circuit diagram of one specific embodiment of the main circuit in FIG. 1 is shown. In FIGS. 2A and 2B, each of the P-channel MOSFETs and each of the N-channel MOSFETs is shown as different symbols. The symbol for a P-channel MOSFET such as MOSFET Q ₇ is distinguished from an N-channel MOSFET such as MOSFET Q ₆ by the addition of a straight line between the drain source:. The illustrated P-channel MOSFET and N-channel MOSFET are in enhancement mode.

The memory array M-ARY consists of several memory rows and several word lines W _{1 to} W ₅ . Each memory row has the same configuration. Accordingly, only one memory row is representatively shown in detail in FIG. One memory row includes a pair of complementary data lines D arranged in parallel with each other, as shown in FIG. Are arranged with each predetermined regularity and each input / output node is a complementary data line D of rice. It consists of memory cells coupled to either side. The memory cells have the same configuration. One memory line consists of, for example, a switch MOSFET Q ₁₆ and a MOS capacitor C coupled thereto. The gate of the switch MOSFET in one memory cell becomes the selection terminal of the memory cell. The selection terminal of each memory cell is coupled to the corresponding word line.

The precharge circuit PC1 is, as representatively shown with the MOSFET Q _14, the complementary data line D, The source drain passage is constituted by a switch MOSFET coupled therebetween.

The unit circuit constituting the sense amplifier SA is composed of a CMOS (complementary MOS) latch circuit composed of P-channel MOSFETs Q ₇ and Q ₉ and N-channel MOSFETs Q ₆ and Q ₈ , as one representative of which is shown. It is. The pair of input / output nodes of the CMOS latch circuit includes the complementary data line D, Is coupled to Although not particularly limited to the latch circuit shown in FIG. 2A, the power supply voltage Vcc is supplied through the P-type MOSFETs Q ₁₂ and Q ₁₃ in parallel, and the N-channel MOSFETs Q ₁₀ and Q ₁₁ in parallel. The ground voltage Vss of the circuit is supplied. These power switch MOSFETs Q ₁₀ , Q ₁₁ and Q ₁₂ , Q ₁₃ are also commonly used for a latch circuit not shown provided in the same memory row as the other.

Timing signals for activating a sense amplifier SA at the gates of the MOSFETs Q ₁₀ and Q ₁₂ Is applied, and the timing signal is applied to the gates of MOSFETs Q ₁₁ and Q ₁₃ . Delayed Timing Signals (Scan) , Is applied. The timing signal Are complementary to each other to turn on and off the power switch MOSFETs Q ₁₀ and Q ₁₂ simultaneously. Similarly, the timing signal The power switches MOSFETs Q ₁₁ and Q ₁₃ are complementary to each other to simultaneously turn ON or OFF. That is, for example, the timing signal Is a timing signal inverted in phase with respect to the timing signal _{.phi pa1} .

Each of the wave switch MOSFETs Q ₁₀ and Q ₁₂ will have a relatively small conductance. In contrast, each of the MOSFETs Q ₁₁ and Q ₁₃ has a relatively large conductance.

Therefore, each unit circuit (latch circuit) constituting the sense amplifier SA includes the timing signals? _Pa1 and Are relatively weakly activated by the timing signals Φ _pa2 and Strongly activated by In this way, by activating the sense amplifier SA in two stages, a large resistance (dropping) of the high level potential of the complementary data line generated by the start of the operation of the sense amplifier SA can be prevented and the data can be prevented. Fast reads can be performed.

That is, when amplifying the small read voltage from the memory cell with the sense amplifier SA, first, the MOSFETs Q ₁₀ and Q ₁₂ having relatively small conductance are the timing signals. It turns ON by Accordingly, the sense amplifier SA starts to amplify the potential difference between the complementary data lines. Since the potential difference between the complementary data lines is small at the start of this amplification operation, the MOSFETs Q ₆ and Q ₈ constituting the sense amplifier SA are still in a conductive state. For this reason, the charge previously held in the data line on the high level side is excessively discharged through one of the MOSFETs constituting the sense amplifier SA and the power switch MOSFETs. For this reason, the potential on the high level side drops. However, the timing signal By setting the conductance of the power switch MOSFETs Q ₁₀ and Q ₁₂ to be turned on for the first time to a relatively small value, the amount of discharge charge in the data line on the high level side which flows undesirably at this time is limited to a small value. This can prevent a large drop in the potential on the high level side. When the potential difference between the complementary data lines is increased to some extent, a timing signal is used for switching MOSFETs Q ₁₁ and Q ₁₃ with relatively large conductance. By the ON state, the amplification operation of the sense amplifier SA becomes high. Therefore, by performing the amplification operation of the sense amplifier SA in two steps as described above, it is possible to execute the high speed read while preventing the drop of the high level side of the complementary data line.

The row decoder R-DCR is composed of several unit circuits. 2, a unit circuit (for four word lines) constituting the row decoder R-DCR is representatively shown. The decoder R-DCR includes a NAND circuit ND having a CMOS circuit configuration consisting of N-channel MOSFETs Q _{32 to} Q ₃₆ and P-channel MOSFETs Q _{37 to} Q ₄₁ which receive internal address signals a ₂ to a ₆ . . Therefore, a word line selection signal for selecting four word lines W _{1 to} W ₄ is formed by the NAND circuit ND.

The output of the NAND circuit ND is inverted in the CMOS inverter IV1 and is transferred to the gates of the MOSFETs QW _{24 to} Q ₂₇ constituting the transfer gate circuit TRF through the cut MOSFETs Q _{28 to} Q ₃₁ .

The word line selection timing signals? _{X00 to} ? _X11 are supplied to the respective sources of the MOSFETs Q _{24 to} Q ₂₇ . The word line selection timing signals? _{X00 to} ? _X11 are formed by circuits not shown, which form part of the row decoder R-DCR. Each level of the word line selection timing signals Φ _{X00 to} Φ _X11 is determined by a combination of a decode signal and timing pulse Φ _X formed by decoding the two-bit address signals a ₀ , a ₁ .

Although not particularly limited, when the word line selection timing signal Φ _X00 is at the low level (logical "0") when the address signals a ₀ and a ₁ are both low level, the timing pulse Φ _X becomes a high level (logical "1"), Correspondingly, high level is reached. The signal phi _X01 goes high in synchronization with the timing pulse phi _X when the address signal a ₀ goes high and the address signal a ₁ goes low. Similarly, the signals Φ _{X10 to} Φ _X11 become high level in accordance with the address signals a ₀ and a ₁ and the timing pulse Φ _X.

Therefore, in the unit circuit shown in the row decoder R-DCR, when the output of the NAND circuit ND becomes low in accordance with the address signals a ₂ and a ₆ , one of the word lines W _{1 to} W ₄ is set to the timing pulse Φ _X. In synchronism with the high level.

The word line selection timing signals Φ _X00 and Φ _X11 are also supplied to a unit circuit (not shown) constituting the row decoder R-DCR.

In addition, between the word lines and the ground potential, MOSFETs Q ₂₀ to Q ₂₃ to which the output of the NAND circuit is supplied to respective gates are provided. MOSFET Q _{20 to} Q ₂₃ are turned on when the combination of address signals a _{2 to a 6} does not represent a set of word line groups W _{1 to} W ₄ , that is, when the output of the NAND circuit ND is at a high level. It is in a state. As a result, the word lines W _{1 to} W ₄ are fixed to the ground potential by the MOSFETs Q ₂₀ to Q ₂₃ when they are not selected, that is, one word line in the desired set of word line groups should be at the selection level. In order to prevent the remaining undesired word line group from being selected at the time of selection, a MOSFET controlled by the output of the NAND circuit is provided between the word line and the ground potential point of the circuit.

Between the word lines and the ground point of the circuit, the reset MOSFETs Q _{1 to} Q ₅ are provided with reset pulses Φ _PW supplied to the respective gates. The word line selected in the previous operation cycle, for example the read cycle, is reset to the ground level for the next operation cycle by receiving the reset pulse? _PW and turning on their MOSFETs Q _{1 to} Q ₅ .

The column switch C-SW is a complementary data line such as MOSFETs Q ₄₂ and Q ₄₃ , which is typically shown in FIG. And common complementary data lines It consists of MOSFET provided in between.

The gates of the MOSFETs Q ₄₂ and Q ₄₃ are supplied with a selection signal from the column decoder C-DCR.

With common complementary data line CD Between it is provided with a precharge MOSFET Q ₄₄ configuring the precharge circuit PC2.

This common complementary data line CD, A pair of input / output nodes of the main amplifier MA having the same circuit configuration as that of the sense amplifier SA are coupled to each other.

Further, the common complementary data line CD, Is coupled to the complementary output node of the data input buffer DIB.

EGTx (EGT _Y) is a second as shown in Figure b, the internal address signal _{a 0 ~a 1 (a 1 +} 1 ~a j) and delay of the internal address signals formed by the delay circuit D ₀ ~D ₁ exclusive-OR circuit receiving the signal E ~E _X0 is composed of the _X1 and the OR circuit receives the output signals of these E ~E _{X0 X1.}

Next, the operation of this embodiment circuit will be described according to the timing diagram of FIG.

In addition, the timing signals Φ _pa1 and Φ _pa2 are the timing signals as described above. And Is reversed with respect to. In FIG. 3, a timing signal is used to prevent the drawing from becoming complicated. Is omitted.

If any one of the address signals a _n falls from the high level to the low level as shown in Fig. 3A, for example, the delay signal a _n is delayed and dropped. Accordingly, the edge detection circuit Φ _EX (Φ _EY ), which becomes a high level (“1”) only from the start of the change of the address signal a _n until the delay signal a _n is generated, is the edge trigger circuit EGT _X (EGT). _Y ) is output.

The timing generating circuit TG receives this pulse Φ _EX (Φ _EY ), thereby forming a reset pulse Φ _RS as shown in FIG. 3 d. This reset pulse is the operating state of each circuit reset as determined in the previous operation cycle, for example of the read operation cycle by Φ _RS.

For example, the word line is reset by the word line reset pulse Φ _PW (not shown in FIG. 3) formed in accordance with the reset pulse Φ _RS .

Similarly, the word line selection timing signal Φ _X , the timing signals Φ _pa1 , Φ _pa2 , and the data line selection timing of the sense amplifier SA as shown in _FIGS . _3E , _3H , _3I and _3J . The timing signals Φ _ma1 and Φ _ma2 of the signals Φ _Y and the main amplifier MA are reset (reset level) by the reset pulse Φ _RS . For example, the timing signals Φ _X , Φ _pa1 , Φ _pa2 , Φ _Y , Φ _ma1, and Φ _{ma2 go} low.

The timing signals Φ _pa1 , Φ _pa2 , Φ _Y , Φ _ma1, and Φ _ma2 become low level and are in a complementary relationship with these signals. Are each at a high level. For this reason, the sense amplifier SA and the main amplifier MA become inactive, respectively, and the complementary data lines D, And common complementary data line CD, Becomes a floating state.

Complementary data line D, And common complementary data line CD, Each of the parasitic doses not shown is combined. Each parasitic capacitance is charged with a charge corresponding to the potential of the corresponding data line in a previous previous operation cycle. For example, parasitic capacitance and complementary data lines not shown coupled to the complementary data lines D Look at the parasitic capacity, not shown, coupled to. In the previous operation cycle, the complementary data line D is, for example, high level (Vcc), and the complementary data line Is at the low level (0V), the charge corresponding to the high level Vcc is accumulated in the parasitic capacitance of the data line D, and the data line In the parasitic capacitance of the electric charge due to the low level (0V) is accumulated. Common complementary data line CD, Each of the parasitic capacitances is also at the high level or the low level.

Complementary data line D having a parasitic capacitance in which charge determined in such a previous operation cycle has accumulated, And common complementary data line CD, Is in the floating state as described above, whereby the complementary data line D, And common complementary data line CD, Each parasitic capacitance coupled to maintains the charge determined for each previous operating cycle. Thus, the complementary data line D, And common complementary data line CD, Each potential of is also retained at each potential in the previous operating cycle. For example, in the previous operation cycle as in the above example, the parasitic capacitance and the complementary data line of the complementary data line D When predetermined charges are respectively stored in the parasitic capacitance of the parasitic capacitance of the complementary data line D in the floating state as described above, the parasitic capacitance in the floating state maintains the charge according to the high level (Vcc), and similarly the complementary state in the floating state. Data line The parasitic capacitance in E retains the charge according to the low level (0 V). For this reason, the potential of the complementary data line D in the floating state is maintained at the high level (Vcc), and the complementary data line The potential of keeps the low level (0V). This is a common complementary data line CD, The same is true for.

That is, the complementary data line D, And common complementary data line CD, Maintains a high level (Vcc) and a low level (0V) in the floating state.

The precharge pulses phi _pc1 and phi _pc2 are generated in accordance with the timing at which the reset of the word line ends.

Since the precharge MOSFETs Q ₁₄ and Q ₄₄ are turned on by the precharge pulses Φ _pc1 and Φ _pc2 , the complementary data lines D and Mutual and common complementary data lines of CD and The mutual is shorted. As a result, the complementary data line D, Mutual and common complementary data lines of CD, Is precharged to an intermediate level of about Vcc / 2.

When the next reset pulse Φ _RS falls to the low level, the reset state is released. The precharge operation ends by releasing the reset state.

Complementary data line D _according to the precharge signal Φ _pa1 , After the end of precharging of the furnace, the word line selection timing signal? _X rises to a high level as shown in FIG. As a result, the high level signal output from the row decoder R-DCR is applied to one word line determined by the address signals A _{0 to} A _i . That is, one word line determined by the address signals A _{0 to} A _i is selected to be the selection level of the memory cell. The switch MOSFET constituting the memory cell is turned ON by the high level potential of the selected word line.

One data line, for example a data line, to which the selected memory cell is coupled Charge distribution is performed between the parasitic capacitance of and the storage capacity of the memory cell. Data line The level of is changed to the level accumulated in the memory capacity of the memory cell, that is, the level corresponding to the data stored in the memory cell. In this case, since the memory cell coupled to the other data line D is not selected, this data line D maintains the precharge level Vcc / 2. As a result, the data line D and In between, a small potential difference corresponding to the sustain data in the selected memory cell is generated.

With data line D The micropotential difference applied in between is specifically as follows. That is, the data line For example, when the charge corresponding to vcc is accumulated in the storage capacity of the memory cell coupled to the data line, the data line The potential is higher than the potential Vcc / 2 of the data line D. On the other hand, when the charge corresponding to 0 V is stored in the memory capacity of the memory cell, in other words, when the charge is not stored in the memory capacity, the data line The potential of is lower than the potential (Vcc / 2) of the data line D.

With this data line D The small voltage difference between the two is amplified by the sense amplifier when the sense amplifier is activated. That is, next, the timing signal Φ _pa1 is at a high level (timing signal). Is a low level), so that the sense amplifier SA is activated, and the sense amplifier SA An amplification operation for increasing the potential difference between them is disclosed. _Next , the timing signal Φ _pa2 is at a high level (timing signal). Low level). As a result, the amplification degree of the sense amplifier SA increases, and the complementary data line D The potential difference between them becomes larger.

Next, the data line select timing signal Φ _Y is as soon as the high level at the same time, the precharging signal Φ _pa2 the low level.

The MOSFET Q ₄₄ is turned off by the precharge signal _.phi.pa2 being at a low level. As a result, the common complementary data line CD, Precharge ends.

Further, when the data line selection timing signal Φ _Y becomes high level, a pair of complementary data lines D to be determined by the address signals A _{i + 1 to} A _j , Common complementary data line CD, The column select signal for coupling to the signal is supplied from the column decoder C-DCR to the column switch C-SW. For this reason, the pair of complementary data lines D to be selected by the column select signal, Common complementary data line CD, via the column switch C-SW Is coupled to.

Complementary data line D, Common complementary data line CD, When coupled to the common complementary data line CD by the precharge signal Φ _pa2 , When the precharge of the circuit is terminated, the common complementary data line CD, even if the common data line is applied to the common complementary data line such as noise, before the common data line and the data line are combined, The potentials of can be equally added to each other. For this reason, the selected data line D, The potential difference between the common data line CD, This semiconductor memory device can be made to be resistant to noise since it is transmitted to the semiconductor memory device.

Common complementary data line CD, The precharge by the precharge MOSFET Q ₄₄ as described above is also precharged to Vcc / 2. For this reason, the common data line The potential of is this common data line The charge accumulated in the parasitic capacitance of the charge (charge corresponding to Vcc / 2) and the common data line Data lines bound to It is determined by the charge dispersion with the charge accumulated in the parasitic capacitance of. Similarly, the potential of the common data line CD is selected from the charge stored in the parasitic capacitance of the common data line CD (the charge corresponding to Vcc / 2) and accumulated in the parasitic capacitance of the data line D coupled to the common data line CD. It is determined by the charge dispersion with the charge.

That is, the complementary data line D, Common complementary data line CD, When coupled to, the potential of the common data line CD determined by the charge distribution between the parasitic charge of the data line D and the charge of the parasitic capacitance of the common data line CD is the data line. Parasitic charge and common data line Common data line determined by charge dispersion with charge of parasitic capacitance of It is higher (lower) than the potential of.

In Fig. 3G, a memory cell coupled to the data line D is selected, and a charge corresponding to Vcc is accumulated in the storage capacity of the selected memory cell (or a memory cell coupled to the data line D is selected). The data line D when the charge corresponding to 0 V is accumulated in the memory capacity of the memory cell; And common data line CD, Each potential change of is shown by the solid line.

With this common data line CD The potential difference between and is amplified by the main amplifier MA. That is, Φ _ma2 , which is the timing signal Φ _ma1 , _goes to a high level next, and the timing signal Becomes low level, the main amplifier MA is operated accordingly accordingly. The potential difference between them is amplified.

In the read operation, the potential difference amplified by the main amplifier MA is supplied to the data output buffer DOB. The data output buffer DOB sends an output signal corresponding to the input signal to the terminal I / O.

In the write operation, the common data line CD, The write data is passed through the data input buffer DIB. Common data line CD, Data line D, depending on the write data supplied to The level of is determined. As a result, the write data is transferred to the selected memory cell.

In addition, although not particularly limited, in order to apply a voltage above the power supply voltage Vcc + Vth (where Vth is the threshold voltage of the switch MOSFET) to the gate of the switch MOSFET of the memory cell when data is written to the memory cell, The line selection timing signal Φ _X is at a high level of the power supply voltage Vcc + Vth or more by a bootstrap circuit (not shown). By doing this, the high level Vcc of the data line can be transferred to the MOS capacitor of the memory cell without losing the level, and the charge accumulated in the MOS capacitor can be increased.

Also in the rewriting (reproducing) to the memory cell, the word line selection timing signal Φ _X is at a high level of the power supply voltage Vcc + Vth or more by a bootstrap circuit (not shown). As a result, the high level Vcc of the data line is rewritten without loss of level to the MOS capacitor of the memory cell held at the high level.

In the read operation, the potential of the selected complementary data line is amplified to the high level (Vcc) and the low level (0V) by the sense amplifier SA, and the potential of the common complementary data line is similarly the high level (Vcc) and low by the main amplifier MA. Amplified to level (0V). The potential of the unselected complementary data line is also amplified to the high level (Vcc) and the low level (0V) by the sense amplifier SA of the row.

For example, as shown by solid lines in FIG. 3G, the selected data line D and the common data line CD are amplified to a high level (Vcc) by the sense amplifier SA and the main amplifier MA, respectively, and the selected data line is selected. And common data lines The sense amplifier and the main amplifier are amplified to low level (0V), respectively. As shown by the dotted lines in Fig. 3G, one of the complementary data lines that were not selected is amplified by the sense amplifiers to the high level (Vcc) and the other complementary data lines to the low level (0V), respectively.

In addition, the potential of the high or low data line is transferred to the MOS capacitor of the memory cell during the rewrite described above.

Also in the write operation, the data input buffer DIB and the sense amplifier SA, depending on the data to be written, cause the potential of the pain data line and the data line to be at the high level (Vcc) or the low level (0V), respectively. For example, depending on the data to be written, the potentials of the common data line CD and the data line D become high level (Vcc), and the common data line , Data line The potential of becomes low level (0V).

In this manner, also in all operations, the data lines D, The potentials of become high level (Vcc) or low level (0V), respectively, and the common data line CD, The potential of is also at the high level (Vcc) or the low level (0V), respectively. For this reason, data line D, In each of the capacitors, charges corresponding to a high level and charges corresponding to a low level are accumulated. Similarly, common data line CD, The charges corresponding to the high level and the charges corresponding to the low level are also accumulated in each of the capacitors. That is, when charges corresponding to a high level (Vcc level) are accumulated in the capacity of one data line (common data line), charges corresponding to a low level (0V) are stored in the capacitance of the other data line (common data line). Will accumulate.

In this way, the data line D, And common data line CD, Charges accumulated in the respective capacities of the data lines D, as described above, Precharge and common data line of CD, Used for precharging.

In addition, although not particularly limited, in this embodiment, when a logic " 1 " is written to a memory cell coupled to one data line D of the complementary data line, the memory capacity of the memory cell depends on, for example, the power supply voltage Vcc. Charges accumulate. On the other hand, the other data line When the logic " 1 " is written in the memory cell coupled to the memory cell as described above, charges are stored in the memory cell according to the ground potential (0V) of the circuit. When a logic "0" is written to a memory cell coupled to one data line D, charges according to the ground potential (0V) are stored in the memory capacity of that memory cell, and the logic "0" is stored in the other data. line When writing to a memory cell coupled to the memory cell, charges corresponding to the power supply voltage Vcc are accumulated in the storage capacity of the memory cell. Specifically, as shown in the same figure, when the potential of the I / O terminal is high level (logical "1"), for example, the common data line CD is set to high level (Vcc). Common data line Is set to the low level (0V). On the contrary, when the potential of the I / O terminal is at the low level (logical "0"), the common data line CD is set at the low level (0V), and the common data line Is set to the high level (Vcc). The main amplifier MA is not particularly limited, but amplifies the level of one common data line CD and transfers it to the node CDI of the data output buffer DIB and the other common data line. The other node of the data output buffer DOB To be delivered to The data output buffer DOB is not particularly limited, but the level of node CDI is When the level is higher than, the output signal of the high level (logical "1") is supplied to the terminal I / O. When it is lower, the output signal of the low level (logical "0") is supplied to the terminal I / O.

According to this configuration, the complementary signal output from the main amplifier MA is supplied to the data output buffer DOB. However, instead of the configuration shown in Fig. 2B, for example, only one of the complementary signals output from the main amplifier MA may be supplied to the data output buffer DOB. In this case, for example, the data output buffer D0B compares the level of the signal from a certain reference voltage (e.g., the logic threshold voltage of the DOB) and the main amplifier MA, and outputs the output signal according to the comparison result. The structure which supplies to a terminal can be taken.

The timing generation circuit TG is not only the detection signal Φ _EX output from the edge trigger circuit EGT _X but also the precharge signal Φ _pc2 and the timing signal Φ _Y according to the detection signal Φ _EY output from the edge trigger circuit EGT _Y according to the column address signal. It is configured to output the main amplifier control signals Φ _ma1 , Φ _ma2 , and the like. This makes it possible to sequentially read the data amplified by the sense amplifier in advance. That is, after one set of row address signals A _{0 to} A _i are supplied to the memory, the column address signals A _{i + 1 to} A _j are sequentially changed, whereby data can be read at the address corresponding thereto.

The detection signals Φ _EX and Φ _EY may correspond to a row address strobe signal and a column address stove signal supplied to a memory of a known address multiplex method. Therefore, the logic configuration of the timing generation circuit for forming various timing signals as described above may be similar to the logic configuration of timing generation of a known memory.

Although not particularly limited in this embodiment, the substrate bias voltage generation circuit V _BB -G is provided to lead the high speed operation of the memory.

Although not particularly limited, in order to achieve low power consumption, the main amplifier MA is not operated during the write operation in this embodiment.

In the semiconductor memory device of this embodiment, precharging is performed by using the edge of the address signal, so that the timing signal to be externally supplied to the memory is unnecessary, except that a regeneration operation is required. You can treat it like a par. Therefore, it is possible to simplify the timing control of the external loader.

As the memory cell, a memory cell of a type used in a dynamic RAM, for example, a memory cell having a relatively small occupied area composed of one switch MOSFET and one storage capacity as described above can be used. Therefore, the operation control can be performed similarly to the static RAM, and at the same time, the capacity can be increased.

In addition, the precharge operation is to make the intermediate level (about Vcc / 2) below the Vcc level by simply shorting a pair of the complementary data lines and the common complementary data line. Compared with charging up from 0V to the Vcc level, the amount of change in the level can be reduced, so that it can be executed at high speed. Since the precharge level is at the intermediate level equal to or less than the Vcc level as described above, the precharge MOSFET is sufficiently turned on even if its gate voltage is at the normal logic level Vcc. As a result, a sufficient precharge level can be formed. On the other hand, in the case of precharging up to the Vcc level as in the related art, it is necessary to apply a high bootstrap voltage higher than the Vcc level to the gate of the precharge MOSFET in order to sufficiently raise the precharge level. As a result, the circuit becomes complicated and the circuit operation is delayed by the complicated circuit. According to the embodiment, since the precharge level is formed by charge dispersion such as complementary data lines, there is no current consumption during precharge. Therefore, the power consumption can be reduced.

In addition, since the precharge level is set to an intermediate level of about Vcc / 2, the switch MOSFET in the memory cell at the time of reading data from the memory cell has its gate voltage (word line potential) at a normal logic high level ( Vcc) is also preferably turned ON. In other words, when the gate voltage of the switch MOSFET in the memory cell is 1 / 2Vcc + Vth or more, the switch MOSFET is turned on in the saturation region. As a result, it is possible to read the entire charge of the MOS capacitor without using the bootstrap voltage as in the conventional dynamic RAM wave. Therefore, high speed lead and high reliability can be realized.

In addition, since a dummy memory cell such as a vertical dynamic RAM is not provided, the chip size can be made smaller by that amount and by the word line selection circuit. Further, the read reference voltage to be referred to by the sense amplifier SA is the complementary data line D just before the read; Since it is composed of the same precharge level, it follows the fluctuation of the power supply voltage Vcc. Also, the read reference suppression is substantially unaffected by the change of the elements of the memory cell and the dummy memory cell. As a result, the operating margin of the circuit can be significantly improved.

In addition, when the peripheral circuit is composed of a CMOS circuit including the sense amplifier SA, the power consumption can be reduced.

In particular, the sense amplifier SA and the main amplifier MA are preferably constituted by a CMOS circuit. That is, when the sense amplifier SA and the main amplifier MA are composed of CMOS circuits composed of P-channel MOSFETs and N-channel MOSFETs, respectively, the complementary data lines D, The potential of can be amplified to the power supply voltage (Vcc) and the ground potential (0V) of the circuit, respectively, and the common complementary data line CD, The potential of can also be amplified to the power supply voltage Vcc and the ground potential of the circuit (0V), respectively. For this reason, the data lines D during the read operation, the write operation or the reproduction operation can be performed by a simple circuit. Potential difference between and common data line CD, Since the potential difference between them can be increased, malfunction can be reduced. Further, by providing such a sense amplifier, the data lines D, before the precharge operation starts, Since the charge according to the power supply voltage (Vcc) and the charge according to the ground potential (0V) can be accumulated in each parasitic capacitance of the data line, the data line D, The precharge level can be set to about Vcc / 2. This is a common complementary data line CD, The same is true for.

In addition, the address buffers X-ADB, Y-ADB, edge trigger circuits EGT _X , EGT _Y, and timing generation circuit TG, etc. are preferably constituted by a static circuit so that an output signal is formed at any time when each input signal changes. Do.

The present invention is not limited to the above embodiment.

One data line in M-ARY may be configured as a dummy data line.

In addition, each complementary data line D, The dummy cells may be coupled to each other. In that case, when the memory cell coupled to one complementary data line is selected, the dummy cell coupled to the other complementary data line is selected. In this way, the potential change of the word line is transmitted to one data line via an undesirable capacitance (overlap capacitance between the gate electrode and one data line) of the switch MOSFET of the selected memory cell, and at the same time, The potential change of the word line for the dummy cell is transferred through the undesirable capacitance of the switch MOSFET of the selected dummy shell. The potential change applied to the data line in accordance with the potential change of the word line is regarded as noise. However, the potential change applied to a pair of data lines at the same time is considered to be in phase. Sense amplifiers do not actually detect frostbite noise. Therefore, the malfunction of the circuit can be further reduced despite the undesirable potential change applied to the pair of complementary data lines.

The edge trigger circuit uses the complementary address signal a ₀ , May be used, and a logical sum or logical gate which biases the logic threshold voltage to the high level or low level side may be used.

In addition, a plurality of bit informations may be read / written in parallel.

In addition, the peripheral circuit can take various embodiments.

In addition, the redundant memory array and its switching circuit may be internalized for defect bit relief.

In addition, the automatic playback function may be incorporated.

Claims (1)

Multiple data line pairs (D, ), The first word line (W ₁₎ and the second word of the multiple word lines, including lines _{(W 3) (W 1,} W 2, W 3, W 4, W 5), each data line pair (D, A first 1 MOS type dynamic memory cell having an input / output terminal coupled to only one data line and a selection terminal coupled to the first word line, and an input / output terminal coupled only to the other data line of each pair of data lines. A second 1-MOS dynamic memory cell having a selection terminal coupled to the second word line, coupled to each data line pair, the data line pair being at an intermediate level between a high level potential (Vcc) and a low level potential (Vss); Each of the CMOS latch circuits including a data line precharge circuit PC ₁ set to a potential, a pair of N-channel MOSFETs Q ₆ and Q ₈ and a pair of P-channel MOSFETs Q ₇ and Q ₉ , respectively. A sense amplifier SA provided corresponding to the data line pair, and a common data line pair CD provided corresponding to the plurality of data line pairs. ), The plurality of data line pairs and the common data line pair (CD, A column switch (C-SW) provided between the plurality of data line pairs and selectively coupling one of the plurality of data line pairs to the common data line pair, and a common data line precharge for setting the common data line pair to the intermediate level potential. A main circuit MA comprising a circuit PC ₂ and a CMOS latch circuit having a pair of N-channel MOSFETs and a pair of P-channel MOSFETs and for amplifying a potential difference applied to the common data line pair, Both the first and second word lines cross each of the data line pairs, and the data line precharge circuit has a source-drain path for shorting between one data line of the respective data line pairs and the other data line. Has a MOSFET (Q ₁₄ ), and the sense amplifier is a P-channel MOSFET provided on the side of the lie level potential of several CMOS latch circuits corresponding to the multiple data line pairs. Has made a power switch power switch (Q ₁₀₎ formed of N-channel MOSFET provided on the (Q ₁₂₎ and low-level voltage supply source In addition, the pair of N-channel type MOSFET (Q _6, Q ₈₎ is the low-level voltage supply source A pair of sources coupled to a power switch provided in common to the pair, a pair of gates receiving a potential of each data line pair, and a pair of drains, and the drain of one of the pair of N-channel MOSFETs and the other of the MOSFETs. The pair of P-channel MOSFETs Q ₇ and Q ₉ are formed by coupling gates to each other, and a pair of sources coupled to a power switch commonly provided on the high level potential side receives a pair of sources and potentials of each pair of data lines. It has a pair of gate and a pair of drain, Comprising: The drain of one MOSFET of the said pair of P-channel-type MOSFET, and the gate of the other MOSFET are combined, respectively, and the said The amplifier receives a potential generated in one data line coupled to a selected IMOS type dynamic memory cell of each data line pair and the mid-level potential of the other data line, amplifies the potential difference, and precharges the common data line precharge. The circuit PC ₂ has a MOSFET Q ₄₄ having a source-drain path for shorting between one common data line of the common data line pair and the other common data line, and the main amplifier is connected to the main amplifier. And a power switch composed of a P-channel MOSFET provided on the high level potential Vcc side of the CMOS latch circuit and a N-channel MOSFET provided on the low level potential Vss side. The pair of N-channel MOSFETs of a pair of source and the common data line pairs coupled to a power switch provided on the low level potential side A pair of gates receiving a potential and a pair of drains, and a drain wave of one of the pair of N-channel MOSFETs and a gate of the other MOSFET are coupled to each other, and the pair of gates in the main amplifier A P-channel MOSFET has a pair of sources coupled to a power switch provided on the high level potential side, a pair of gates and a pair of drains receiving the potential of the common data line pair, and one of the pair of P-channel MOSFETs. The drain and the gate of the other MOSFET are coupled to each other, and the column switch is operated after the sense amplifier is in operation and before the potential of each data line pair is amplified to the high level potential and the low level potential. The main amplifier then amplifies the potential of the common data line pair to the high level potential and the low level potential. The semiconductor memory device.